i965/cs: Initialize gl_LocalInvocationID from payload
authorJordan Justen <jordan.l.justen@intel.com>
Sat, 22 Nov 2014 03:14:41 +0000 (19:14 -0800)
committerJordan Justen <jordan.l.justen@intel.com>
Sun, 13 Sep 2015 16:53:16 +0000 (09:53 -0700)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
src/mesa/drivers/dri/i965/brw_cs.cpp
src/mesa/drivers/dri/i965/brw_fs.h

index d273f99c5ca0f374cc8a65f9733c8cba0d858030..9ee5ae52798f0416054a7e36a1e11f8a6a25a59d 100644 (file)
@@ -473,8 +473,9 @@ const struct brw_tracked_state brw_cs_state = {
  * Therefore, for SIMD8, we use 3 full registers, and for SIMD16 we use 6
  * registers worth of push constant space.
  *
- * Note: Any updates to brw_cs_prog_local_id_payload_dwords or
- * fill_local_id_payload need to coordinated.
+ * Note: Any updates to brw_cs_prog_local_id_payload_dwords,
+ * fill_local_id_payload or fs_visitor::emit_cs_local_invocation_id_setup need
+ * to coordinated.
  *
  * FINISHME: There are a few easy optimizations to consider.
  *
@@ -522,6 +523,26 @@ fill_local_id_payload(const struct brw_cs_prog_data *cs_prog_data,
 }
 
 
+fs_reg *
+fs_visitor::emit_cs_local_invocation_id_setup()
+{
+   assert(stage == MESA_SHADER_COMPUTE);
+
+   fs_reg *reg = new(this->mem_ctx) fs_reg(vgrf(glsl_type::uvec3_type));
+
+   struct brw_reg src =
+      brw_vec8_grf(payload.local_invocation_id_reg, 0);
+   src = retype(src, BRW_REGISTER_TYPE_UD);
+   bld.MOV(*reg, src);
+   src.nr += dispatch_width / 8;
+   bld.MOV(offset(*reg, bld, 1), src);
+   src.nr += dispatch_width / 8;
+   bld.MOV(offset(*reg, bld, 2), src);
+
+   return reg;
+}
+
+
 /**
  * Creates a region containing the push constants for the CS on gen7+.
  *
index c584cc70cb868e47d381eb06ad0ab4aa721221e5..6bfc29002a331973b48dd1827eeec366a4b261bb 100644 (file)
@@ -275,6 +275,7 @@ public:
    void emit_fb_writes();
    void emit_urb_writes();
    void emit_cs_terminate();
+   fs_reg *emit_cs_local_invocation_id_setup();
 
    void emit_barrier();