sim: v850: migrate to standard uintXX_t types

This old port setup its own uintXX types, but since we require C11
now, we can assume the standard uintXX_t types exist and use them.

diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index f450679aaf22dfdb2da7df9af5f27ec47e0154d8..88191481a86ad68245db011eaeab7b8cfbcdcbea 100644 (file)
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -170,7 +170,7 @@ get_insn_name (sim_cpu *cpu, int i)
 
 /* These default values correspond to expected usage for the chip.  */
 
-uint32 OP[4];
+uint32_t OP[4];
 
 static sim_cia
 v850_pc_get (sim_cpu *cpu)
@@ -315,13 +315,13 @@ sim_create_inferior (SIM_DESC      sd,
 static int
 v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 {
-  *(unsigned32*)memory = H2T_4 (State.regs[rn]);
+  *(uint32_t*)memory = H2T_4 (State.regs[rn]);
   return -1;
 }
 
 static int
 v850_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
 {
-  State.regs[rn] = T2H_4 (*(unsigned32 *) memory);
+  State.regs[rn] = T2H_4 (*(uint32_t *) memory);
   return length;
 }

diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index 792af5602199717668ba9a62dd86daca5325c1a2..49b845dfe7aec93cf3cdb1709d0bb1d2b2e6b1ee 100644 (file)
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -14,14 +14,8 @@
 #include "bfd.h"
 
 
-typedef signed8 int8;
-typedef unsigned8 uint8;
-typedef signed16 int16;
-typedef unsigned16 uint16;
-typedef signed32 int32;
-typedef unsigned32 uint32;
-typedef unsigned32 reg_t;
-typedef unsigned64 reg64_t;
+typedef uint32_t reg_t;
+typedef uint64_t reg64_t;
 
 
 /* The current state of the processor; registers, memory, etc.  */
@@ -62,7 +56,7 @@ extern SIM_DESC simulator;
    macro's that store the instruction where the old simops expects
    it. */
 
-extern uint32 OP[4];
+extern uint32_t OP[4];
 #if 0
 OP[0] = inst & 0x1f;           /* RRRRR -> reg1 */
 OP[1] = (inst >> 11) & 0x1f;   /* rrrrr -> reg2 */
@@ -444,11 +438,11 @@ enum op_types
 #ifdef DEBUG
 void trace_input (char *name, enum op_types type, int size);
 void trace_output (enum op_types result);
-void trace_result (int has_result, unsigned32 result);
+void trace_result (int has_result, uint32_t result);
 
 extern int trace_num_values;
-extern unsigned32 trace_values[];
-extern unsigned32 trace_pc;
+extern uint32_t trace_values[];
+extern uint32_t trace_pc;
 extern const char *trace_name;
 extern int trace_module;
 
@@ -542,7 +536,7 @@ do { \
 do { \
   if (TRACE_FPU_P (CPU)) \
     { \
-      unsigned64 f0; \
+      uint64_t f0; \
       sim_fpu_to64 (&f0, (V0)); \
       trace_input_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
     } \
@@ -552,7 +546,7 @@ do { \
 do { \
   if (TRACE_FPU_P (CPU)) \
     { \
-      unsigned64 f0, f1; \
+      uint64_t f0, f1; \
       sim_fpu_to64 (&f0, (V0)); \
       sim_fpu_to64 (&f1, (V1)); \
       trace_input_fp2 (SD, CPU, TRACE_FPU_IDX, f0, f1);        \
@@ -563,7 +557,7 @@ do { \
 do { \
   if (TRACE_FPU_P (CPU)) \
     { \
-      unsigned64 f0, f1, f2; \
+      uint64_t f0, f1, f2; \
       sim_fpu_to64 (&f0, (V0)); \
       sim_fpu_to64 (&f1, (V1)); \
       sim_fpu_to64 (&f2, (V2)); \
@@ -576,7 +570,7 @@ do { \
   if (TRACE_FPU_P (CPU)) \
     { \
       int d0 = (V0); \
-      unsigned64 f1, f2; \
+      uint64_t f1, f2; \
       TRACE_DATA *data = CPU_TRACE_DATA (CPU); \
       TRACE_IDX (data) = TRACE_FPU_IDX;        \
       sim_fpu_to64 (&f1, (V1)); \
@@ -597,7 +591,7 @@ do { \
 do { \
   if (TRACE_FPU_P (CPU)) \
     { \
-      unsigned64 f0; \
+      uint64_t f0; \
       sim_fpu_to64 (&f0, (R0));        \
       trace_result_fp1 (SD, CPU, TRACE_FPU_IDX, f0); \
     } \
@@ -639,15 +633,15 @@ do { \
 extern void divun ( unsigned int       N,
                    unsigned long int  als,
                    unsigned long int  sfi,
-                   unsigned32 /*unsigned long int*/ *  quotient_ptr,
-                   unsigned32 /*unsigned long int*/ *  remainder_ptr,
+                   uint32_t /*unsigned long int*/ *  quotient_ptr,
+                   uint32_t /*unsigned long int*/ *  remainder_ptr,
                    int *overflow_ptr
                    );
 extern void divn ( unsigned int       N,
                   unsigned long int  als,
                   unsigned long int  sfi,
-                  signed32 /*signed long int*/ *  quotient_ptr,
-                  signed32 /*signed long int*/ *  remainder_ptr,
+                  int32_t /*signed long int*/ *  quotient_ptr,
+                  int32_t /*signed long int*/ *  remainder_ptr,
                   int *overflow_ptr
                   );
 extern int type1_regs[];
@@ -667,7 +661,7 @@ extern int type3_regs[];
 #define SAT16(X)                       \
   do                                   \
     {                                  \
-      signed64 z = (X);                        \
+      int64_t z = (X);                 \
       if (z > 0x7fff)                  \
        {                               \
          SESR |= SESR_OV | SESR_SOV;   \
@@ -685,7 +679,7 @@ extern int type3_regs[];
 #define SAT32(X)                       \
   do                                   \
     {                                  \
-      signed64 z = (X);                        \
+      int64_t z = (X);                 \
       if (z > 0x7fffffff)              \
        {                               \
          SESR |= SESR_OV | SESR_SOV;   \
@@ -703,7 +697,7 @@ extern int type3_regs[];
 #define ABS16(X)                       \
   do                                   \
     {                                  \
-      signed64 z = (X) & 0xffff;       \
+      int64_t z = (X) & 0xffff;        \
       if (z == 0x8000)                 \
        {                               \
          SESR |= SESR_OV | SESR_SOV;   \
@@ -720,7 +714,7 @@ extern int type3_regs[];
 #define ABS32(X)                       \
   do                                   \
     {                                  \
-      signed64 z = (X) & 0xffffffff;   \
+      int64_t z = (X) & 0xffffffff;    \
       if (z == 0x80000000)             \
        {                               \
          SESR |= SESR_OV | SESR_SOV;   \

diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 1178721a975901e8d0e2d901b3b278636f0bc8de..8fac8bd9891124ffd3236fae87e069ca51bf2004 100644 (file)
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -49,9 +49,9 @@ int type3_regs[15] = { 2, 1, 0, 27, 26, 25, 24, 31, 30, 29, 28, 23, 22, 20, 21};
 #endif
 
 
-unsigned32   trace_values[3];
+uint32_t   trace_values[3];
 int          trace_num_values;
-unsigned32   trace_pc;
+uint32_t   trace_pc;
 const char * trace_name;
 int          trace_module;
 
@@ -190,7 +190,7 @@ trace_input (char *name, enum op_types type, int size)
 }
 
 void
-trace_result (int has_result, unsigned32 result)
+trace_result (int has_result, uint32_t result)
 {
   char buf[1000];
   char *chp;
@@ -415,7 +415,7 @@ fetch_argv (SIM_DESC sd, address_word addr)
 
   while (1)
     {
-      unsigned32 a = sim_core_read_4 (STATE_CPU (sd, 0),
+      uint32_t a = sim_core_read_4 (STATE_CPU (sd, 0),
                                      PC, read_map, addr + nr * 4);
       if (a == 0) break;
       buf[nr] = fetch_str (sd, a);
@@ -1669,7 +1669,7 @@ OP_10007E0 (void)
            buf = PARM1;
            RETVAL = pipe (host_fd);
            SW (buf, host_fd[0]);
-           buf += sizeof (uint16);
+           buf += sizeof (uint16_t);
            SW (buf, host_fd[1]);
            RETERR = errno;
          }
@@ -2017,8 +2017,8 @@ divun
   unsigned int       N,
   unsigned long int  als,
   unsigned long int  sfi,
-  unsigned32 /*unsigned long int*/ *  quotient_ptr,
-  unsigned32 /*unsigned long int*/ *  remainder_ptr,
+  uint32_t /*unsigned long int*/ *  quotient_ptr,
+  uint32_t /*unsigned long int*/ *  remainder_ptr,
   int *          overflow_ptr
 )
 {
@@ -2091,8 +2091,8 @@ divn
   unsigned int       N,
   unsigned long int  als,
   unsigned long int  sfi,
-  signed32 /*signed long int*/ *  quotient_ptr,
-  signed32 /*signed long int*/ *  remainder_ptr,
+  int32_t /*signed long int*/ *  quotient_ptr,
+  int32_t /*signed long int*/ *  remainder_ptr,
   int *          overflow_ptr
 )
 {
@@ -2188,8 +2188,8 @@ divn
 int
 OP_1C207E0 (void)
 {
-  unsigned32 /*unsigned long int*/  quotient;
-  unsigned32 /*unsigned long int*/  remainder;
+  uint32_t /*unsigned long int*/  quotient;
+  uint32_t /*unsigned long int*/  remainder;
   unsigned long int  divide_by;
   unsigned long int  divide_this;
   int            overflow = 0;
@@ -2223,8 +2223,8 @@ OP_1C207E0 (void)
 int
 OP_1C007E0 (void)
 {
-  signed32 /*signed long int*/  quotient;
-  signed32 /*signed long int*/  remainder;
+  int32_t /*signed long int*/  quotient;
+  int32_t /*signed long int*/  remainder;
   signed long int  divide_by;
   signed long int  divide_this;
   int          overflow = 0;
@@ -2234,8 +2234,8 @@ OP_1C007E0 (void)
 
   imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
 
-  divide_by   = (signed32) State.regs[ OP[0] ];
-  divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
+  divide_by   = (int32_t) State.regs[ OP[0] ];
+  divide_this = (int32_t) (State.regs[ OP[1] ] << imm5);
 
   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
   
@@ -2258,8 +2258,8 @@ OP_1C007E0 (void)
 int
 OP_18207E0 (void)
 {
-  unsigned32 /*unsigned long int*/  quotient;
-  unsigned32 /*unsigned long int*/  remainder;
+  uint32_t /*unsigned long int*/  quotient;
+  uint32_t /*unsigned long int*/  remainder;
   unsigned long int  divide_by;
   unsigned long int  divide_this;
   int            overflow = 0;
@@ -2293,8 +2293,8 @@ OP_18207E0 (void)
 int
 OP_18007E0 (void)
 {
-  signed32 /*signed long int*/  quotient;
-  signed32 /*signed long int*/  remainder;
+  int32_t /*signed long int*/  quotient;
+  int32_t /*signed long int*/  remainder;
   signed long int  divide_by;
   signed long int  divide_this;
   int          overflow = 0;
@@ -2305,7 +2305,7 @@ OP_18007E0 (void)
   imm5 = 32 - ((OP[3] & 0x3c0000) >> 17);
 
   divide_by   = EXTEND16 (State.regs[ OP[0] ]);
-  divide_this = (signed32) (State.regs[ OP[1] ] << imm5);
+  divide_this = (int32_t) (State.regs[ OP[1] ] << imm5);
 
   divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow);
   
@@ -2376,7 +2376,7 @@ OP_2C007E0 (void)
   
   /* Compute the result.  */
   
-  divide_by   = (signed32) State.regs[ OP[0] ];
+  divide_by   = (int32_t) State.regs[ OP[0] ];
   divide_this = State.regs[ OP[1] ];
   
   if (divide_by == 0)
@@ -2392,7 +2392,7 @@ OP_2C007E0 (void)
     }
   else
     {
-      divide_this = (signed32) divide_this;
+      divide_this = (int32_t) divide_this;
       State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
       State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
  
@@ -2477,7 +2477,7 @@ OP_28007E0 (void)
     }
   else
     {
-      divide_this = (signed32) divide_this;
+      divide_this = (int32_t) divide_this;
       State.regs[ OP[1]       ] = quotient  = divide_this / divide_by;
       State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by;
   
@@ -3378,12 +3378,12 @@ v850_satsub (SIM_DESC sd, unsigned int op0, unsigned int op1, unsigned int *op2p
   *op2p = result;
 }
 
-unsigned32
+uint32_t
 load_data_mem (SIM_DESC  sd,
               SIM_ADDR  addr,
               int       len)
 {
-  uint32 data;
+  uint32_t data;
 
   switch (len)
     {
@@ -3409,7 +3409,7 @@ void
 store_data_mem (SIM_DESC    sd,
                SIM_ADDR    addr,
                int         len,
-               unsigned32  data)
+               uint32_t  data)
 {
   switch (len)
     {

diff --git a/sim/v850/simops.h b/sim/v850/simops.h
index 1b6b4072f08278f56950993ae2a48a6984fb77fe..632febe5de55a77867245e5eac38e93256f90c5e 100644 (file)
--- a/sim/v850/simops.h
+++ b/sim/v850/simops.h
@@ -79,8 +79,8 @@ int OP_307E0 (void);
 int v850_float_compare(SIM_DESC sd, int cmp, sim_fpu wop1, sim_fpu wop2, int double_op_p);
 
 /* MEMORY ACCESS */
-unsigned32 load_data_mem(SIM_DESC sd, SIM_ADDR addr, int len);
-void store_data_mem(SIM_DESC sd, SIM_ADDR addr, int len, unsigned32 data);
+uint32_t load_data_mem(SIM_DESC sd, SIM_ADDR addr, int len);
+void store_data_mem(SIM_DESC sd, SIM_ADDR addr, int len, uint32_t data);
 
 unsigned long Add32 (unsigned long a1, unsigned long a2, int * carry);
 

diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index 41a9075a8e79448ee9bfb22422f5bb20bd1916a9..eb32c0f5ec33cf65783d7fd35562d04675d949c3 100644 (file)
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -220,7 +220,7 @@ rrrrr,11111100000 + wwwww,01101000010:XII:::bsh
 *v850e3v5
 "bsh r<reg2>, r<reg3>"
 {
-  unsigned32 value;
+  uint32_t value;
   TRACE_ALU_INPUT1 (GR[reg2]);
 
   value = (MOVED32 (GR[reg2], 23, 16, 31, 24)
@@ -249,7 +249,7 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 "bsw r<reg2>, r<reg3>"
 {
 #define WORDHASNULLBYTE(x) (((x) - 0x01010101) & ~(x)&0x80808080)
-  unsigned32 value;
+  uint32_t value;
   TRACE_ALU_INPUT1 (GR[reg2]);
 
   value = GR[reg2];
@@ -279,8 +279,8 @@ rrrrr,11111100000 + wwwww,01101000000:XII:::bsw
 *v850e3v5
 "callt <imm6>"
 {
-  unsigned32 adr;
-  unsigned32 off;
+  uint32_t adr;
+  uint32_t off;
   CTPC  = cia + 2;
   CTPSW = PSW;
   adr = (CTBP & ~1) + (imm6 << 1);
@@ -299,8 +299,8 @@ rrrrr,111111,RRRRR + wwwww,00011101110:IX:::caxi
 "caxi [reg1], reg2, reg3"
 {
   unsigned int z,s,cy,ov;
-  unsigned32 addr;
-  unsigned32 token,result;
+  uint32_t addr;
+  uint32_t token,result;
 
   addr = GR[reg1];
 
@@ -486,7 +486,7 @@ rrrrr,111111,RRRRR + wwwww,01011000000:XI:::div
 rrrrr!0,000010,RRRRR!0:I:::divh
 "divh r<reg1>, r<reg2>"
 {
-  unsigned32 ov, s, z;
+  uint32_t ov, s, z;
   signed long int op0, op1, result;
 
   trace_input ("divh", OP_REG_REG, 0);
@@ -511,7 +511,7 @@ rrrrr!0,000010,RRRRR!0:I:::divh
     }
   else
     {
-      result = (signed32) op1 / op0;
+      result = (int32_t) op1 / op0;
       ov = 0;
 
       /* Compute the condition codes.  */
@@ -714,7 +714,7 @@ rrrrr,11111100000 + wwwww,01101000110:XII:::hsh
 *v850e3v5
 "hsh r<reg2>, r<reg3>"
 {
-  unsigned32 value;
+  uint32_t value;
   TRACE_ALU_INPUT1 (GR[reg2]);
 
   value = 0xffff & GR[reg2];
@@ -738,7 +738,7 @@ rrrrr,11111100000 + wwwww,01101000100:XII:::hsw
 *v850e3v5
 "hsw r<reg2>, r<reg3>"
 {
-  unsigned32 value;
+  uint32_t value;
   TRACE_ALU_INPUT1 (GR[reg2]);
 
   value = GR[reg2];
@@ -844,8 +844,8 @@ rrrrr,111000,RRRRR + dddddddddddddddd:VII:::ld.b
 *v850e2v3
 *v850e3v5
 {
-  unsigned32 addr = GR[reg1] + disp23;
-  unsigned32 result = EXTEND8 (load_data_mem (sd, addr, 1));
+  uint32_t addr = GR[reg1] + disp23;
+  uint32_t result = EXTEND8 (load_data_mem (sd, addr, 1));
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -861,8 +861,8 @@ rrrrr,111001,RRRRR + ddddddddddddddd,0:VII:::ld.h
 *v850e3v5
 "ld.h <disp23>[r<reg1>], r<reg3>"
 {
-  unsigned32 addr = GR[reg1] + disp23;
-  unsigned32 result = EXTEND16 (load_data_mem (sd, addr, 2));
+  uint32_t addr = GR[reg1] + disp23;
+  uint32_t result = EXTEND16 (load_data_mem (sd, addr, 2));
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -878,8 +878,8 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 *v850e3v5
 "ld.w <disp23>[r<reg1>], r<reg3>"
 {
-  unsigned32 addr = GR[reg1] + disp23;
-  unsigned32 result = load_data_mem (sd, addr, 4);
+  uint32_t addr = GR[reg1] + disp23;
+  uint32_t result = load_data_mem (sd, addr, 4);
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -888,8 +888,8 @@ rrrrr,111001,RRRRR + ddddddddddddddd,1:VII:::ld.w
 *v850e3v5
 "ld.dw <disp23>[r<reg1>], r<reg3>"
 {
-  unsigned32 addr = GR[reg1] + disp23;
-  unsigned32 result = load_data_mem (sd, addr, 4);
+  uint32_t addr = GR[reg1] + disp23;
+  uint32_t result = load_data_mem (sd, addr, 4);
   GR[reg3] = result;
   TRACE_LD (addr, result);
   result = load_data_mem (sd, addr + 4, 4);
@@ -913,8 +913,8 @@ rrrrr!0,11110,b,RRRRR + ddddddddddddddd,1:VII:::ld.bu
 *v850e3v5
 "ld.bu <disp23>[r<reg1>], r<reg3>"
 { 
-  unsigned32 addr = GR[reg1] + disp23;
-  unsigned32 result = load_data_mem (sd, addr, 1);
+  uint32_t addr = GR[reg1] + disp23;
+  uint32_t result = load_data_mem (sd, addr, 1);
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -935,8 +935,8 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 *v850e3v5
 "ld.hu <disp23>[r<reg1>], r<reg3>"
 {
-  unsigned32 addr = GR[reg1] + disp23;
-  unsigned32 result = load_data_mem (sd, addr, 2);
+  uint32_t addr = GR[reg1] + disp23;
+  uint32_t result = load_data_mem (sd, addr, 2);
   GR[reg3] = result;
   TRACE_LD (addr, result);
 }
@@ -948,7 +948,7 @@ regID,111111,RRRRR + selID,00000100000:IX:::ldsr
 "ldsr r<reg1>, s<regID>":(selID == 0)
 "ldsr r<reg1>, s<regID>, <selID>"
 {
-  uint32 sreg = GR[reg1];
+  uint32_t sreg = GR[reg1];
   TRACE_ALU_INPUT1 (GR[reg1]);
 
   /* FIXME: For now we ignore the selID.  */
@@ -1911,8 +1911,8 @@ rrrrr,0110,ddddddd:IV:::sld.b
 "sld.bu <disp7>[ep], r<reg2>":(PSW & PSW_US)
 "sld.b <disp7>[ep], r<reg2>"
 {
-  unsigned32 addr = EP + disp7;
-  unsigned32 result = load_mem (addr, 1);
+  uint32_t addr = EP + disp7;
+  uint32_t result = load_mem (addr, 1);
   if (PSW & PSW_US)
     {
       GR[reg2] = result;
@@ -1930,8 +1930,8 @@ rrrrr,1000,ddddddd:IV:::sld.h
 "sld.hu <disp8>[ep], r<reg2>":(PSW & PSW_US)
 "sld.h <disp8>[ep], r<reg2>"
 {
-  unsigned32 addr = EP + disp8;
-  unsigned32 result = load_mem (addr, 2);
+  uint32_t addr = EP + disp8;
+  uint32_t result = load_mem (addr, 2);
   if (PSW & PSW_US)
     {
       GR[reg2] = result;
@@ -1948,8 +1948,8 @@ rrrrr,1000,ddddddd:IV:::sld.h
 rrrrr,1010,dddddd,0:IV:::sld.w
 "sld.w <disp8>[ep], r<reg2>"
 {
-  unsigned32 addr = EP + disp8;
-  unsigned32 result = load_mem (addr, 4);
+  uint32_t addr = EP + disp8;
+  uint32_t result = load_mem (addr, 4);
   GR[reg2] = result;
   TRACE_LD (addr, result);
 }
@@ -1963,8 +1963,8 @@ rrrrr!0,0000110,dddd:IV:::sld.bu
 "sld.b <disp4>[ep], r<reg2>":(PSW & PSW_US)
 "sld.bu <disp4>[ep], r<reg2>"
 {
-  unsigned32 addr = EP + disp4;
-  unsigned32 result = load_mem (addr, 1);
+  uint32_t addr = EP + disp4;
+  uint32_t result = load_mem (addr, 1);
   if (PSW & PSW_US)
     {
       result = EXTEND8 (result);
@@ -1987,8 +1987,8 @@ rrrrr!0,0000111,dddd:IV:::sld.hu
 "sld.h <disp5>[ep], r<reg2>":(PSW & PSW_US)
 "sld.hu <disp5>[ep], r<reg2>"
 {
-  unsigned32 addr = EP + disp5;
-  unsigned32 result = load_mem (addr, 2);
+  uint32_t addr = EP + disp5;
+  uint32_t result = load_mem (addr, 2);
   if (PSW & PSW_US)
     {
       result = EXTEND16 (result);
@@ -2035,7 +2035,7 @@ rrrrr,111010,RRRRR + dddddddddddddddd:VII:::st.b
 *v850e3v5
 "st.b r<reg3>, <disp23>[r<reg1>]"
 {
-  unsigned32 addr = GR[reg1] + disp23;
+  uint32_t addr = GR[reg1] + disp23;
   store_data_mem (sd, addr, 1, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
 }
@@ -2051,7 +2051,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,0:VII:::st.h
 *v850e3v5
 "st.h r<reg3>, <disp23>[r<reg1>]"
 {
-  unsigned32 addr = GR[reg1] + disp23;
+  uint32_t addr = GR[reg1] + disp23;
   store_data_mem (sd, addr, 2, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
 }
@@ -2067,7 +2067,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 *v850e3v5
 "st.w r<reg3>, <disp23>[r<reg1>]"
 {
-  unsigned32 addr = GR[reg1] + disp23;
+  uint32_t addr = GR[reg1] + disp23;
   store_data_mem (sd, addr, 4, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
 }
@@ -2076,7 +2076,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 *v850e3v5
 "st.dw r<reg3>, <disp23>[r<reg1>]"
 {
-  unsigned32 addr = GR[reg1] + disp23;
+  uint32_t addr = GR[reg1] + disp23;
   store_data_mem (sd, addr, 4, GR[reg3]);
   TRACE_ST (addr, GR[reg3]);
   store_data_mem (sd, addr + 4, 4, GR[reg3 + 1]);
@@ -2088,7 +2088,7 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 rrrrr,111111,regID + 0000000001000000:IX:::stsr
 "stsr s<regID>, r<reg2>"
 {
-  uint32 sreg = 0;
+  uint32_t sreg = 0;
 
   if ((idecode_issue == idecode_v850e2_issue
        || idecode_issue == idecode_v850e3v5_issue
@@ -2561,7 +2561,7 @@ rrrr,011111100100 + wwww,010001010100:F_I:::cvtf_dl
 *v850e3v5
 "cvtf.dl r<reg2e>, r<reg3e>"
 {
-  signed64 ans;
+  int64_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -2604,7 +2604,7 @@ rrrr,011111100100 + wwwww,10001010000:F_I:::cvtf_dw
 *v850e3v5
 "cvtf.dw r<reg2e>, r<reg3>"
 {
-  int32 ans;
+  int32_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -2626,11 +2626,11 @@ rrrr,011111100001 + wwww,010001010010:F_I:::cvtf_ld
 *v850e3v5
 "cvtf.ld r<reg2e>, r<reg3e>"
 {
-  signed64 op;
+  int64_t op;
   sim_fpu wop;
   sim_fpu_status status;
 
-  op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e];
+  op = ((int64_t)GR[reg2e+1] << 32L) | GR[reg2e];
   TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]);
 
   sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
@@ -2648,11 +2648,11 @@ rrrr,011111100001 + wwwww,10001000010:F_I:::cvtf_ls
 *v850e3v5
 "cvtf.ls r<reg2e>, r<reg3>"
 {
-  signed64 op;
+  int64_t op;
   sim_fpu wop;
   sim_fpu_status status;
 
-  op = ((signed64)GR[reg2e+1] << 32L) | GR[reg2e];
+  op = ((int64_t)GR[reg2e+1] << 32L) | GR[reg2e];
   TRACE_FP_INPUT_WORD2 (GR[reg2e], GR[reg2e+1]);
 
   sim_fpu_i64to (&wop, op, FPSR_GET_ROUND());
@@ -2689,7 +2689,7 @@ rrrrr,11111100100 + wwww,010001000100:F_I:::cvtf_sl
 *v850e3v5
 "cvtf.sl r<reg2>, r<reg3e>"
 {
-  signed64 ans;
+  int64_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -2712,7 +2712,7 @@ rrrrr,11111100100 + wwwww,10001000000:F_I:::cvtf_sw
 *v850e3v5
 "cvtf.sw r<reg2>, r<reg3>"
 {
-  int32 ans;
+  int32_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3449,7 +3449,7 @@ rrrr,011111100001 + wwww,010001010100:F_I:::trncf_dl
 *v850e3v5
 "trncf.dl r<reg2e>, r<reg3e>"
 {
-  signed64 ans;
+  int64_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3471,7 +3471,7 @@ rrrr,011111110001 + wwww,010001010100:F_I:::trncf_dul
 *v850e3v5
 "trncf.dul r<reg2e>, r<reg3e>"
 {
-  unsigned64 ans;
+  uint64_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3493,7 +3493,7 @@ rrrr,011111100001 + wwwww,10001010000:F_I:::trncf_dw
 *v850e3v5
 "trncf.dw r<reg2e>, r<reg3>"
 {
-  int32 ans;
+  int32_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3514,7 +3514,7 @@ rrrr,011111110001 + wwwww,10001010000:F_I:::trncf_duw
 *v850e3v5
 "trncf.duw r<reg2e>, r<reg3>"
 {
-  uint32 ans;
+  uint32_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3535,7 +3535,7 @@ rrrrr,11111100001 + wwww,010001000100:F_I:::trncf_sl
 *v850e3v5
 "trncf.sl r<reg2>, r<reg3e>"
 {
-  signed64 ans;
+  int64_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3555,7 +3555,7 @@ rrrrr,11111110001 + wwww,010001000100:F_I:::trncf_sul
 *v850e3v5
 "trncf.sul r<reg2>, r<reg3e>"
 {
-  unsigned64 ans;
+  uint64_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3575,7 +3575,7 @@ rrrrr,11111100001 + wwwww,10001000000:F_I:::trncf_sw
 *v850e3v5
 "trncf.sw r<reg2>, r<reg3>"
 {
-  int32 ans;
+  int32_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3596,7 +3596,7 @@ rrrrr,11111110001 + wwwww,10001000000:F_I:::trncf_suw
 *v850e3v5
 "trncf.suw r<reg2>, r<reg3>"
 {
-  uint32 ans;
+  uint32_t ans;
   sim_fpu wop;
   sim_fpu_status status;
 
@@ -3808,7 +3808,7 @@ rrrr,011111100000+0000011011011000:C:::modadd
 "modadd r<reg2e>"
 {
   reg_t r;
-  int32 inc;
+  int32_t inc;
   reg_t max;
 
   TRACE_ALU_INPUT1 (GR[reg2e]);