Addressed review comments

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c66e1d750b0d96982b3a6ecb3085b7781dd58680..90ab688e5400f568f361de9d85ae490e13a7bb68 100644 (file)
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -85,7 +85,8 @@ struct SynthXilinxPass : public ScriptPass
                log("        do not use DSP48E1s to implement multipliers and associated logic\n");
                log("\n");
                log("    -noiopad\n");
-               log("        disable I/O buffer insertion\n");
+               log("        disable I/O buffer insertion (useful for hierarchical or \n");
+               log("        out-of-context flows)\n");
                log("\n");
                log("    -noclkbuf\n");
                log("        disable automatic clock buffer insertion\n");
@@ -210,7 +211,7 @@ struct SynthXilinxPass : public ScriptPass
                        }
                        if (args[argidx] == "-iopad") {
                                continue;
-                       }                       
+                       }
                        if (args[argidx] == "-noiopad") {
                                noiopad = true;
                                continue;

diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys
index 55e20c37b70fbf1df6b1f1f0ebbfe3f220420d5f..eaccab1269d436912cd5931ab2576e73126c70d1 100644 (file)
--- a/tests/arch/xilinx/tribuf.ys
+++ b/tests/arch/xilinx/tribuf.ys
@@ -7,7 +7,6 @@ synth
 equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd tristate # Constrain all select calls below inside the top module
-# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225
 select -assert-count 2 t:IBUF
 select -assert-count 1 t:INV
 select -assert-count 1 t:OBUFT