Add [script] documentation, add some paragraphs on "verific" command

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/docs/source/reference.rst b/docs/source/reference.rst
index e62e30e5f1a988be4b7da0d3b582f66ec5171a2b..1a6191775310532facab82d06c71dc50b4af3b7b 100644 (file)
--- a/docs/source/reference.rst
+++ b/docs/source/reference.rst
@@ -279,7 +279,28 @@ implementing the solver.
 Script section
 --------------
 
-TBD
+The ``[script]`` section contains the Yosys script that reads and elaborates
+the design under test. For example, for a simple project contained in a single
+design file ``mytest.sv`` with the top-module ``mytest``:
+
+.. code-block:: text
+
+   [script]
+   read_verilog -sv mytest.sv
+   prep -top mytest
+
+Or using the Verific SystemVerilog parser:
+
+.. code-block:: text
+
+   [script]
+   verific -sv mytest.sv
+   verific -import mytest
+   prep -top mytest
+
+Run ``yosys`` in a terminal window and enter ``help`` on the Yosys prompt
+for a command list. Run ``help <command>`` for a detailed description of the
+command, for example ``help prep``.
 
 Files section
 -------------

diff --git a/docs/source/verific.rst b/docs/source/verific.rst
index 4ea9c6768ac4961e56fa8520c05b692ba3aa372c..aa79f220388c7f7aeabdcd7893c471ee0e2e6b2a 100644 (file)
--- a/docs/source/verific.rst
+++ b/docs/source/verific.rst
@@ -2,15 +2,15 @@
 SystemVerilog, VHDL, SVA
 ========================
 
-TBD
+Run ``verific -sv <files>`` in the ``[script]`` section of you ``.sby`` file
+to read a SystemVerilog source file, and ``verific -vhdl <files>`` to read a
+VHDL source file.
 
-``verific -sv <files>``
+After all source files have been read, run ``verific -import <topmodule>``
+to import the design elaborated at the specified top module.
 
-``verific -vhdl <files>``
-
-``verific -import <top>``
-
-TBD
+Run ``yosys -h verific`` in a terminal window and enter for more information
+on the ``verific`` script command.
 
 Supported SVA Property Syntax
 -----------------------------