i2c/uart: Name the synchronizers

diff --git a/src/main/scala/devices/i2c/I2CPins.scala b/src/main/scala/devices/i2c/I2CPins.scala
index 2e294238d0b5286b1c50a2407aa1a8d5331f0f08..9bbc57605dd2ca6976912328659d99192ba5cf61 100644 (file)
--- a/src/main/scala/devices/i2c/I2CPins.scala
+++ b/src/main/scala/devices/i2c/I2CPins.scala
@@ -18,11 +18,13 @@ class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
     withClockAndReset(clock, reset) {
       scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
       scl.o.oe := i2c.scl.oe
-      i2c.scl.in := SynchronizerShiftRegInit(scl.i.ival, syncStages, init = Bool(true))
+      i2c.scl.in := SynchronizerShiftRegInit(scl.i.ival, syncStages, init = Bool(true),
+        name = Some("i2c_scl_sync"))
 
       sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
       sda.o.oe := i2c.sda.oe
-      i2c.sda.in := SynchronizerShiftRegInit(sda.i.ival, syncStages, init = Bool(true))
+      i2c.sda.in := SynchronizerShiftRegInit(sda.i.ival, syncStages, init = Bool(true),
+        name = Some("i2c_sda_sync"))
     }
   }
 }

diff --git a/src/main/scala/devices/uart/UARTPeriphery.scala b/src/main/scala/devices/uart/UARTPeriphery.scala
index f24cbadcdf2a1d39a5848797a40476f7a50b9dfe..01ae55cd9ea18d47401e71ab0c6a94e3b3bd1c48 100644 (file)
--- a/src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/src/main/scala/devices/uart/UARTPeriphery.scala
@@ -51,7 +51,7 @@ class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
     withClockAndReset(clock, reset) {
       txd.outputPin(uart.txd)
       val rxd_t = rxd.inputPin()
-      uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true))
+      uart.rxd := SynchronizerShiftRegInit(rxd_t, n = syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
     }
   }
 }