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rs6000.md (mov<mode>_softfloat, FMOVE32): Reformat alternatives and attributes so...
authorMichael Meissner <meissner@linux.vnet.ibm.com>
Fri, 11 May 2018 22:47:03 +0000 (22:47 +0000)
committerMichael Meissner <meissner@gcc.gnu.org>
Fri, 11 May 2018 22:47:03 +0000 (22:47 +0000)
2018-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>

* config/rs6000/rs6000.md (mov<mode>_softfloat, FMOVE32):
Reformat alternatives and attributes so it is easier to identify
which constraints/attributes go with which instruction.
(mov<mode>_hardfloat32, FMOVE64): Likewise.
(mov<mode>_softfloat32, FMOVE64): Likewise.
(mov<mode>_hardfloat64, FMOVE64): Likewise.
(mov<mode>_softfloat64, FMOVE64): Likewise.

From-SVN: r260190

gcc/ChangeLog patch | blob | history
gcc/config/rs6000/rs6000.md patch | blob | history

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index bda74308a9ebaade360bfd3bd9fef768ab933670..92dc3f4f68ffff8e2f74a3ade98d7aa743e7cf7f 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,13 @@
+2018-05-11  Michael Meissner  <meissner@linux.vnet.ibm.com>
+
+       * config/rs6000/rs6000.md (mov<mode>_softfloat, FMOVE32):
+       Reformat alternatives and attributes so it is easier to identify
+       which constraints/attributes go with which instruction.
+       (mov<mode>_hardfloat32, FMOVE64): Likewise.
+       (mov<mode>_softfloat32, FMOVE64): Likewise.
+       (mov<mode>_hardfloat64, FMOVE64): Likewise.
+       (mov<mode>_softfloat64, FMOVE64): Likewise.
+
 2018-05-11  Kelvin Nilsen  <kelvin@gcc.gnu.org>
 
        * doc/extend.texi (PowerPC Built-in Functions): Rename this
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 253d3f24f95132181e1c8e988bd670c819dbe207..b249a1f1ca7206114b02263efb8c05b85f878d44 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7154,9 +7154,17 @@
        "load,       fpload,    store,     fpstore,   mffgpr,    mftgpr,
         fpsimple,   *,         mtjmpr,    mfjmpr,    *")])
 
+;;     MR           MT%0       MF%0       LWZ        STW        LI
+;;     LIS          G-const.   F/n-const  NOP
 (define_insn "*mov<mode>_softfloat"
-  [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
-       (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
+  [(set (match_operand:FMOVE32 0 "nonimmediate_operand"
+       "=r,         cl,        r,         r,         m,         r,
+          r,         r,         r,         *h")
+
+       (match_operand:FMOVE32 1 "input_operand"
+        "r,         r,         h,         m,         r,         I,
+          L,         G,         Fn,        0"))]
+
   "(gpc_reg_operand (operands[0], <MODE>mode)
    || gpc_reg_operand (operands[1], <MODE>mode))
    && TARGET_SOFT_FLOAT"
@@ -7171,8 +7179,13 @@
    #
    #
    nop"
-  [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
-   (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
+  [(set_attr "type"
+       "*,          mtjmpr,    mfjmpr,    load,      store,     *,
+         *,          *,         *,         *")
+
+   (set_attr "length"
+       "4,          4,         4,         4,         4,         4,
+         4,          4,         8,         4")])
 
 ;; Like movsf, but adjust a SI value to be used in a SF context, i.e.
 ;; (set (reg:SF ...) (subreg:SF (reg:SI ...) 0))
@@ -7335,9 +7348,22 @@
 ;; If we have FPR registers, rs6000_emit_move has moved all constants to memory,
 ;; except for 0.0 which can be created on VSX with an xor instruction.
 
+;;           STFD         LFD         FMR         LXSD        STXSD
+;;           LXSD         STXSD       XXLOR       XXLXOR      GPR<-0
+;;           LWZ          STW         MR
+
+
 (define_insn "*mov<mode>_hardfloat32"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
-       (match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+            "=m,          d,          d,          <f64_p9>,   wY,
+              <f64_av>,   Z,          <f64_vsx>,  <f64_vsx>,  !r,
+              Y,          r,          !r")
+
+       (match_operand:FMOVE64 1 "input_operand"
+             "d,          m,          d,          wY,         <f64_p9>,
+              Z,          <f64_av>,   <f64_vsx>,  <zero_fp>,  <zero_fp>,
+              r,          Y,          r"))]
+
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7355,25 +7381,57 @@
    #
    #
    #"
-  [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two")
+  [(set_attr "type"
+            "fpstore,     fpload,     fpsimple,   fpload,     fpstore,
+             fpload,      fpstore,    veclogical, veclogical, two,
+             store,       load,       two")
+
    (set_attr "size" "64")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")])
+   (set_attr "length"
+            "4,           4,          4,          4,          4,
+             4,           4,          4,          4,          8,
+             8,           8,          8")])
+
+;;           STW      LWZ     MR      G-const H-const F-const
 
 (define_insn "*mov<mode>_softfloat32"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
-       (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+           "=Y,       r,      r,      r,      r,      r")
+
+       (match_operand:FMOVE64 1 "input_operand"
+            "r,       Y,      r,      G,      H,      F"))]
+
   "!TARGET_POWERPC64
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
   "#"
-  [(set_attr "type" "store,load,two,*,*,*")
-   (set_attr "length" "8,8,8,8,12,16")])
+  [(set_attr "type"
+            "store,   load,   two,    *,      *,      *")
+
+   (set_attr "length"
+             "8,      8,      8,      8,      12,     16")])
 
 ; ld/std require word-aligned displacements -> 'Y' constraint.
 ; List Y->r and r->Y before r->r for reload.
+
+;;           STFD         LFD         FMR         LXSD        STXSD
+;;           LXSDX        STXSDX      XXLOR       XXLXOR      LI 0
+;;           STD          LD          MR          MT{CTR,LR}  MF{CTR,LR}
+;;           NOP          MFTGPR      MFFGPR      MFVSRD      MTVSRD
+
 (define_insn "*mov<mode>_hardfloat64"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
-       (match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+           "=m,           d,          d,          <f64_p9>,   wY,
+             <f64_av>,    Z,          <f64_vsx>,  <f64_vsx>,  !r,
+             Y,           r,          !r,         *c*l,       !r,
+            *h,           r,          wg,         r,          <f64_dm>")
+
+       (match_operand:FMOVE64 1 "input_operand"
+            "d,           m,          d,          wY,         <f64_p9>,
+             Z,           <f64_av>,   <f64_vsx>,  <zero_fp>,  <zero_fp>,
+             r,           Y,          r,          r,          h,
+             0,           wg,         r,          <f64_dm>,   r"))]
+
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7398,13 +7456,27 @@
    mffgpr %0,%1
    mfvsrd %0,%x1
    mtvsrd %x0,%1"
-  [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
+  [(set_attr "type"
+            "fpstore,     fpload,     fpsimple,   fpload,     fpstore,
+             fpload,      fpstore,    veclogical, veclogical, integer,
+             store,       load,       *,          mtjmpr,     mfjmpr,
+             *,           mftgpr,     mffgpr,     mftgpr,    mffgpr")
+
    (set_attr "size" "64")
    (set_attr "length" "4")])
 
+;;           STD      LD       MR      MT<SPR> MF<SPR> G-const
+;;           H-const  F-const  Special
+
 (define_insn "*mov<mode>_softfloat64"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
-       (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+           "=Y,       r,      r,      cl,     r,      r,
+             r,       r,      *h")
+
+       (match_operand:FMOVE64 1 "input_operand"
+            "r,       Y,      r,      r,      h,      G,
+             H,       F,      0"))]
+
   "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7418,8 +7490,13 @@
    #
    #
    nop"
-  [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
-   (set_attr "length" "4,4,4,4,4,8,12,16,4")])
+  [(set_attr "type"
+            "store,   load,   *,      mtjmpr, mfjmpr, *,
+             *,       *,      *")
+
+   (set_attr "length"
+            "4,       4,      4,      4,      4,      8,
+             12,      16,     4")])
 \f
 (define_expand "mov<mode>"
   [(set (match_operand:FMOVE128 0 "general_operand")