sparc: Add some missing M5_FALLTHROUGHs and breaks.

These fix what I believe are some bugs, and also some gcc warnings.

Change-Id: I5fb2a1b2f0ef3643b25aaf0c29c096996ef98ec0
Reviewed-on: https://gem5-review.googlesource.com/9402
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>

diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index f6b941e2d42dc76c54107b7f443e212b91a0f10a..3456029c4369cad06536207f3bcd41f58c26e792 100644 (file)
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -480,6 +480,7 @@ ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
         break;
       case MISCREG_HINTP:
         hintp = val;
+        break;
       case MISCREG_HTBA:
         htba = val;
         break;

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index f4564c6fd92588d0672ab863048057836b79cabc..49b353a7cd092bba1c5803d3eaa3fceeb13659da 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -36,6 +36,7 @@
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/registers.hh"
 #include "base/bitfield.hh"
+#include "base/compiler.hh"
 #include "base/trace.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
@@ -1155,6 +1156,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         break;
       case ASI_ITLB_DATA_ACCESS_REG:
         entry_insert = bits(va, 8,3);
+        M5_FALLTHROUGH;
       case ASI_ITLB_DATA_IN_REG:
         assert(entry_insert != -1 || mbits(va,10,9) == va);
         ta_insert = itb->tag_access;
@@ -1169,6 +1171,7 @@ TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
         break;
       case ASI_DTLB_DATA_ACCESS_REG:
         entry_insert = bits(va, 8,3);
+        M5_FALLTHROUGH;
       case ASI_DTLB_DATA_IN_REG:
         assert(entry_insert != -1 || mbits(va,10,9) == va);
         ta_insert = tag_access;

diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 274301b3704f829d332b4d54b1306a8d231bbc2a..d8af29b918dd083152b2f05e348a37b9f15d2df7 100644 (file)
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -137,6 +137,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
 
       case MISCREG_PSTATE:
         setMiscRegNoEffect(miscReg, val);
+        break;
 
       case MISCREG_PIL:
         setMiscRegNoEffect(miscReg, val);