crg: support for resetless system clock domain

diff --git a/mibuild/crg.py b/mibuild/crg.py
index 83ae9c4e570c09f27f84d4054cdcc6b5fdfe683f..7b5799f36556a3e89ff8d37771ea6e60774d3a95 100644 (file)
--- a/mibuild/crg.py
+++ b/mibuild/crg.py
@@ -3,11 +3,13 @@ from migen.fhdl.module import Module
 
 class SimpleCRG(Module):
        def __init__(self, platform, clk_name, rst_name, rst_invert=False):
+                       reset_less = rst_name is None
+                       self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
                        self._clk = platform.request(clk_name)
-                       self._rst = platform.request(rst_name)
-                       self.clock_domains.cd_sys = ClockDomain()
                        self.comb += self.cd_sys.clk.eq(self._clk)
-                       if rst_invert:
-                               self.comb += self.cd_sys.rst.eq(~self._rst)
-                       else:
-                               self.comb += self.cd_sys.rst.eq(self._rst)
+
+                       if not reset_less:
+                               if rst_invert:
+                                       self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
+                               else:
+                                       self.comb += self.cd_sys.rst.eq(platform.request(rst_name))

diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 85d277122a54fbdbf81950ed0abeb05d1f01c59a..d6ac47291a3c0e127487a14f50b0506a96f68311 100644 (file)
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -21,18 +21,20 @@ class CRG_SE(SimpleCRG):
 
 class CRG_DS(Module):
        def __init__(self, platform, clk_name, rst_name, period, rst_invert=False):
-               self.clock_domains.cd_sys = ClockDomain()
+               reset_less = rst_name is None
+               self.clock_domains.cd_sys = ClockDomain(reset_less=reset_less)
                self._clk = platform.request(clk_name)
-               if rst_invert:
-                       self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
-               else:
-                       self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
                _add_period_constraint(platform, self._clk.p, period)
                self.specials += Instance("IBUFGDS",
                        Instance.Input("I", self._clk.p),
                        Instance.Input("IB", self._clk.n),
                        Instance.Output("O", self.cd_sys.clk)
                )
+               if not reset_less:
+                       if rst_invert:
+                               self.comb += self.cd_sys.rst.eq(~platform.request(rst_name))
+                       else:
+                               self.comb += self.cd_sys.rst.eq(platform.request(rst_name))
 
 def _format_constraint(c):
        if isinstance(c, Pins):