extend table with SVP64

diff --git a/openpower/sv/comparison_table.mdwn b/openpower/sv/comparison_table.mdwn
index e9f20e1a8cd00cbde4d02aa773fc21079baee4f8..1881b1623e777852fb126071917bbeacdfc984a2 100644 (file)
--- a/openpower/sv/comparison_table.mdwn
+++ b/openpower/sv/comparison_table.mdwn
@@ -2,6 +2,12 @@
 
 | Name | Num of <br />opcodes | Scalable | Predicate <br /> Masks | Twin <br /> Predication |  Explicit <br /> Vector regs | 128-bit | Bigint <br /> capability | LDST <br /> Fault-First | Data-dependent <br /> Fail-first | Predicate-<br /> Result |
 |------|----------------------|----------|------------------------|-------------------------|------------------------------|---------|--------------------------|-------------------------|----------------------------------|-------------------------|
-| SVP64| 5 (plus prefixing)   | yes      | yes                    | yes[1]                  | no[2]                        | n/a[3]  | yes[4]                   | yes[5]                  | yes[6]                           | yes[7]                  |
+| SVP64| 5 (plus prefixing)   | yes      | yes                    | yes{1}                  | no{2}                        | n/a{3}  | yes{4}                   | yes{5}                  | yes{6}                           | yes{7}                  |
 
-[1]: only on some operations
+* {1}: on specific operations.
+* {2}: SVP64 provides the Vector register concept on top of the *Scalar* GPR, FPR and CR register files
+* {3}: SVP64 Vectorises Scalar instructions. When applied to e.g. VSX QP instructions, SVP64 "gains" 128-bit.
+* {4}: big-integer add is just `sv.adde`. Mul and divide require addition of two scalar operations
+* {5} See [[sv/svp64/appendix]]
+* {6} Based on LD/ST Fail-first, extended to data. See [[sv/svp64/appendix]]
+* {7} Turns standard ops into a type of "cmp". See [[sv/svp64/appendix]]