Remove undriven reset signals

diff --git a/milkymist/dvisampler/clocking.py b/milkymist/dvisampler/clocking.py
index dcc2443e7c051b3b3c026653bfe17091c2224a94..be7f833f1c4f8a38162c528c1838e1b5cbaebb63 100644 (file)
--- a/milkymist/dvisampler/clocking.py
+++ b/milkymist/dvisampler/clocking.py
@@ -13,8 +13,8 @@ class Clocking(Module, AutoCSR):
                self.serdesstrobe = Signal()
                self.clock_domains._cd_pix = ClockDomain()
                self.clock_domains._cd_pix5x = ClockDomain()
-               self.clock_domains._cd_pix10x = ClockDomain()
-               self.clock_domains._cd_pix20x = ClockDomain()
+               self.clock_domains._cd_pix10x = ClockDomain(reset_less=True)
+               self.clock_domains._cd_pix20x = ClockDomain(reset_less=True)
 
                ###
 

diff --git a/milkymist/m1crg/__init__.py b/milkymist/m1crg/__init__.py
index 7779cf4ec4b1eae11a7dea45b632a35cd373315a..9e1511f6c4e478135fed6f770ac02408f4f8ca21 100644 (file)
--- a/milkymist/m1crg/__init__.py
+++ b/milkymist/m1crg/__init__.py
@@ -13,7 +13,7 @@ class M1CRG(Module, AutoCSR):
                self.clock_domains.cd_sys4x_rd = ClockDomain()
                self.clock_domains.cd_eth_rx = ClockDomain()
                self.clock_domains.cd_eth_tx = ClockDomain()
-               self.clock_domains.cd_vga = ClockDomain()
+               self.clock_domains.cd_vga = ClockDomain(reset_less=True)
 
                self.clk4x_wr_strb = Signal()
                self.clk4x_rd_strb = Signal()