/*
- * Copyright (c) 2011-2012,2016-2017, 2019 ARM Limited
+ * Copyright (c) 2011-2012,2016-2017, 2019-2020 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include "sim/clocked_object.hh"
#include "sim/full_system.hh"
#include "sim/process.hh"
+#include "sim/root.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
#include "sim/system.hh"
using namespace std;
+std::unique_ptr<BaseCPU::GlobalStats> BaseCPU::globalStats;
+
vector<BaseCPU *> BaseCPU::cpuList;
// This variable reflects the max number of threads in any CPU. Be
{
ClockedObject::regStats();
+ if (!globalStats) {
+ /* We need to construct the global CPU stat structure here
+ * since it needs a pointer to the Root object. */
+ globalStats.reset(new GlobalStats(Root::root()));
+ }
+
using namespace Stats;
numCycles
{
return params()->wait_for_remote_gdb;
}
+
+
+BaseCPU::GlobalStats::GlobalStats(::Stats::Group *parent)
+ : ::Stats::Group(parent),
+ simInsts(this, "sim_insts", "Number of instructions simulated"),
+ simOps(this, "sim_ops", "Number of ops (including micro ops) simulated"),
+ hostInstRate(this, "host_inst_rate",
+ "Simulator instruction rate (inst/s)"),
+ hostOpRate(this, "host_op_rate",
+ "Simulator op (including micro ops) rate (op/s)")
+{
+ simInsts
+ .functor(BaseCPU::numSimulatedInsts)
+ .precision(0)
+ .prereq(simInsts)
+ ;
+
+ simOps
+ .functor(BaseCPU::numSimulatedOps)
+ .precision(0)
+ .prereq(simOps)
+ ;
+
+ hostInstRate
+ .precision(0)
+ .prereq(simInsts)
+ ;
+
+ hostOpRate
+ .precision(0)
+ .prereq(simOps)
+ ;
+
+ hostInstRate = simInsts / hostSeconds;
+ hostOpRate = simOps / hostSeconds;
+}
/** Cache the cache line size that we get from the system */
const unsigned int _cacheLineSize;
+ /** Global CPU statistics that are merged into the Root object. */
+ struct GlobalStats : public Stats::Group {
+ GlobalStats(::Stats::Group *parent);
+
+ ::Stats::Value simInsts;
+ ::Stats::Value simOps;
+
+ ::Stats::Formula hostInstRate;
+ ::Stats::Formula hostOpRate;
+ };
+
+ /**
+ * Pointer to the global stat structure. This needs to be
+ * constructed from regStats since we merge it into the root
+ * group. */
+ static std::unique_ptr<GlobalStats> globalStats;
+
public:
/**
#include "base/hostinfo.hh"
#include "base/statistics.hh"
#include "base/time.hh"
-#include "config/the_isa.hh"
-#if THE_ISA != NULL_ISA
-#include "cpu/base.hh"
-#endif
#include "sim/global_event.hh"
using namespace std;
Stats::Value simTicks;
Stats::Value finalTick;
Stats::Value simFreq;
+Stats::Value hostSeconds;
namespace Stats {
struct Global
{
- Stats::Formula hostInstRate;
- Stats::Formula hostOpRate;
Stats::Formula hostTickRate;
Stats::Value hostMemory;
- Stats::Value hostSeconds;
-
- Stats::Value simInsts;
- Stats::Value simOps;
Global();
};
Global::Global()
{
- simInsts
- .name("sim_insts")
- .desc("Number of instructions simulated")
- .precision(0)
- .prereq(simInsts)
- ;
-
- simOps
- .name("sim_ops")
- .desc("Number of ops (including micro ops) simulated")
- .precision(0)
- .prereq(simOps)
- ;
-
-#if THE_ISA != NULL_ISA
- simInsts.functor(BaseCPU::numSimulatedInsts);
- simOps.functor(BaseCPU::numSimulatedOps);
-#else
- simInsts.functor([] { return 0; });
- simOps.functor([] { return 0; });
-#endif
-
simSeconds
.name("sim_seconds")
.desc("Number of seconds simulated")
"(restored from checkpoints and never reset)")
;
- hostInstRate
- .name("host_inst_rate")
- .desc("Simulator instruction rate (inst/s)")
- .precision(0)
- .prereq(simInsts)
- ;
-
- hostOpRate
- .name("host_op_rate")
- .desc("Simulator op (including micro ops) rate (op/s)")
- .precision(0)
- .prereq(simOps)
- ;
-
hostMemory
.functor(memUsage)
.name("host_mem_usage")
;
simSeconds = simTicks / simFreq;
- hostInstRate = simInsts / hostSeconds;
- hostOpRate = simOps / hostSeconds;
hostTickRate = simTicks / hostSeconds;
registerResetCallback([]() {
extern Stats::Formula simSeconds;
extern Stats::Value simTicks;
extern Stats::Value simFreq;
+extern Stats::Value hostSeconds;
#endif // __SIM_SIM_STATS_HH__