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Added English Language description for lfsu instruction
author
Shriya Sharma
<shriya@redsemiconductor.com>
Tue, 3 Oct 2023 10:22:54 +0000
(11:22 +0100)
committer
Luke Kenneth Casson Leighton
<lkcl@lkcl.net>
Fri, 22 Dec 2023 19:26:21 +0000
(19:26 +0000)
openpower/isa/fpload.mdwn
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diff --git
a/openpower/isa/fpload.mdwn
b/openpower/isa/fpload.mdwn
index 9e16cc9ed96e8a261d69912a35edca57491b5525..e4d969608a0d44e01e0db4391eda8071b8d9ed3c 100644
(file)
--- a/
openpower/isa/fpload.mdwn
+++ b/
openpower/isa/fpload.mdwn
@@
-61,6
+61,19
@@
Pseudo-code:
FRT <- DOUBLE(MEM(EA, 4))
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum (RA)+D.
+
+ The word in storage addressed by EA is interpreted as
+ a floating-point single-precision operand. This word is
+ converted to floating-point double format (see
+ page 138) and placed into register FRT.
+
+ EA is placed into register RA.
+
+ If RA=0, the instruction form is invalid.
+
Special Registers Altered:
None