i965/blorp: Fix hiz ops on MSAA surfaces

Two things were broken here:
- The depth/stencil surface dimensions were broken for MSAA.
- Sample count was programmed incorrectly.

Result was the depth resolve didn't work correctly on MSAA surfaces, and
so sampling the surface later produced garbage.

Fixes the new piglit test arb_texture_multisample-sample-depth, and
various artifacts in 'tesseract' with msaa=4 glineardepth=0.

Fixes freedesktop bug #76396.

Not observed any piglit regressions on Haswell.

v2: Just set brw_hiz_op_params::dst.num_samples rather than adding a
    helper function (Ken).

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
v3: moved the alignment needed for hiz+msaa to brw_blorp.cpp, as
    suggested by Chad Versace (Alejandro Piñeiro on behalf of Chris
    Forbes)

Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 1bc6d15969fa6feca539aa142d0c26fb793f1a79..4497eab3bf0dc01a4065c4250ecb6167ce936c0b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -319,8 +319,14 @@ brw_hiz_op_params::brw_hiz_op_params(struct intel_mipmap_tree *mt,
     * not 8. But commit 1f112cc increased the alignment from 4 to 8, which
     * prevents the clobbering.
     */
-   depth.width = ALIGN(depth.width, 8);
-   depth.height = ALIGN(depth.height, 4);
+   dst.num_samples = mt->num_samples;
+   if (dst.num_samples > 1) {
+      depth.width = ALIGN(mt->logical_width0, 8);
+      depth.height = ALIGN(mt->logical_height0, 4);
+   } else {
+      depth.width = ALIGN(depth.width, 8);
+      depth.height = ALIGN(depth.height, 4);
+   }
 
    x1 = depth.width;
    y1 = depth.height;