fix urls

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index 2f208d36d1e1b630ca417bfb652f1cc40183560e..b6f53bb0073015aba07fd765dd052507c8d67e46 100644 (file)
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -421,7 +421,7 @@ uint_xlen_t bmextrev(RA, RB, sh)
 
 # grevlut
 
-([3x lower latency alternative](bitmanip/grev_gorc_design.mdwn))
+([3x lower latency alternative](grev_gorc_design/))
 
 generalised reverse combined with a pair of LUT2s and allowing
 a constant `0b0101...0101` when RA=0, and an option to invert

diff --git a/openpower/sv/bitmanip/grev_gorc_design.mdwn b/openpower/sv/bitmanip/grev_gorc_design.mdwn
index 9d2a2f60a5ac35ee2b98080e3807af9bcb2347a0..879e7d26827712272f0a0b8061f126964c374487 100644 (file)
--- a/openpower/sv/bitmanip/grev_gorc_design.mdwn
+++ b/openpower/sv/bitmanip/grev_gorc_design.mdwn
@@ -2,17 +2,17 @@
 
 The design is derived from a circuit for GRev made with muxes:
 
-![grev_made_with_muxes.svg](grev_made_with_muxes.svg)
+![grev_made_with_muxes.svg](../grev_made_with_muxes.svg)
 
 First, we convert that circuit to use And-Or-Invert gates, since that's an efficient way the muxes can be implemented:
 
-![grev_made_with_aoi_gates.svg](grev_made_with_aoi_gates.svg)
+![grev_made_with_aoi_gates.svg](../grev_made_with_aoi_gates.svg)
 
 Notice how each And-Or-Invert has both a bit of `SH` and `~SH` as inputs? Those can be converted to separate inputs, controlled by the bits of `SH` using the instruction's immediate as a pair of 2-bit look-up-tables. This requires 4-bits of immediate.
 
 This gives us our final design:
 
-![grev_gorc_combination.svg](grev_gorc_combination.svg)
+![grev_gorc_combination.svg](../grev_gorc_combination.svg)
 
 Notice how this still has an overall circuit latency that is essentially equivalent to grev's latency (or shift/rotate's latency). Also notice how this circuit allows specifying much more than just `grev` or `gorc` instructions. A final layer of XOR gates can be added at the input and output, allowing it to function as a `gandc` instruction too, requiring a total of 6-bits of immediate.