# This file is Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
-# This file is Copyright (c) 2014-2018 Florent Kermarrec <florent@enjoy-digital.fr>
+# This file is Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2015 Yann Sionneau <ys@m-labs.hk>
# License: BSD
if name is None:
name = self.__module__.split(".")[-1]
self.name = name
- self.sources = set()
- self.verilog_include_paths = set()
+ self.sources = []
+ self.verilog_include_paths = []
self.finalized = False
def request(self, *args, **kwargs):
if library is None:
library = "work"
- self.sources.add((os.path.abspath(filename), language, library))
+ self.sources.append((os.path.abspath(filename), language, library))
def add_sources(self, path, *filenames, language=None, library=None):
for f in filenames:
self.add_source(filename, _language, library)
def add_verilog_include_path(self, path):
- self.verilog_include_paths.add(os.path.abspath(path))
+ self.verilog_include_paths.append(os.path.abspath(path))
def resolve_signals(self, vns):
# resolve signal names in constraints