(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index b5ddcba94130944141b6e2fdc36adf34717cbb3f..bf3634b33424186b8dddf20c7ecd27a424e75256 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -166,7 +166,7 @@ Core SVP64 instructions:
 Beyond this point are additional **Scalar** instructions related to
 specific workloads that have nothing to do with the SV Specification*
 
-# Guarantees in Simple-V
+# Stability Guarantees in Simple-V
 
 Providing long-term stability in an ISA is extremely challenging
 but critically important.
@@ -181,14 +181,17 @@ It requires certain guarantees to be provided.
 * Fourthly, that any part of Simple-V not implemented by
   a lower Compliancy Level is *required* to raise an illegal
   instruction trap.
+* Fifthly, that any `UNDEFINED` behaviour for practical implementation
+  reasons is clearly documented for both programmers and hardware
+  implementors.
 
 In particular, given the strong recent emphasis and interest in
 "Scalable Vector" ISAs, it is most unfortunate that both ARM SVE
 and RISC-V RVV permit the exact same instruction to produce
 different results on different hardware depending on a
 "Silicon Partner" hardware choice. This choice catastrophically
-and irrevocably causes binary non-interoperability despite being
-a "feature".  Explained in <https://m.youtube.com/watch?v=HNEm8zmkjBU>
+and irrevocably causes binary non-interoperability *despite being
+a "feature"*.  Explained in <https://m.youtube.com/watch?v=HNEm8zmkjBU>
 
 It is therefore *guaranteed* that extensions to the register file
 width and quantity in Simple-V shall only be made in future by