Fix RC being set for stb and stbu

diff --git a/openpower/isatables/major.csv b/openpower/isatables/major.csv
index effd8696c76d2c1e2b163d57a62faa26adbaef28..076c319546e296c4da61b1b1c9a36a136705a8f1 100644 (file)
--- a/openpower/isatables/major.csv
+++ b/openpower/isatables/major.csv
@@ -23,8 +23,8 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 20,SHIFT_ROT,OP_RLC,RA,CONST_SH32,RS,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwimi,M
 21,SHIFT_ROT,OP_RLC,NONE,CONST_SH32,RS,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwinm,M
 23,SHIFT_ROT,OP_RLC,NONE,RB,RS,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,RC,0,0,rlwnm,M
-38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,RC,0,1,stb,D
-39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,RC,0,1,stbu,D
+38,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,1,stb,D
+39,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is1B,0,0,1,0,0,0,NONE,0,1,stbu,D
 44,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,0,0,0,0,NONE,0,1,sth,D
 45,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is2B,0,0,1,0,0,0,NONE,0,1,sthu,D
 36,LDST,OP_STORE,RA_OR_ZERO,CONST_SI,RS,NONE,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,1,stw,D