+2004-07-06 Steven Bosscher <stevenb@suse.de>
+
+ * config/mcore/mcore.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE):
+ Define.
+ * config/mcore/mcore.md: Model memory latency with a simple DFA
+ pipeline description instead of a define_function_unit.
+
2004-07-05 Richard Kenner <kenner@vlsi1.ultra.nyu.edu>
* langhooks-def.h (LANG_HOOKS_TREE_INLINING_VAR_MOD_TYPE_P): Extra arg.
#undef TARGET_SETUP_INCOMING_VARARGS
#define TARGET_SETUP_INCOMING_VARARGS mcore_setup_incoming_varargs
+#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
+
struct gcc_target targetm = TARGET_INITIALIZER;
\f
/* Adjust the stack and return the number of bytes taken to do it. */
;; calculations and the literal table placement into the assembler,
;; where their interactions can be managed in a single place.
-; All MCORE instructions are two bytes long.
+;; All MCORE instructions are two bytes long.
(define_attr "length" "" (const_int 2))
-;; (define_function_unit {name} {num-units} {n-users} {test}
-;; {ready-delay} {issue-delay} [{conflict-list}])
-
-
-(define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
+;; Scheduling. We only model a simple load latency.
+(define_insn_reservation "any_insn" 1
+ (eq_attr "type" "!load")
+ "nothing")
+(define_insn_reservation "memory" 2
+ (eq_attr "type" "load")
+ "nothing")
;; -------------------------------------------------------------------------
;; Test and bit test