r600g: Use blitter rather than DMA for 128bpp on cayman (v3)

On cayman, 128bpp surfaces require non_disp ordering for hw
access to both linear and tiled surfaces.  When we use the 3D
engine we can set the non_disp ordering on both the tiled and
linear sides (via CB or texture), but when we use the DMA
engine, we can only set the non_disp ordering on the tiled
side, so after a L2T operation with the DMA engine, the data
ends up in the wrong order on the tiled side.

v2: cayman/TN only

v3: fix comments

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=60802

Note: this is a candidate for the 9.1 branch.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 2bdefb0d35158e10b250087a74a841bbb1e70f6b..6b6d93e3f83b1266b6d72b09b9bf1f513801d53d 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3674,6 +3674,17 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
                return FALSE;
        }
 
+       /* 128 bpp surfaces require non_disp_tiling for both
+        * tiled and linear buffers on cayman.  However, async
+        * DMA only supports it on the tiled side.  As such
+        * the tile order is backwards after a L2T/T2L packet.
+        */
+       if ((rctx->chip_class == CAYMAN) &&
+           (src_mode != dst_mode) &&
+           (util_format_get_blocksize(src->format) >= 16)) {
+               return FALSE;
+       }
+
        if (src_mode == dst_mode) {
                uint64_t dst_offset, src_offset;
                /* simple dma blit would do NOTE code here assume :