ARM: Get rid of unnecessary Re operand.

diff --git a/src/arch/arm/isa/bitfields.isa b/src/arch/arm/isa/bitfields.isa
index bcb2869b7dc0e13c26209fb77b96a9014cef12ad..e334f5521b0c5b6a1199aa3273d63ae4a8c252cc 100644 (file)
--- a/src/arch/arm/isa/bitfields.isa
+++ b/src/arch/arm/isa/bitfields.isa
@@ -70,8 +70,6 @@ def bitfield SHIFT_SIZE    <11: 7>;
 def bitfield SHIFT         < 6: 5>;
 def bitfield RM            < 3: 0>;
 
-def bitfield RE            <20:16>;
-
 def bitfield RS            <11: 8>;
 
 def bitfield RDUP          <19:16>;

diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index f82e491096c1e3c7f7c652117ae03f479c6358f3..be4ec6e0305755abf917abed9f11ffcadc45ff66 100644 (file)
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -46,7 +46,6 @@ def operands {{
     'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
     'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
     'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
-    'Re': ('IntReg', 'uw', 'RE', 'IsInteger', 5),
 
     'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
     'R0': ('IntReg', 'uw', '0', 'IsInteger', 5),