* Preserving the underlying scalar execution dependencies as if the
for-loop had been expanded as actual scalar instructions
(termed "preserving Program Order")
+* Specifically designed to be Precise-Interruptible at all times
+ (many Vector ISAs have operations which, due to higher internal
+ accuracy or other complexity, must be effectively atomic for
+ the full Vector operation's duration, adversely affecting interrupt
+ response latency)
* Augments ("tags") existing instructions, providing Vectorisation
"context" rather than adding new instructions.
* Strictly does not interfere with or alter the non-Scalable Power ISA