Fixed a gcc compiler warning [-Wparentheses]

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 7c7d518dc7dbc8da2b92ca3256630e65d4fd258c..7d6c75150bd019663ceeacff63582588b5b2936a 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -139,12 +139,13 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
        if (reg_wires.count(sig.chunks[0].wire->name) == 0)
                return false;
        reg_name = id(sig.chunks[0].wire->name);
-       if (sig.width != sig.chunks[0].wire->width)
+       if (sig.width != sig.chunks[0].wire->width) {
                if (sig.width == 1)
                        reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset +  sig.chunks[0].offset);
                else
                        reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset +  sig.chunks[0].offset + sig.chunks[0].width - 1,
                                        sig.chunks[0].wire->start_offset +  sig.chunks[0].offset);
+       }
        return true;
 }