README: update Yosys version requirement.

diff --git a/README.md b/README.md
index 3df893a066a6e3667f8eb0419a273a2955f90a30..0948df26e08b05e856224b630c9dc059dd0328a2 100644 (file)
--- a/README.md
+++ b/README.md
@@ -14,7 +14,7 @@ See the [doc/](doc/) folder for more technical information.
 
 nMigen is a direct descendant of [Migen][] rewritten from scratch to address many issues that became clear in the many years Migen has been used in production. nMigen provides an extensive compatibility layer that makes it possible to build and simulate most Migen designs unmodified, as well as integrate modules written for Migen and nMigen.
 
-nMigen is designed for Python 3.6 and newer. nMigen's Verilog backend depends on [Yosys][]; currently, the `master` branch of Yosys is required.
+nMigen is designed for Python 3.6 and newer. nMigen's Verilog backend requires [Yosys][] 0.9 or a newer version.
 
 Thanks [LambdaConcept][] for being a sponsor of this project! Contact sb [at] m-labs.hk if you also wish to support this work.
 
@@ -28,6 +28,8 @@ nMigen is *not* a "Python-to-FPGA" conventional high level synthesis (HLS) tool.
 
 ### Installation
 
+nMigen requires [Yosys][] 0.9 or newer, as well as a device-specific toolchain.
+
     pip install git+https://github.com/m-labs/nmigen.git
     pip install git+https://github.com/m-labs/nmigen-boards.git