codegen/nv50_ir_target_nvc0.h
NVC0_C_SOURCES := \
+ nvc0/cla0c0qmd.h \
+ nvc0/drf.h \
+ nvc0/qmd.h \
+ nvc0/qmda0c0.c \
nvc0/gm107_texture.xml.h \
nvc0/nvc0_3d.xml.h \
nvc0/nvc0_compute.c \
'codegen/nv50_ir_target_gm107.h',
'codegen/nv50_ir_target_nvc0.cpp',
'codegen/nv50_ir_target_nvc0.h',
+ 'nvc0/cla0c0qmd.h',
+ 'nvc0/drf.h',
+ 'nvc0/qmd.h',
+ 'nvc0/qmda0c0.c',
'nvc0/gm107_texture.xml.h',
'nvc0/nvc0_3d.xml.h',
'nvc0/nvc0_compute.c',
--- /dev/null
+/*******************************************************************************
+ Copyright (c) 2016 NVIDIA Corporation
+
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to
+ deal in the Software without restriction, including without limitation the
+ rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
+ sell copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be
+ included in all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+
+*******************************************************************************/
+
+/* AUTO GENERATED FILE -- DO NOT EDIT */
+
+#ifndef __CLA0C0QMD_H__
+#define __CLA0C0QMD_H__
+
+/*
+** Queue Meta Data, Version 00_06
+ */
+
+// The below C preprocessor definitions describe "multi-word" structures, where
+// fields may have bit numbers beyond 32. For example, MW(127:96) means
+// the field is in bits 0-31 of word number 3 of the structure. The "MW(X:Y)"
+// syntax is to distinguish from similar "X:Y" single-word definitions: the
+// macros historically used for single-word definitions would fail with
+// multi-word definitions.
+//
+// See nvmisc.h:DRF_VAL_MW() in the source code of the kernel
+// interface layer of nvidia.ko for an example of how to manipulate
+// these MW(X:Y) definitions.
+
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_A MW(30:0)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_B MW(31:31)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_C MW(62:32)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_D MW(63:63)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_E MW(94:64)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_F MW(95:95)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_G MW(126:96)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_H MW(127:127)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_A_A MW(159:128)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_I MW(191:160)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_J MW(196:192)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_A MW(199:197)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K MW(200:200)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_K_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L MW(201:201)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_L_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202)
+#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203)
+#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_QMD_RESERVED_B MW(207:204)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_M MW(222:208)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N MW(223:223)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_N_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_O MW(248:224)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_C MW(249:249)
+#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250)
+#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251)
+#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252)
+#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253)
+#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254)
+#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255)
+#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_PROGRAM_OFFSET MW(287:256)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_P MW(319:288)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Q MW(327:320)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_D MW(335:328)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_R MW(351:336)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_S MW(357:352)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_E MW(365:358)
+#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE MW(366:366)
+#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
+#define NVA0C0_QMDV00_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
+#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE MW(369:368)
+#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
+#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
+#define NVA0C0_QMDV00_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T MW(370:370)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_T_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U MW(371:371)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_U_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_THROTTLED MW(372:372)
+#define NVA0C0_QMDV00_06_THROTTLED_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_THROTTLED_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_A MW(376:376)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_E2_B MW(377:377)
+#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT MW(378:378)
+#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT__32 0x00000000
+#define NVA0C0_QMDV00_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
+#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING MW(379:379)
+#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000
+#define NVA0C0_QMDV00_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001
+#define NVA0C0_QMDV00_06_SAMPLER_INDEX MW(382:382)
+#define NVA0C0_QMDV00_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
+#define NVA0C0_QMDV00_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
+#define NVA0C0_QMDV00_06_QMD_RESERVED_E3_A MW(383:383)
+#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH MW(415:384)
+#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT MW(431:416)
+#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH MW(447:432)
+#define NVA0C0_QMDV00_06_CTA_RASTER_WIDTH_RESUME MW(479:448)
+#define NVA0C0_QMDV00_06_CTA_RASTER_HEIGHT_RESUME MW(495:480)
+#define NVA0C0_QMDV00_06_CTA_RASTER_DEPTH_RESUME MW(511:496)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_V MW(535:512)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_F MW(542:536)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W MW(543:543)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_W_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_SHARED_MEMORY_SIZE MW(561:544)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_G MW(575:562)
+#define NVA0C0_QMDV00_06_QMD_VERSION MW(579:576)
+#define NVA0C0_QMDV00_06_QMD_MAJOR_VERSION MW(583:580)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_H MW(591:584)
+#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION0 MW(607:592)
+#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION1 MW(623:608)
+#define NVA0C0_QMDV00_06_CTA_THREAD_DIMENSION2 MW(639:624)
+#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
+#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_QMD_RESERVED_I MW(668:648)
+#define NVA0C0_QMDV00_06_L1_CONFIGURATION MW(671:669)
+#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001
+#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002
+#define NVA0C0_QMDV00_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_X MW(703:672)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_V1_Y MW(735:704)
+#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_LOWER MW(767:736)
+#define NVA0C0_QMDV00_06_RELEASE0_ADDRESS_UPPER MW(775:768)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_J MW(783:776)
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP MW(790:788)
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
+#define NVA0C0_QMDV00_06_QMD_RESERVED_K MW(791:791)
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT MW(793:792)
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE MW(794:794)
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE MW(799:799)
+#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
+#define NVA0C0_QMDV00_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
+#define NVA0C0_QMDV00_06_RELEASE0_PAYLOAD MW(831:800)
+#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_LOWER MW(863:832)
+#define NVA0C0_QMDV00_06_RELEASE1_ADDRESS_UPPER MW(871:864)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_L MW(879:872)
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP MW(886:884)
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
+#define NVA0C0_QMDV00_06_QMD_RESERVED_M MW(887:887)
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT MW(889:888)
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE MW(890:890)
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE MW(895:895)
+#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
+#define NVA0C0_QMDV00_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
+#define NVA0C0_QMDV00_06_RELEASE1_PAYLOAD MW(927:896)
+#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64))
+#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64))
+#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64))
+#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64))
+#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
+#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
+#define NVA0C0_QMDV00_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64))
+#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440)
+#define NVA0C0_QMDV00_06_QMD_RESERVED_N MW(1466:1464)
+#define NVA0C0_QMDV00_06_BARRIER_COUNT MW(1471:1467)
+#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472)
+#define NVA0C0_QMDV00_06_REGISTER_COUNT MW(1503:1496)
+#define NVA0C0_QMDV00_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504)
+#define NVA0C0_QMDV00_06_SASS_VERSION MW(1535:1528)
+#define NVA0C0_QMDV00_06_QMD_SPARE_A MW(1567:1536)
+#define NVA0C0_QMDV00_06_QMD_SPARE_B MW(1599:1568)
+#define NVA0C0_QMDV00_06_QMD_SPARE_C MW(1631:1600)
+#define NVA0C0_QMDV00_06_QMD_SPARE_D MW(1663:1632)
+#define NVA0C0_QMDV00_06_QMD_SPARE_E MW(1695:1664)
+#define NVA0C0_QMDV00_06_QMD_SPARE_F MW(1727:1696)
+#define NVA0C0_QMDV00_06_QMD_SPARE_G MW(1759:1728)
+#define NVA0C0_QMDV00_06_QMD_SPARE_H MW(1791:1760)
+#define NVA0C0_QMDV00_06_QMD_SPARE_I MW(1823:1792)
+#define NVA0C0_QMDV00_06_QMD_SPARE_J MW(1855:1824)
+#define NVA0C0_QMDV00_06_QMD_SPARE_K MW(1887:1856)
+#define NVA0C0_QMDV00_06_QMD_SPARE_L MW(1919:1888)
+#define NVA0C0_QMDV00_06_QMD_SPARE_M MW(1951:1920)
+#define NVA0C0_QMDV00_06_QMD_SPARE_N MW(1983:1952)
+#define NVA0C0_QMDV00_06_DEBUG_ID_UPPER MW(2015:1984)
+#define NVA0C0_QMDV00_06_DEBUG_ID_LOWER MW(2047:2016)
+
+
+/*
+** Queue Meta Data, Version 01_06
+ */
+
+#define NVA0C0_QMDV01_06_OUTER_PUT MW(30:0)
+#define NVA0C0_QMDV01_06_OUTER_OVERFLOW MW(31:31)
+#define NVA0C0_QMDV01_06_OUTER_GET MW(62:32)
+#define NVA0C0_QMDV01_06_OUTER_STICKY_OVERFLOW MW(63:63)
+#define NVA0C0_QMDV01_06_INNER_GET MW(94:64)
+#define NVA0C0_QMDV01_06_INNER_OVERFLOW MW(95:95)
+#define NVA0C0_QMDV01_06_INNER_PUT MW(126:96)
+#define NVA0C0_QMDV01_06_INNER_STICKY_OVERFLOW MW(127:127)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_A_A MW(159:128)
+#define NVA0C0_QMDV01_06_SCHEDULER_NEXT_QMD_POINTER MW(191:160)
+#define NVA0C0_QMDV01_06_QMD_GROUP_ID MW(197:192)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_A MW(199:198)
+#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(200:200)
+#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_SCHEDULE_ON_PUT_UPDATE_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201)
+#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0 MW(202:202)
+#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1 MW(203:203)
+#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS MW(204:204)
+#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_QMD_RESERVED_B MW(207:205)
+#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_ADDR MW(222:208)
+#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID MW(223:223)
+#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_SKED_PRIVATE_LIST_VALID_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_SIZE MW(248:224)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_C MW(249:249)
+#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250)
+#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251)
+#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252)
+#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE MW(253:253)
+#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE MW(254:254)
+#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255)
+#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_PROGRAM_OFFSET MW(287:256)
+#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288)
+#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_D MW(335:328)
+#define NVA0C0_QMDV01_06_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336)
+#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_ID MW(357:352)
+#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358)
+#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE MW(366:366)
+#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
+#define NVA0C0_QMDV01_06_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
+#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367)
+#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE MW(369:368)
+#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
+#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
+#define NVA0C0_QMDV01_06_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
+#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS MW(370:370)
+#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371)
+#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_THROTTLED MW(372:372)
+#define NVA0C0_QMDV01_06_THROTTLED_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_THROTTLED_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR MW(376:376)
+#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_LEGACY 0x00000000
+#define NVA0C0_QMDV01_06_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001
+#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR MW(377:377)
+#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000
+#define NVA0C0_QMDV01_06_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001
+#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT MW(378:378)
+#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT__32 0x00000000
+#define NVA0C0_QMDV01_06_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
+#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING MW(379:379)
+#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000
+#define NVA0C0_QMDV01_06_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001
+#define NVA0C0_QMDV01_06_SAMPLER_INDEX MW(382:382)
+#define NVA0C0_QMDV01_06_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
+#define NVA0C0_QMDV01_06_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
+#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION MW(383:383)
+#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000
+#define NVA0C0_QMDV01_06_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001
+#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH MW(415:384)
+#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT MW(431:416)
+#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH MW(447:432)
+#define NVA0C0_QMDV01_06_CTA_RASTER_WIDTH_RESUME MW(479:448)
+#define NVA0C0_QMDV01_06_CTA_RASTER_HEIGHT_RESUME MW(495:480)
+#define NVA0C0_QMDV01_06_CTA_RASTER_DEPTH_RESUME MW(511:496)
+#define NVA0C0_QMDV01_06_LAUNCH_QUOTA MW(535:512)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_F MW(542:536)
+#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE MW(543:543)
+#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_LAUNCH_QUOTA_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_SHARED_MEMORY_SIZE MW(561:544)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_G MW(575:562)
+#define NVA0C0_QMDV01_06_QMD_VERSION MW(579:576)
+#define NVA0C0_QMDV01_06_QMD_MAJOR_VERSION MW(583:580)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_H MW(591:584)
+#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION0 MW(607:592)
+#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION1 MW(623:608)
+#define NVA0C0_QMDV01_06_CTA_THREAD_DIMENSION2 MW(639:624)
+#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
+#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_VALID_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_QMD_RESERVED_I MW(668:648)
+#define NVA0C0_QMDV01_06_L1_CONFIGURATION MW(671:669)
+#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001
+#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002
+#define NVA0C0_QMDV01_06_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003
+#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_LOWER MW(703:672)
+#define NVA0C0_QMDV01_06_SM_DISABLE_MASK_UPPER MW(735:704)
+#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_LOWER MW(767:736)
+#define NVA0C0_QMDV01_06_RELEASE0_ADDRESS_UPPER MW(775:768)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_J MW(783:776)
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP MW(790:788)
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
+#define NVA0C0_QMDV01_06_QMD_RESERVED_K MW(791:791)
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT MW(793:792)
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE MW(794:794)
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE MW(799:799)
+#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
+#define NVA0C0_QMDV01_06_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
+#define NVA0C0_QMDV01_06_RELEASE0_PAYLOAD MW(831:800)
+#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_LOWER MW(863:832)
+#define NVA0C0_QMDV01_06_RELEASE1_ADDRESS_UPPER MW(871:864)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_L MW(879:872)
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP MW(886:884)
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
+#define NVA0C0_QMDV01_06_QMD_RESERVED_M MW(887:887)
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT MW(889:888)
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE MW(890:890)
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE MW(895:895)
+#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
+#define NVA0C0_QMDV01_06_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
+#define NVA0C0_QMDV01_06_RELEASE1_PAYLOAD MW(927:896)
+#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64))
+#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64))
+#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64))
+#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64))
+#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
+#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
+#define NVA0C0_QMDV01_06_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64))
+#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_N MW(1466:1464)
+#define NVA0C0_QMDV01_06_BARRIER_COUNT MW(1471:1467)
+#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472)
+#define NVA0C0_QMDV01_06_REGISTER_COUNT MW(1503:1496)
+#define NVA0C0_QMDV01_06_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504)
+#define NVA0C0_QMDV01_06_SASS_VERSION MW(1535:1528)
+#define NVA0C0_QMDV01_06_HW_ONLY_INNER_GET MW(1566:1536)
+#define NVA0C0_QMDV01_06_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567)
+#define NVA0C0_QMDV01_06_HW_ONLY_INNER_PUT MW(1598:1568)
+#define NVA0C0_QMDV01_06_HW_ONLY_SCHEDULE_ON_PUT_UPDATE_ENABLE MW(1599:1599)
+#define NVA0C0_QMDV01_06_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(1606:1600)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_Q MW(1609:1607)
+#define NVA0C0_QMDV01_06_COALESCE_WAITING_PERIOD MW(1617:1610)
+#define NVA0C0_QMDV01_06_QMD_RESERVED_R MW(1631:1618)
+#define NVA0C0_QMDV01_06_QMD_SPARE_D MW(1663:1632)
+#define NVA0C0_QMDV01_06_QMD_SPARE_E MW(1695:1664)
+#define NVA0C0_QMDV01_06_QMD_SPARE_F MW(1727:1696)
+#define NVA0C0_QMDV01_06_QMD_SPARE_G MW(1759:1728)
+#define NVA0C0_QMDV01_06_QMD_SPARE_H MW(1791:1760)
+#define NVA0C0_QMDV01_06_QMD_SPARE_I MW(1823:1792)
+#define NVA0C0_QMDV01_06_QMD_SPARE_J MW(1855:1824)
+#define NVA0C0_QMDV01_06_QMD_SPARE_K MW(1887:1856)
+#define NVA0C0_QMDV01_06_QMD_SPARE_L MW(1919:1888)
+#define NVA0C0_QMDV01_06_QMD_SPARE_M MW(1951:1920)
+#define NVA0C0_QMDV01_06_QMD_SPARE_N MW(1983:1952)
+#define NVA0C0_QMDV01_06_DEBUG_ID_UPPER MW(2015:1984)
+#define NVA0C0_QMDV01_06_DEBUG_ID_LOWER MW(2047:2016)
+
+
+/*
+** Queue Meta Data, Version 01_07
+ */
+
+#define NVA0C0_QMDV01_07_OUTER_PUT MW(30:0)
+#define NVA0C0_QMDV01_07_OUTER_OVERFLOW MW(31:31)
+#define NVA0C0_QMDV01_07_OUTER_GET MW(62:32)
+#define NVA0C0_QMDV01_07_OUTER_STICKY_OVERFLOW MW(63:63)
+#define NVA0C0_QMDV01_07_INNER_GET MW(94:64)
+#define NVA0C0_QMDV01_07_INNER_OVERFLOW MW(95:95)
+#define NVA0C0_QMDV01_07_INNER_PUT MW(126:96)
+#define NVA0C0_QMDV01_07_INNER_STICKY_OVERFLOW MW(127:127)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_A_A MW(159:128)
+#define NVA0C0_QMDV01_07_DEPENDENT_QMD_POINTER MW(191:160)
+#define NVA0C0_QMDV01_07_QMD_GROUP_ID MW(197:192)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_A MW(200:198)
+#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST MW(201:201)
+#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_ADD_TO_HEAD_OF_QMD_GROUP_LINKED_LIST_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0 MW(202:202)
+#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE0_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1 MW(203:203)
+#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_SEMAPHORE_RELEASE_ENABLE1_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS MW(204:204)
+#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_REQUIRE_SCHEDULING_PCAS_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE MW(205:205)
+#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_DEPENDENT_QMD_SCHEDULE_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE MW(206:206)
+#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_QUEUE 0x00000000
+#define NVA0C0_QMDV01_07_DEPENDENT_QMD_TYPE_GRID 0x00000001
+#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY MW(207:207)
+#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_DEPENDENT_QMD_FIELD_COPY_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_QMD_RESERVED_B MW(223:208)
+#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_SIZE MW(248:224)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_C MW(249:249)
+#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE MW(250:250)
+#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_HEADER_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE MW(251:251)
+#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_SAMPLER_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE MW(252:252)
+#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_INVALIDATE_TEXTURE_DATA_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE MW(253:253)
+#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_DATA_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE MW(254:254)
+#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_INVALIDATE_INSTRUCTION_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE MW(255:255)
+#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_INVALIDATE_SHADER_CONSTANT_CACHE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_PROGRAM_OFFSET MW(287:256)
+#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_LOWER MW(319:288)
+#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ADDR_UPPER MW(327:320)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_D MW(335:328)
+#define NVA0C0_QMDV01_07_CIRCULAR_QUEUE_ENTRY_SIZE MW(351:336)
+#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_ID MW(357:352)
+#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DELTA_MINUS_ONE MW(365:358)
+#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE MW(366:366)
+#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_NONE 0x00000000
+#define NVA0C0_QMDV01_07_RELEASE_MEMBAR_TYPE_FE_SYSMEMBAR 0x00000001
+#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE MW(367:367)
+#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_INCR_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE MW(369:368)
+#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_NONE 0x00000000
+#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_SYSMEMBAR 0x00000001
+#define NVA0C0_QMDV01_07_CWD_MEMBAR_TYPE_L1_MEMBAR 0x00000003
+#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS MW(370:370)
+#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_SEQUENTIALLY_RUN_CTAS_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE MW(371:371)
+#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_CWD_REFERENCE_COUNT_DECR_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_THROTTLED MW(372:372)
+#define NVA0C0_QMDV01_07_THROTTLED_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_THROTTLED_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR MW(376:376)
+#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_LEGACY 0x00000000
+#define NVA0C0_QMDV01_07_FP32_NAN_BEHAVIOR_FP64_COMPATIBLE 0x00000001
+#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR MW(377:377)
+#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_ZERO 0x00000000
+#define NVA0C0_QMDV01_07_FP32_F2I_NAN_BEHAVIOR_PASS_INDEFINITE 0x00000001
+#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT MW(378:378)
+#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT__32 0x00000000
+#define NVA0C0_QMDV01_07_API_VISIBLE_CALL_LIMIT_NO_CHECK 0x00000001
+#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING MW(379:379)
+#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_FOUR_BYTES_PER_BANK 0x00000000
+#define NVA0C0_QMDV01_07_SHARED_MEMORY_BANK_MAPPING_EIGHT_BYTES_PER_BANK 0x00000001
+#define NVA0C0_QMDV01_07_SAMPLER_INDEX MW(382:382)
+#define NVA0C0_QMDV01_07_SAMPLER_INDEX_INDEPENDENTLY 0x00000000
+#define NVA0C0_QMDV01_07_SAMPLER_INDEX_VIA_HEADER_INDEX 0x00000001
+#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION MW(383:383)
+#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_KEEP_DENORMS 0x00000000
+#define NVA0C0_QMDV01_07_FP32_NARROW_INSTRUCTION_FLUSH_DENORMS 0x00000001
+#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH MW(415:384)
+#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT MW(431:416)
+#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH MW(447:432)
+#define NVA0C0_QMDV01_07_CTA_RASTER_WIDTH_RESUME MW(479:448)
+#define NVA0C0_QMDV01_07_CTA_RASTER_HEIGHT_RESUME MW(495:480)
+#define NVA0C0_QMDV01_07_CTA_RASTER_DEPTH_RESUME MW(511:496)
+#define NVA0C0_QMDV01_07_QUEUE_ENTRIES_PER_CTA_MINUS_ONE MW(518:512)
+#define NVA0C0_QMDV01_07_COALESCE_WAITING_PERIOD MW(529:522)
+#define NVA0C0_QMDV01_07_SHARED_MEMORY_SIZE MW(561:544)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_G MW(575:562)
+#define NVA0C0_QMDV01_07_QMD_VERSION MW(579:576)
+#define NVA0C0_QMDV01_07_QMD_MAJOR_VERSION MW(583:580)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_H MW(591:584)
+#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION0 MW(607:592)
+#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION1 MW(623:608)
+#define NVA0C0_QMDV01_07_CTA_THREAD_DIMENSION2 MW(639:624)
+#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID(i) MW((640+(i)*1):(640+(i)*1))
+#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_VALID_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_QMD_RESERVED_I MW(668:648)
+#define NVA0C0_QMDV01_07_L1_CONFIGURATION MW(671:669)
+#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB 0x00000001
+#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB 0x00000002
+#define NVA0C0_QMDV01_07_L1_CONFIGURATION_DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB 0x00000003
+#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_LOWER MW(703:672)
+#define NVA0C0_QMDV01_07_SM_DISABLE_MASK_UPPER MW(735:704)
+#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_LOWER MW(767:736)
+#define NVA0C0_QMDV01_07_RELEASE0_ADDRESS_UPPER MW(775:768)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_J MW(783:776)
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP MW(790:788)
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_ADD 0x00000000
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MIN 0x00000001
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_MAX 0x00000002
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_INC 0x00000003
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_DEC 0x00000004
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_AND 0x00000005
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_OR 0x00000006
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_OP_RED_XOR 0x00000007
+#define NVA0C0_QMDV01_07_QMD_RESERVED_K MW(791:791)
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT MW(793:792)
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_FORMAT_SIGNED_32 0x00000001
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE MW(794:794)
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_RELEASE0_REDUCTION_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE MW(799:799)
+#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
+#define NVA0C0_QMDV01_07_RELEASE0_STRUCTURE_SIZE_ONE_WORD 0x00000001
+#define NVA0C0_QMDV01_07_RELEASE0_PAYLOAD MW(831:800)
+#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_LOWER MW(863:832)
+#define NVA0C0_QMDV01_07_RELEASE1_ADDRESS_UPPER MW(871:864)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_L MW(879:872)
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP MW(886:884)
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_ADD 0x00000000
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MIN 0x00000001
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_MAX 0x00000002
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_INC 0x00000003
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_DEC 0x00000004
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_AND 0x00000005
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_OR 0x00000006
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_OP_RED_XOR 0x00000007
+#define NVA0C0_QMDV01_07_QMD_RESERVED_M MW(887:887)
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT MW(889:888)
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_UNSIGNED_32 0x00000000
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_FORMAT_SIGNED_32 0x00000001
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE MW(890:890)
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_RELEASE1_REDUCTION_ENABLE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE MW(895:895)
+#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_FOUR_WORDS 0x00000000
+#define NVA0C0_QMDV01_07_RELEASE1_STRUCTURE_SIZE_ONE_WORD 0x00000001
+#define NVA0C0_QMDV01_07_RELEASE1_PAYLOAD MW(927:896)
+#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_LOWER(i) MW((959+(i)*64):(928+(i)*64))
+#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_ADDR_UPPER(i) MW((967+(i)*64):(960+(i)*64))
+#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_RESERVED_ADDR(i) MW((973+(i)*64):(968+(i)*64))
+#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE(i) MW((974+(i)*64):(974+(i)*64))
+#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_INVALIDATE_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_CONSTANT_BUFFER_SIZE(i) MW((991+(i)*64):(975+(i)*64))
+#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_LOW_SIZE MW(1463:1440)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_N MW(1466:1464)
+#define NVA0C0_QMDV01_07_BARRIER_COUNT MW(1471:1467)
+#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_HIGH_SIZE MW(1495:1472)
+#define NVA0C0_QMDV01_07_REGISTER_COUNT MW(1503:1496)
+#define NVA0C0_QMDV01_07_SHADER_LOCAL_MEMORY_CRS_SIZE MW(1527:1504)
+#define NVA0C0_QMDV01_07_SASS_VERSION MW(1535:1528)
+#define NVA0C0_QMDV01_07_HW_ONLY_INNER_GET MW(1566:1536)
+#define NVA0C0_QMDV01_07_HW_ONLY_REQUIRE_SCHEDULING_PCAS MW(1567:1567)
+#define NVA0C0_QMDV01_07_HW_ONLY_INNER_PUT MW(1598:1568)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_P MW(1599:1599)
+#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX MW(1629:1600)
+#define NVA0C0_QMDV01_07_QMD_RESERVED_Q MW(1630:1630)
+#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID MW(1631:1631)
+#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_FALSE 0x00000000
+#define NVA0C0_QMDV01_07_HW_ONLY_SPAN_LIST_HEAD_INDEX_VALID_TRUE 0x00000001
+#define NVA0C0_QMDV01_07_HW_ONLY_SKED_NEXT_QMD_POINTER MW(1663:1632)
+#define NVA0C0_QMDV01_07_QMD_SPARE_E MW(1695:1664)
+#define NVA0C0_QMDV01_07_QMD_SPARE_F MW(1727:1696)
+#define NVA0C0_QMDV01_07_QMD_SPARE_G MW(1759:1728)
+#define NVA0C0_QMDV01_07_QMD_SPARE_H MW(1791:1760)
+#define NVA0C0_QMDV01_07_QMD_SPARE_I MW(1823:1792)
+#define NVA0C0_QMDV01_07_QMD_SPARE_J MW(1855:1824)
+#define NVA0C0_QMDV01_07_QMD_SPARE_K MW(1887:1856)
+#define NVA0C0_QMDV01_07_QMD_SPARE_L MW(1919:1888)
+#define NVA0C0_QMDV01_07_QMD_SPARE_M MW(1951:1920)
+#define NVA0C0_QMDV01_07_QMD_SPARE_N MW(1983:1952)
+#define NVA0C0_QMDV01_07_DEBUG_ID_UPPER MW(2015:1984)
+#define NVA0C0_QMDV01_07_DEBUG_ID_LOWER MW(2047:2016)
+
+
+
+#endif // #ifndef __CLA0C0QMD_H__
--- /dev/null
+/*
+ * Copyright 2019 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#ifndef __NVHW_DRF_H__
+#define __NVHW_DRF_H__
+
+/* Helpers common to all DRF accessors. */
+#define DRF_LO(drf) (0 ? drf)
+#define DRF_HI(drf) (1 ? drf)
+#define DRF_BITS(drf) (DRF_HI(drf) - DRF_LO(drf) + 1)
+#define DRF_MASK(drf) (~0ULL >> (64 - DRF_BITS(drf)))
+#define DRF_SMASK(drf) (DRF_MASK(drf) << DRF_LO(drf))
+
+/* Helpers for DRF-MW accessors. */
+#define DRF_MX_MW(drf) drf
+#define DRF_MX(drf) DRF_MX_##drf
+#define DRF_MW(drf) DRF_MX(drf)
+#define DRF_MW_SPANS(o,drf) (DRF_LW_IDX((o),drf) != DRF_HW_IDX((o),drf))
+#define DRF_MW_SIZE(o) (sizeof((o)[0]) * 8)
+
+#define DRF_LW_IDX(o,drf) (DRF_LO(DRF_MW(drf)) / DRF_MW_SIZE(o))
+#define DRF_LW_LO(o,drf) (DRF_LO(DRF_MW(drf)) % DRF_MW_SIZE(o))
+#define DRF_LW_HI(o,drf) (DRF_MW_SPANS((o),drf) ? (DRF_MW_SIZE(o) - 1) : DRF_HW_HI((o),drf))
+#define DRF_LW_BITS(o,drf) (DRF_LW_HI((o),drf) - DRF_LW_LO((o),drf) + 1)
+#define DRF_LW_MASK(o,drf) (~0ULL >> (64 - DRF_LW_BITS((o),drf)))
+#define DRF_LW_SMASK(o,drf) (DRF_LW_MASK((o),drf) << DRF_LW_LO((o),drf))
+#define DRF_LW_GET(o,drf) (((o)[DRF_LW_IDX((o),drf)] >> DRF_LW_LO((o),drf)) & DRF_LW_MASK((o),drf))
+#define DRF_LW_VAL(o,drf,v) (((v) & DRF_LW_MASK((o),drf)) << DRF_LW_LO((o),drf))
+#define DRF_LW_CLR(o,drf) ((o)[DRF_LW_IDX((o),drf)] & ~DRF_LW_SMASK((o),drf))
+#define DRF_LW_SET(o,drf,v) (DRF_LW_CLR((o),drf) | DRF_LW_VAL((o),drf,(v)))
+
+#define DRF_HW_IDX(o,drf) (DRF_HI(DRF_MW(drf)) / DRF_MW_SIZE(o))
+#define DRF_HW_LO(o,drf) 0
+#define DRF_HW_HI(o,drf) (DRF_HI(DRF_MW(drf)) % DRF_MW_SIZE(o))
+#define DRF_HW_BITS(o,drf) (DRF_HW_HI((o),drf) - DRF_HW_LO((o),drf) + 1)
+#define DRF_HW_MASK(o,drf) (~0ULL >> (64 - DRF_HW_BITS((o),drf)))
+#define DRF_HW_SMASK(o,drf) (DRF_HW_MASK((o),drf) << DRF_HW_LO((o),drf))
+#define DRF_HW_GET(o,drf) ((o)[DRF_HW_IDX(o,drf)] & DRF_HW_SMASK((o),drf))
+#define DRF_HW_VAL(o,drf,v) (((long long)(v) >> DRF_LW_BITS((o),drf)) & DRF_HW_SMASK((o),drf))
+#define DRF_HW_CLR(o,drf) ((o)[DRF_HW_IDX((o),drf)] & ~DRF_HW_SMASK((o),drf))
+#define DRF_HW_SET(o,drf,v) (DRF_HW_CLR((o),drf) | DRF_HW_VAL((o),drf,(v)))
+
+/* DRF accessors. */
+#define NVVAL_X(drf,v) (((v) & DRF_MASK(drf)) << DRF_LO(drf))
+#define NVVAL_N(X,d,r,f, v) NVVAL_X(d##_##r##_##f, (v))
+#define NVVAL_I(X,d,r,f,i,v) NVVAL_X(d##_##r##_##f(i), (v))
+#define NVVAL_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL
+#define NVVAL(A...) NVVAL_(X, ##A, NVVAL_I, NVVAL_N)(X, ##A)
+
+#define NVDEF_N(X,d,r,f, v) NVVAL_X(d##_##r##_##f, d##_##r##_##f##_##v)
+#define NVDEF_I(X,d,r,f,i,v) NVVAL_X(d##_##r##_##f(i), d##_##r##_##f##_##v)
+#define NVDEF_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL
+#define NVDEF(A...) NVDEF_(X, ##A, NVDEF_I, NVDEF_N)(X, ##A)
+
+#define NVVAL_GET_X(o,drf) (((o) >> DRF_LO(drf)) & DRF_MASK(drf))
+#define NVVAL_GET_N(X,o,d,r,f ) NVVAL_GET_X(o, d##_##r##_##f)
+#define NVVAL_GET_I(X,o,d,r,f,i) NVVAL_GET_X(o, d##_##r##_##f(i))
+#define NVVAL_GET_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL
+#define NVVAL_GET(A...) NVVAL_GET_(X, ##A, NVVAL_GET_I, NVVAL_GET_N)(X, ##A)
+
+#define NVVAL_SET_X(o,drf,v) (((o) & ~DRF_SMASK(drf)) | NVVAL_X(drf, (v)))
+#define NVVAL_SET_N(X,o,d,r,f, v) NVVAL_SET_X(o, d##_##r##_##f, (v))
+#define NVVAL_SET_I(X,o,d,r,f,i,v) NVVAL_SET_X(o, d##_##r##_##f(i), (v))
+#define NVVAL_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
+#define NVVAL_SET(A...) NVVAL_SET_(X, ##A, NVVAL_SET_I, NVVAL_SET_N)(X, ##A)
+
+#define NVDEF_SET_N(X,o,d,r,f, v) \
+ NVVAL_SET_X(o, d##_##r##_##f, d##_##r##_##f##_##v)
+#define NVDEF_SET_I(X,o,d,r,f,i,v) \
+ NVVAL_SET_X(o, d##_##r##_##f(i), d##_##r##_##f##_##v)
+#define NVDEF_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
+#define NVDEF_SET(A...) NVDEF_SET_(X, ##A, NVDEF_SET_I, NVDEF_SET_N)(X, ##A)
+
+/* DRF-MW accessors. */
+#define NVVAL_MW_GET_X(o,drf) \
+ ((DRF_MW_SPANS((o),drf) ? \
+ (DRF_HW_GET((o),drf) << DRF_LW_BITS((o),drf)) : 0) | DRF_LW_GET((o),drf))
+#define NVVAL_MW_GET_N(X,o,d,r,f ) NVVAL_MW_GET_X((o), d##_##r##_##f)
+#define NVVAL_MW_GET_I(X,o,d,r,f,i) NVVAL_MW_GET_X((o), d##_##r##_##f(i))
+#define NVVAL_MW_GET_(X,_1,_2,_3,_4,_5,IMPL,...) IMPL
+#define NVVAL_MW_GET(A...) NVVAL_MW_GET_(X, ##A, NVVAL_MW_GET_I, NVVAL_MW_GET_N)(X, ##A)
+
+#define NVVAL_MW_SET_X(o,drf,v) do { \
+ (o)[DRF_LW_IDX((o),drf)] = DRF_LW_SET((o),drf,(v)); \
+ if (DRF_MW_SPANS((o),drf)) \
+ (o)[DRF_HW_IDX((o),drf)] = DRF_HW_SET((o),drf,(v)); \
+} while(0)
+#define NVVAL_MW_SET_N(X,o,d,r,f, v) NVVAL_MW_SET_X((o), d##_##r##_##f, (v))
+#define NVVAL_MW_SET_I(X,o,d,r,f,i,v) NVVAL_MW_SET_X((o), d##_##r##_##f(i), (v))
+#define NVVAL_MW_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
+#define NVVAL_MW_SET(A...) \
+ NVVAL_MW_SET_(X, ##A, NVVAL_MW_SET_I, NVVAL_MW_SET_N)(X, ##A)
+
+#define NVDEF_MW_SET_N(X,o,d,r,f, v) \
+ NVVAL_MW_SET_X(o, d##_##r##_##f, d##_##r##_##f##_##v)
+#define NVDEF_MW_SET_I(X,o,d,r,f,i,v) \
+ NVVAL_MW_SET_X(o, d##_##r##_##f(i), d##_##r##_##f##_##v)
+#define NVDEF_MW_SET_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
+#define NVDEF_MW_SET(A...) \
+ NVDEF_MW_SET_(X, ##A, NVDEF_MW_SET_I, NVDEF_MW_SET_N)(X, ##A)
+#endif
#include "codegen/nv50_ir_driver.h"
+#include "drf.h"
+#include "qmd.h"
+#include "cla0c0qmd.h"
+
+#define NVA0C0_QMDV00_06_VAL_SET(p,a...) NVVAL_MW_SET((p), NVA0C0, QMDV00_06, ##a)
+#define NVA0C0_QMDV00_06_DEF_SET(p,a...) NVDEF_MW_SET((p), NVA0C0, QMDV00_06, ##a)
+
#ifndef NDEBUG
-static void nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *);
static void gp100_compute_dump_launch_desc(const struct gp100_cp_launch_desc *);
#endif
PUSH_DATA (push, NVE4_COMPUTE_FLUSH_CB);
}
-static inline uint8_t
-nve4_compute_derive_cache_split(struct nvc0_context *nvc0, uint32_t shared_size)
+static inline void
+nve4_cp_launch_desc_set_cb(uint32_t *qmd, unsigned index, struct nouveau_bo *bo,
+ uint32_t base, uint32_t size)
{
- if (shared_size > (32 << 10))
- return NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1;
- if (shared_size > (16 << 10))
- return NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1;
- return NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1;
+ uint64_t address = bo->offset + base;
+
+ assert(index < 8);
+ assert(!(base & 0xff));
+
+ NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_LOWER, index, address);
+ NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_ADDR_UPPER, index, address >> 32);
+ NVA0C0_QMDV00_06_VAL_SET(qmd, CONSTANT_BUFFER_SIZE, index, size);
+ NVA0C0_QMDV00_06_DEF_SET(qmd, CONSTANT_BUFFER_VALID, index, TRUE);
}
static void
}
static void
-nve4_compute_setup_launch_desc(struct nvc0_context *nvc0,
- struct nve4_cp_launch_desc *desc,
+nve4_compute_setup_launch_desc(struct nvc0_context *nvc0, uint32_t *qmd,
const struct pipe_grid_info *info)
{
const struct nvc0_screen *screen = nvc0->screen;
const struct nvc0_program *cp = nvc0->compprog;
- nve4_cp_launch_desc_init_default(desc);
-
- desc->entry = nvc0_program_symbol_offset(cp, info->pc);
-
- desc->griddim_x = info->grid[0];
- desc->griddim_y = info->grid[1];
- desc->griddim_z = info->grid[2];
- desc->blockdim_x = info->block[0];
- desc->blockdim_y = info->block[1];
- desc->blockdim_z = info->block[2];
-
- desc->shared_size = align(cp->cp.smem_size, 0x100);
- desc->local_size_p = (cp->hdr[1] & 0xfffff0) + align(cp->cp.lmem_size, 0x10);
- desc->local_size_n = 0;
- desc->cstack_size = 0x800;
- desc->cache_split = nve4_compute_derive_cache_split(nvc0, cp->cp.smem_size);
+ NVA0C0_QMDV00_06_DEF_SET(qmd, INVALIDATE_TEXTURE_HEADER_CACHE, TRUE);
+ NVA0C0_QMDV00_06_DEF_SET(qmd, INVALIDATE_TEXTURE_SAMPLER_CACHE, TRUE);
+ NVA0C0_QMDV00_06_DEF_SET(qmd, INVALIDATE_TEXTURE_DATA_CACHE, TRUE);
+ NVA0C0_QMDV00_06_DEF_SET(qmd, INVALIDATE_SHADER_DATA_CACHE, TRUE);
+ NVA0C0_QMDV00_06_DEF_SET(qmd, INVALIDATE_SHADER_CONSTANT_CACHE, TRUE);
+ NVA0C0_QMDV00_06_DEF_SET(qmd, RELEASE_MEMBAR_TYPE, FE_SYSMEMBAR);
+ NVA0C0_QMDV00_06_DEF_SET(qmd, CWD_MEMBAR_TYPE, L1_SYSMEMBAR);
+ NVA0C0_QMDV00_06_DEF_SET(qmd, API_VISIBLE_CALL_LIMIT, NO_CHECK);
+ NVA0C0_QMDV00_06_VAL_SET(qmd, SASS_VERSION, 0x30);
+
+ NVA0C0_QMDV00_06_VAL_SET(qmd, PROGRAM_OFFSET,
+ nvc0_program_symbol_offset(cp, info->pc));
+
+ NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_WIDTH, info->grid[0]);
+ NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_HEIGHT, info->grid[1]);
+ NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_RASTER_DEPTH, info->grid[2]);
+ NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_THREAD_DIMENSION0, info->block[0]);
+ NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_THREAD_DIMENSION1, info->block[1]);
+ NVA0C0_QMDV00_06_VAL_SET(qmd, CTA_THREAD_DIMENSION2, info->block[2]);
+
+ NVA0C0_QMDV00_06_VAL_SET(qmd, SHARED_MEMORY_SIZE,
+ align(cp->cp.smem_size, 0x100));
+ NVA0C0_QMDV00_06_VAL_SET(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE,
+ (cp->hdr[1] & 0xfffff0) +
+ align(cp->cp.lmem_size, 0x10));
+ NVA0C0_QMDV00_06_VAL_SET(qmd, SHADER_LOCAL_MEMORY_HIGH_SIZE, 0);
+ NVA0C0_QMDV00_06_VAL_SET(qmd, SHADER_LOCAL_MEMORY_CRS_SIZE, 0x800);
+
+ if (cp->cp.smem_size > (32 << 10))
+ NVA0C0_QMDV00_06_DEF_SET(qmd, L1_CONFIGURATION,
+ DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB);
+ else
+ if (cp->cp.smem_size > (16 << 10))
+ NVA0C0_QMDV00_06_DEF_SET(qmd, L1_CONFIGURATION,
+ DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB);
+ else
+ NVA0C0_QMDV00_06_DEF_SET(qmd, L1_CONFIGURATION,
+ DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB);
- desc->gpr_alloc = cp->num_gprs;
- desc->bar_alloc = cp->num_barriers;
+ NVA0C0_QMDV00_06_VAL_SET(qmd, REGISTER_COUNT, cp->num_gprs);
+ NVA0C0_QMDV00_06_VAL_SET(qmd, BARRIER_COUNT, cp->num_barriers);
// Only bind user uniforms and the driver constant buffer through the
// launch descriptor because UBOs are sticked to the driver cb to avoid the
// limitation of 8 CBs.
if (nvc0->constbuf[5][0].user || cp->parm_size) {
- nve4_cp_launch_desc_set_cb(desc, 0, screen->uniform_bo,
+ nve4_cp_launch_desc_set_cb(qmd, 0, screen->uniform_bo,
NVC0_CB_USR_INFO(5), 1 << 16);
// Later logic will attempt to bind a real buffer at position 0. That
// should not happen if we've bound a user buffer.
assert(nvc0->constbuf[5][0].user || !nvc0->constbuf[5][0].u.buf);
}
- nve4_cp_launch_desc_set_cb(desc, 7, screen->uniform_bo,
+ nve4_cp_launch_desc_set_cb(qmd, 7, screen->uniform_bo,
NVC0_CB_AUX_INFO(5), 1 << 11);
- nve4_compute_setup_buf_cb(nvc0, false, desc);
+ nve4_compute_setup_buf_cb(nvc0, false, qmd);
}
static void
ptr += adj;
*pgpuaddr += adj;
}
+ memset(ptr, 0x00, 256);
return ptr;
}
#ifndef NDEBUG
if (debug_get_num_option("NV50_PROG_DEBUG", 0)) {
+ debug_printf("Queue Meta Data:\n");
if (nvc0->screen->compute->oclass >= GP100_COMPUTE_CLASS)
gp100_compute_dump_launch_desc(desc);
else
- nve4_compute_dump_launch_desc(desc);
+ NVA0C0QmdDump_V00_06(desc);
}
#endif
#ifndef NDEBUG
-static const char *nve4_cache_split_name(unsigned value)
-{
- switch (value) {
- case NVC1_3D_CACHE_SPLIT_16K_SHARED_48K_L1: return "16K_SHARED_48K_L1";
- case NVE4_3D_CACHE_SPLIT_32K_SHARED_32K_L1: return "32K_SHARED_32K_L1";
- case NVC0_3D_CACHE_SPLIT_48K_SHARED_16K_L1: return "48K_SHARED_16K_L1";
- default:
- return "(invalid)";
- }
-}
-
-static void
-nve4_compute_dump_launch_desc(const struct nve4_cp_launch_desc *desc)
-{
- const uint32_t *data = (const uint32_t *)desc;
- unsigned i;
- bool zero = false;
-
- debug_printf("COMPUTE LAUNCH DESCRIPTOR:\n");
-
- for (i = 0; i < sizeof(*desc); i += 4) {
- if (data[i / 4]) {
- debug_printf("[%x]: 0x%08x\n", i, data[i / 4]);
- zero = false;
- } else
- if (!zero) {
- debug_printf("...\n");
- zero = true;
- }
- }
-
- debug_printf("entry = 0x%x\n", desc->entry);
- debug_printf("grid dimensions = %ux%ux%u\n",
- desc->griddim_x, desc->griddim_y, desc->griddim_z);
- debug_printf("block dimensions = %ux%ux%u\n",
- desc->blockdim_x, desc->blockdim_y, desc->blockdim_z);
- debug_printf("s[] size: 0x%x\n", desc->shared_size);
- debug_printf("l[] size: -0x%x / +0x%x\n",
- desc->local_size_n, desc->local_size_p);
- debug_printf("stack size: 0x%x\n", desc->cstack_size);
- debug_printf("barrier count: %u\n", desc->bar_alloc);
- debug_printf("$r count: %u\n", desc->gpr_alloc);
- debug_printf("cache split: %s\n", nve4_cache_split_name(desc->cache_split));
- debug_printf("linked tsc: %d\n", desc->linked_tsc);
-
- for (i = 0; i < 8; ++i) {
- uint64_t address;
- uint32_t size = desc->cb[i].size;
- bool valid = !!(desc->cb_mask & (1 << i));
-
- address = ((uint64_t)desc->cb[i].address_h << 32) | desc->cb[i].address_l;
-
- if (!valid && !address && !size)
- continue;
- debug_printf("CB[%u]: address = 0x%"PRIx64", size 0x%x%s\n",
- i, address, size, valid ? "" : " (invalid)");
- }
-}
-
static void
gp100_compute_dump_launch_desc(const struct gp100_cp_launch_desc *desc)
{
#include "nvc0/nve4_compute.xml.h"
-struct nve4_cp_launch_desc
-{
- u32 unk0[8];
- u32 entry;
- u32 unk9[2];
- u32 unk11_0 : 30;
- u32 linked_tsc : 1;
- u32 unk11_31 : 1;
- u32 griddim_x : 31;
- u32 unk12 : 1;
- u16 griddim_y;
- u16 griddim_z;
- u32 unk14[3];
- u16 shared_size; /* must be aligned to 0x100 */
- u16 unk17;
- u16 unk18;
- u16 blockdim_x;
- u16 blockdim_y;
- u16 blockdim_z;
- u32 cb_mask : 8;
- u32 unk20_8 : 21;
- u32 cache_split : 2;
- u32 unk20_31 : 1;
- u32 unk21[8];
- struct {
- u32 address_l;
- u32 address_h : 8;
- u32 reserved : 7;
- u32 size : 17;
- } cb[8];
- u32 local_size_p : 20;
- u32 unk45_20 : 7;
- u32 bar_alloc : 5;
- u32 local_size_n : 20;
- u32 unk46_20 : 4;
- u32 gpr_alloc : 8;
- u32 cstack_size : 20;
- u32 unk47_20 : 12;
- u32 unk48[16];
-};
-
struct gp100_cp_launch_desc
{
u32 unk0[8];
u32 unk48[16];
};
-static inline void
-nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc)
-{
- memset(desc, 0, sizeof(*desc));
-
- desc->unk0[7] = 0xbc000000;
- desc->unk11_0 = 0x04014000;
- desc->unk47_20 = 0x300;
-}
-
-static inline void
-nve4_cp_launch_desc_set_cb(struct nve4_cp_launch_desc *desc,
- unsigned index,
- struct nouveau_bo *bo,
- uint32_t base, uint32_t size)
-{
- uint64_t address = bo->offset + base;
-
- assert(index < 8);
- assert(!(base & 0xff));
-
- desc->cb[index].address_l = address;
- desc->cb[index].address_h = address >> 32;
- desc->cb[index].size = size;
-
- desc->cb_mask |= 1 << index;
-}
-
static inline void
gp100_cp_launch_desc_init_default(struct gp100_cp_launch_desc *desc)
{
--- /dev/null
+#ifndef __NVHW_QMD_H__
+#define __NVHW_QMD_H__
+#include <stdio.h>
+#include <stdint.h>
+#include "util/u_debug.h"
+#include "drf.h"
+
+#define NVQMD_ENUM_1(X,drf,v0) \
+ [drf##_##v0] = #v0
+#define NVQMD_ENUM_2(X,drf,v0,v1) \
+ [drf##_##v0] = #v0, \
+ [drf##_##v1] = #v1
+#define NVQMD_ENUM_3(X,drf,v0,v1,v2) \
+ [drf##_##v0] = #v0, \
+ [drf##_##v1] = #v1, \
+ [drf##_##v2] = #v2
+#define NVQMD_ENUM_8(X,drf,v0,v1,v2,v3,v4,v5,v6,v7) \
+ [drf##_##v0] = #v0, \
+ [drf##_##v1] = #v1, \
+ [drf##_##v2] = #v2, \
+ [drf##_##v3] = #v3, \
+ [drf##_##v4] = #v4, \
+ [drf##_##v5] = #v5, \
+ [drf##_##v6] = #v6, \
+ [drf##_##v7] = #v7
+
+#define NVQMD_ENUM_(X,_1,_2,_3,_4,_5,_6,_7,_8,_9,IMPL,...) IMPL
+#define NVQMD_ENUM(A...) NVQMD_ENUM_(X, ##A, NVQMD_ENUM_8, NVQMD_ENUM_7, \
+ NVQMD_ENUM_6, NVQMD_ENUM_5, \
+ NVQMD_ENUM_4, NVQMD_ENUM_3, \
+ NVQMD_ENUM_2, NVQMD_ENUM_1)(X, ##A)
+
+#define NVQMD_VAL_N(X,d,r,p,f,o) do { \
+ uint32_t val = NVVAL_MW_GET_X((p), d##_##r##_##f); \
+ debug_printf(" %-36s: "o"\n", #f, val); \
+} while(0)
+#define NVQMD_VAL_I(X,d,r,p,f,i,o) do { \
+ uint32_t val = NVVAL_MW_GET_X((p), d##_##r##_##f(i)); \
+ char name[80]; \
+ snprintf(name, sizeof(name), "%s(%d)", #f, i); \
+ debug_printf(" %-36s: "o"\n", name, val); \
+} while(0)
+#define NVQMD_VAL_(X,_1,_2,_3,_4,_5,_6,IMPL,...) IMPL
+#define NVQMD_VAL(A...) NVQMD_VAL_(X, ##A, NVQMD_VAL_I, NVQMD_VAL_N)(X, ##A)
+
+#define NVQMD_DEF(d,r,p,f,e...) do { \
+ static const char *ev[] = { NVQMD_ENUM(d##_##r##_##f,##e) }; \
+ uint32_t val = NVVAL_MW_GET((p), d, r, f); \
+ if (val < ARRAY_SIZE(ev) && ev[val]) \
+ debug_printf(" %-36s: %s\n", #f, ev[val]); \
+ else \
+ debug_printf(" %-36s: UNKNOWN 0x%x\n", #f, val); \
+} while(0)
+#define NVQMD_IDX(d,r,p,f,i,e...) do { \
+ static const char *ev[] = { NVQMD_ENUM(d##_##r##_##f,##e) }; \
+ char name[80]; \
+ snprintf(name, sizeof(name), "%s(%d)", #f, i); \
+ uint32_t val = NVVAL_MW_GET((p), d, r, f, i); \
+ if (val < ARRAY_SIZE(ev) && ev[val]) \
+ debug_printf(" %-36s: %s\n", name, ev[val]); \
+ else \
+ debug_printf(" %-36s: UNKNOWN 0x%x\n", name, val); \
+} while(0)
+
+void NVA0C0QmdDump_V00_06(uint32_t *);
+#endif
--- /dev/null
+/*
+ * Copyright 2020 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include "qmd.h"
+#include "cla0c0qmd.h"
+
+#define NVA0C0_QMDV00_06_VAL(a...) NVQMD_VAL(NVA0C0, QMDV00_06, ##a)
+#define NVA0C0_QMDV00_06_DEF(a...) NVQMD_DEF(NVA0C0, QMDV00_06, ##a)
+#define NVA0C0_QMDV00_06_IDX(a...) NVQMD_IDX(NVA0C0, QMDV00_06, ##a)
+
+void
+NVA0C0QmdDump_V00_06(uint32_t *qmd)
+{
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_A, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_B, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_C, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_D, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_E, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_F, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_G, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_H, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_A_A, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_I, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_J, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_A, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, QMD_RESERVED_V1_K, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, QMD_RESERVED_V1_L, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, SEMAPHORE_RELEASE_ENABLE0, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, SEMAPHORE_RELEASE_ENABLE1, FALSE, TRUE);
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_B, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_M, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, QMD_RESERVED_V1_N, FALSE, TRUE);
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_O, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_C, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, INVALIDATE_TEXTURE_HEADER_CACHE, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, INVALIDATE_TEXTURE_SAMPLER_CACHE, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, INVALIDATE_TEXTURE_DATA_CACHE, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, INVALIDATE_SHADER_DATA_CACHE, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, INVALIDATE_INSTRUCTION_CACHE, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, INVALIDATE_SHADER_CONSTANT_CACHE, FALSE, TRUE);
+ NVA0C0_QMDV00_06_VAL(qmd, PROGRAM_OFFSET, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_P, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_Q, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_D, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_R, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_S, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_E, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, RELEASE_MEMBAR_TYPE, FE_NONE, FE_SYSMEMBAR);
+ NVA0C0_QMDV00_06_DEF(qmd, CWD_MEMBAR_TYPE, L1_NONE, L1_SYSMEMBAR, L1_MEMBAR);
+ NVA0C0_QMDV00_06_DEF(qmd, QMD_RESERVED_V1_T, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, QMD_RESERVED_V1_U, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, THROTTLED, FALSE, TRUE);
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_E2_A, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_E2_B, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, API_VISIBLE_CALL_LIMIT, _32, NO_CHECK);
+ NVA0C0_QMDV00_06_DEF(qmd, SHARED_MEMORY_BANK_MAPPING, FOUR_BYTES_PER_BANK,
+ EIGHT_BYTES_PER_BANK);
+ NVA0C0_QMDV00_06_DEF(qmd, SAMPLER_INDEX, INDEPENDENTLY, VIA_HEADER_INDEX);
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_E3_A, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CTA_RASTER_WIDTH, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CTA_RASTER_HEIGHT, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CTA_RASTER_DEPTH, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CTA_RASTER_WIDTH_RESUME, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CTA_RASTER_HEIGHT_RESUME, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CTA_RASTER_DEPTH_RESUME, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_V, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_F, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, QMD_RESERVED_V1_W, FALSE, TRUE);
+ NVA0C0_QMDV00_06_VAL(qmd, SHARED_MEMORY_SIZE, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_G, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_VERSION, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_MAJOR_VERSION, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_H, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CTA_THREAD_DIMENSION0, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CTA_THREAD_DIMENSION1, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CTA_THREAD_DIMENSION2, "0x%x");
+ for (int i = 0; i < 8; i++)
+ NVA0C0_QMDV00_06_IDX(qmd, CONSTANT_BUFFER_VALID, i, FALSE, TRUE);
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_I, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, L1_CONFIGURATION,
+ DIRECTLY_ADDRESSABLE_MEMORY_SIZE_16KB,
+ DIRECTLY_ADDRESSABLE_MEMORY_SIZE_32KB,
+ DIRECTLY_ADDRESSABLE_MEMORY_SIZE_48KB);
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_X, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_V1_Y, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, RELEASE0_ADDRESS_LOWER, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, RELEASE0_ADDRESS_UPPER, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_J, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, RELEASE0_REDUCTION_OP, RED_ADD,
+ RED_MIN,
+ RED_MAX,
+ RED_INC,
+ RED_DEC,
+ RED_AND,
+ RED_OR,
+ RED_XOR);
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_K, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, RELEASE0_REDUCTION_FORMAT, UNSIGNED_32, SIGNED_32);
+ NVA0C0_QMDV00_06_DEF(qmd, RELEASE0_REDUCTION_ENABLE, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, RELEASE0_STRUCTURE_SIZE, FOUR_WORDS, ONE_WORD);
+ NVA0C0_QMDV00_06_VAL(qmd, RELEASE0_PAYLOAD, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, RELEASE1_ADDRESS_LOWER, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, RELEASE1_ADDRESS_UPPER, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_L, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, RELEASE1_REDUCTION_OP, RED_ADD,
+ RED_MIN,
+ RED_MAX,
+ RED_INC,
+ RED_DEC,
+ RED_AND,
+ RED_OR,
+ RED_XOR);
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_M, "0x%x");
+ NVA0C0_QMDV00_06_DEF(qmd, RELEASE1_REDUCTION_FORMAT, UNSIGNED_32, SIGNED_32);
+ NVA0C0_QMDV00_06_DEF(qmd, RELEASE1_REDUCTION_ENABLE, FALSE, TRUE);
+ NVA0C0_QMDV00_06_DEF(qmd, RELEASE1_STRUCTURE_SIZE, FOUR_WORDS, ONE_WORD);
+ NVA0C0_QMDV00_06_VAL(qmd, RELEASE1_PAYLOAD, "0x%x");
+ for (int i = 0; i < 8; i++) {
+ NVA0C0_QMDV00_06_VAL(qmd, CONSTANT_BUFFER_ADDR_LOWER, i, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CONSTANT_BUFFER_ADDR_UPPER, i, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, CONSTANT_BUFFER_RESERVED_ADDR, i, "0x%x");
+ NVA0C0_QMDV00_06_IDX(qmd, CONSTANT_BUFFER_INVALIDATE, i, FALSE, TRUE);
+ NVA0C0_QMDV00_06_VAL(qmd, CONSTANT_BUFFER_SIZE, i, "0x%x");
+ }
+ NVA0C0_QMDV00_06_VAL(qmd, SHADER_LOCAL_MEMORY_LOW_SIZE, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_RESERVED_N, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, BARRIER_COUNT, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, SHADER_LOCAL_MEMORY_HIGH_SIZE, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, REGISTER_COUNT, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, SHADER_LOCAL_MEMORY_CRS_SIZE, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, SASS_VERSION, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_A, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_B, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_C, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_D, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_E, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_F, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_G, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_H, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_I, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_J, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_K, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_L, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_M, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, QMD_SPARE_N, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, DEBUG_ID_UPPER, "0x%x");
+ NVA0C0_QMDV00_06_VAL(qmd, DEBUG_ID_LOWER, "0x%x");
+}
projects / mesa.git / commitdiff