reformat list

diff --git a/openpower/sv/rfc/ls013.mdwn b/openpower/sv/rfc/ls013.mdwn
index 8757fab6b490a1c1fc66ff533464dd16fd06bf6a..2c7d14005daede7647e76dca214aed0b6fe12782 100644 (file)
--- a/openpower/sv/rfc/ls013.mdwn
+++ b/openpower/sv/rfc/ls013.mdwn
@@ -65,18 +65,17 @@ instruction in order to effectively implement Reduce-Min/Max.
 **Notes and Observations**:
 
 1. SVP64 REMAP Parallel Reduction needs a single Scalar instruction to
-   work with, for best effectiveness.  With no SFFS minimum/maximum instructions
-   Simple-V min/max Parallel Reduction is severely compromised.
-2. Once one FP min/max mode is implemented the rest are not much more
-   hardware.
-3.  There exists similar instructions in VSX (not IEEE754-2019 though).
-   This is frequently used to justify not
-   adding them. However SVP64/VSX may have different meaning from SVP64/SFFS,
-    so it is *really* crucial to have SFFS ops even if "equivalent" to VSX
-   in order for SVP64 to not be compromised (non-orthogonal).
+    work with, for best effectiveness.  With no SFFS minimum/maximum
+    instructions Simple-V min/max Parallel Reduction is severely compromised.
+2. Once one FP min/max mode is implemented the rest are not much more hardware.
+3. There exists similar instructions in VSX (not IEEE754-2019 though).
+    This is frequently used to justify not adding them. However SVP64/VSX may
+    have different meaning from SVP64/SFFS, so it is *really* crucial to have
+    SFFS ops even if "equivalent" to VSX in order for SVP64 to not be
+    compromised (non-orthogonal).
 4. FP min/max are rather complex to implement in software, the most commonly
-    used FP max function `fmax` from glibc compiled for SFFS is an
-    astounding 32 instructions.
+    used FP max function `fmax` from glibc compiled for SFFS is an astounding
+    32 instructions.
 
 **Changes**