bpf: add xBPF ISA

This patch adds support for xBPF, another ISA targetting the BPF
virtual architecture. For now, the primary difference between eBPF
and xBPF is that xBPF supports indirect calls through the
'call %reg' form of the call instruction.

bfd/
	* archures.c (bfd_mach_xbpf): Define.
	* bfd-in2.h: Regenerate.
	* cpu-bpf.c (bfd_xbpf_arch) New.
	(bfd_bpf_arch) Update next in list field to point to xbpf arch.

cpu/
	* bpf.cpu (arch bpf): Add xbpf mach and isas.
	(define-xbpf-isa) New pmacro.
	(all-isas) Add xbpfle,xbpfbe.
	(endian-isas): New pmacro.
	(mach xbpf): New.
	(model xbpf-def): Likewise.
	(h-gpr): Add xbpf mach.
	(f-dstle, f-srcle, dstle, srcle): Add xbpfle isa.
	(f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa.
	(define-alu-insn-un): Use new endian-isas pmacro.
	(define-alu-insn-bin, define-alu-insn-mov): Likewise.
	(define-endian-insn, define-lddw): Likewise.
	(dlind, dxli, dxsi, dsti): Likewise.
	(define-cond-jump-insn, define-call-insn): Likewise.
	(define-atomic-insns): Likewise.

gas/
	* config/tc-bpf.c: Add option -mxbpf to select xbpf isa.
	* testsuite/gas/bpf/indcall-1.d: New file.
	* testsuite/gas/bpf/indcall-1.s: Likewise.
	* testsuite/gas/bpf/indcall-bad-1.l: Likewise.
	* testsuite/gas/bpf/indcall-bad-1.s: Likewise.
	* testsuite/gas/bpf/bpf.exp: Run new tests.

opcodes/
	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-opc.h: Likewise.
	* disassemble.c (disassemble_init_for_target): Set bits for xBPF
	ISA when appropriate.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 8a2677791fa3b61c73495d9c7b5a348bd28b8070..616b22f1600ea7b349dc81254a8c05af655fd63f 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,10 @@
+2020-08-26  David Faust  <david.faust@oracle.com>
+
+       * archures.c (bfd_mach_xbpf): Define.
+       * bfd-in2.h: Regenerate.
+       * cpu-bpf.c (bfd_xbpf_arch) New.
+       (bfd_bpf_arch) Update next in list field to point to xbpf arch.
+
 2020-08-26  Alan Modra  <amodra@gmail.com>
 
        * archures.c (bfd_mach_ck860): Define.

diff --git a/bfd/archures.c b/bfd/archures.c
index 715abc7fadfb6aa5f50a10fce5f6dd5f473f5809..969fa20873997a2c641c9cbd10d23d50b8319f0d 100644 (file)
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -411,6 +411,7 @@ DESCRIPTION
 .#define bfd_mach_iq10         2
 .  bfd_arch_bpf,       {* Linux eBPF.  *}
 .#define bfd_mach_bpf          1
+.#define bfd_mach_xbpf         2
 .  bfd_arch_epiphany,  {* Adapteva EPIPHANY.  *}
 .#define bfd_mach_epiphany16   1
 .#define bfd_mach_epiphany32   2

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index a16d03780e2fa2f8428d36e1e180a577c203737e..3c85b073013872dc2023e0f7b647b30eebd8dd83 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1811,6 +1811,7 @@ enum bfd_architecture
 #define bfd_mach_iq10          2
   bfd_arch_bpf,       /* Linux eBPF.  */
 #define bfd_mach_bpf           1
+#define bfd_mach_xbpf          2
   bfd_arch_epiphany,  /* Adapteva EPIPHANY.  */
 #define bfd_mach_epiphany16    1
 #define bfd_mach_epiphany32    2

diff --git a/bfd/cpu-bpf.c b/bfd/cpu-bpf.c
index edd24c6800eb30675a497a5ff9e6ca2b24fc5de4..947d7861331f933f45ca275cc5f3d6ec5a7aea66 100644 (file)
--- a/bfd/cpu-bpf.c
+++ b/bfd/cpu-bpf.c
@@ -23,6 +23,26 @@
 #include "bfd.h"
 #include "libbfd.h"
 
+
+static const bfd_arch_info_type bfd_xbpf_arch =
+{
+  64,                          /* Bits per word.  */
+  64,                          /* Bits per address.  */
+  8,                           /* Bits per byte.  */
+  bfd_arch_bpf,                        /* Architecture.  */
+  bfd_mach_xbpf,               /* Machine.  */
+  "bpf",                       /* Architecture name.  */
+  "xbpf",                      /* Machine name.  */
+  3,                           /* Section align power.  */
+  FALSE,                       /* The default ?  */
+  bfd_default_compatible,      /* Architecture comparison fn.  */
+  bfd_default_scan,            /* String to architecture convert fn.  */
+  bfd_arch_default_fill,       /* Default fill.  */
+  NULL,                                /* Next in list.  */
+  0 /* Maximum offset of a reloc from the start of an insn.  */
+};
+
+
 const bfd_arch_info_type bfd_bpf_arch =
 {
   64,                          /* Bits per word.  */
@@ -37,6 +57,6 @@ const bfd_arch_info_type bfd_bpf_arch =
   bfd_default_compatible,      /* Architecture comparison fn.  */
   bfd_default_scan,            /* String to architecture convert fn.  */
   bfd_arch_default_fill,       /* Default fill.  */
-  NULL,                                /* Next in list.  */
+  &bfd_xbpf_arch,              /* Next in list.  */
   0 /* Maximum offset of a reloc from the start of an insn.  */
 };

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index 053760d446573daa25ffccdbdf4cf29830685521..f81024848258a865ea947e6ec0477fd0e2731473 100644 (file)
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,21 @@
+2020-08-26  David Faust  <david.faust@oracle.com>
+
+       * bpf.cpu (arch bpf): Add xbpf mach and isas.
+       (define-xbpf-isa) New pmacro.
+       (all-isas) Add xbpfle,xbpfbe.
+       (endian-isas): New pmacro.
+       (mach xbpf): New.
+       (model xbpf-def): Likewise.
+       (h-gpr): Add xbpf mach.
+       (f-dstle, f-srcle, dstle, srcle): Add xbpfle isa.
+       (f-dstbe, f-srcbe, dstbe, srcbe): Add xbpfbe isa.
+       (define-alu-insn-un): Use new endian-isas pmacro.
+       (define-alu-insn-bin, define-alu-insn-mov): Likewise.
+       (define-endian-insn, define-lddw): Likewise.
+       (dlind, dxli, dxsi, dsti): Likewise.
+       (define-cond-jump-insn, define-call-insn): Likewise.
+       (define-atomic-insns): Likewise.
+
 2020-07-04  Nick Clifton  <nickc@redhat.com>
 
        Binutils 2.35 branch created.

diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu
index 95290f6f4e11a7a12c321ac61d774929fe29620e..966500e36d188c94b88acbbfe73791d89aea6608 100644 (file)
--- a/cpu/bpf.cpu
+++ b/cpu/bpf.cpu
@@ -36,8 +36,8 @@
   ;; It is confusing that the simulator follows the emulated memory
   ;; access conventions for fetching instructions by pieces...
   (default-alignment unaligned)
-  (machs bpf)
-  (isas ebpfle ebpfbe))
+  (machs bpf xbpf)
+  (isas ebpfle ebpfbe xbpfle xbpfbe))
 
 ;;;; The ISAs
 
@@ -105,18 +105,33 @@
 (define-bpf-isa le)
 (define-bpf-isa be)
 
-(define-pmacro all-isas () (ISA ebpfle,ebpfbe))
+(define-pmacro (define-xbpf-isa x-endian)
+  (define-isa
+    (name (.sym xbpf x-endian))
+    (comment "The xBPF instruction set")
+    (default-insn-word-bitsize 64)
+    (default-insn-bitsize 64)
+    (base-insn-bitsize 64)))
+
+(define-xbpf-isa le)
+(define-xbpf-isa be)
+
+(define-pmacro all-isas () (ISA ebpfle,ebpfbe,xbpfle,xbpfbe))
+(define-pmacro xbpf-isas () (ISA xbpfle,xbpfbe))
+
+(define-pmacro (endian-isas x-endian)
+  ((ISA (.sym ebpf x-endian) (.sym xbpf x-endian))))
 
 ;;;; Hardware Hierarchy
 
 ;;
-;;     bpf         architecture
-;;      |
-;;    bpfbf        cpu-family
-;;      |
-;;     bpf         machine
-;;      |
-;;   bpf-def       model
+;;         bpf            architecture
+;;          |
+;;        bpfbf           cpu-family
+;;      /       \
+;;     bpf     xbpf       machine
+;;      |       |
+;;   bpf-def  xbpf-def    model
 
 (define-cpu
   (name bpfbf)
@@ -143,6 +158,25 @@
     () ; profile action (default)
     ))
 
+(define-mach
+  (name xbpf)
+  (comment "Experimental BPF")
+  (cpu bpfbf)
+  (isas ebpfle ebpfbe xbpfle xbpfbe))
+
+(define-model
+  (name xbpf-def)
+  (comment "xBPF default model")
+  (mach xbpf)
+  (unit u-exec "execution unit" ()
+    1 ; issue
+    1 ; done
+    () ; state
+    () ; inputs
+    () ; outputs
+    () ; profile action (default)
+    ))
+
 ;;;; Hardware Elements
 
 ;; eBPF programs can access 10 general-purpose registers which are
@@ -151,7 +185,7 @@
 (define-hardware
   (name h-gpr)
   (comment "General Purpose Registers")
-  (attrs all-isas (MACH bpf))
+  (attrs all-isas (MACH bpf xbpf))
   (type register DI (16))
   (indices keyword "%"
            ;; XXX the frame pointer fp is read-only, so it should
@@ -259,11 +293,11 @@
 ;; NOT use registers, where endianness is irrelevant i.e. f-regs is a
 ;; constant 0 opcode.
 
-(dwf f-dstle "eBPF dst register field" ((ISA ebpfle)) 8 8 3 4 UINT)
-(dwf f-srcle "eBPF source register field" ((ISA ebpfle)) 8 8 7 4 UINT)
+(dwf f-dstle "eBPF dst register field" ((ISA ebpfle xbpfle)) 8 8 3 4 UINT)
+(dwf f-srcle "eBPF source register field" ((ISA ebpfle xbpfle)) 8 8 7 4 UINT)
 
-(dwf f-dstbe "eBPF dst register field" ((ISA ebpfbe)) 8 8 7 4 UINT)
-(dwf f-srcbe "eBPF source register field" ((ISA ebpfbe)) 8 8 3 4 UINT)
+(dwf f-dstbe "eBPF dst register field" ((ISA ebpfbe xbpfbe)) 8 8 7 4 UINT)
+(dwf f-srcbe "eBPF source register field" ((ISA ebpfbe xbpfbe)) 8 8 3 4 UINT)
 
 (dwf f-regs "eBPF registers field" (all-isas) 8 8 7 8 UINT)
 
@@ -303,11 +337,11 @@
 ;; A couple of source and destination register operands are defined
 ;; for each ISA: ebpfle and ebpfbe.
 
-(dno dstle "destination register" ((ISA ebpfle)) h-gpr f-dstle)
-(dno srcle "source register" ((ISA ebpfle)) h-gpr f-srcle)
+(dno dstle "destination register" ((ISA ebpfle xbpfle)) h-gpr f-dstle)
+(dno srcle "source register" ((ISA ebpfle xbpfle)) h-gpr f-srcle)
 
-(dno dstbe "destination register" ((ISA ebpfbe)) h-gpr f-dstbe)
-(dno srcbe "source register" ((ISA ebpfbe)) h-gpr f-srcbe)
+(dno dstbe "destination register" ((ISA ebpfbe xbpfbe)) h-gpr f-dstbe)
+(dno srcbe "source register" ((ISA ebpfbe xbpfbe)) h-gpr f-srcbe)
 
 ;; Jump instructions have a 16-bit PC-relative address.
 ;; CALL instructions have a 32-bit PC-relative address.
@@ -378,7 +412,7 @@
                  x-endian x-mode x-semop)
   (dni (.sym x-basename x-suffix x-endian)
        (.str x-basename x-suffix)
-       ((ISA (.sym ebpf x-endian)))
+       (endian-isas x-endian)
        (.str x-basename x-suffix " $dst" x-endian)
        (+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
           x-op-class OP_SRC_K x-op-code)
@@ -391,7 +425,7 @@
     ;; dst = dst OP immediate
     (dni (.sym x-basename x-suffix "i" x-endian)
          (.str x-basename x-suffix " immediate")
-         ((ISA (.sym ebpf x-endian)))
+         (endian-isas x-endian)
          (.str x-basename x-suffix " $dst" x-endian ",$imm32")
          (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
             x-op-class OP_SRC_K x-op-code)
@@ -400,7 +434,7 @@
     ;; dst = dst OP src
     (dni (.sym x-basename x-suffix "r" x-endian)
          (.str x-basename x-suffix " register")
-         ((ISA (.sym ebpf x-endian)))
+         (endian-isas x-endian)
          (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
          (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
             x-op-class OP_SRC_X x-op-code)
@@ -413,7 +447,7 @@
   (begin
     (dni (.sym mov x-suffix "i" x-endian)
          (.str mov x-suffix " immediate")
-         ((ISA (.sym ebpf x-endian)))
+         (endian-isas x-endian)
          (.str x-basename x-suffix " $dst" x-endian ",$imm32")
          (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
             x-op-class OP_SRC_K x-op-code)
@@ -421,7 +455,7 @@
          ())
     (dni (.sym mov x-suffix "r" x-endian)
          (.str mov x-suffix " register")
-         ((ISA (.sym ebpf x-endian)))
+         (endian-isas x-endian)
          (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
          (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
             x-op-class OP_SRC_X x-op-code)
@@ -483,7 +517,7 @@
 (define-pmacro (define-endian-insn x-suffix x-op-src x-endian)
   (dni (.sym "end" x-suffix x-endian)
        (.str "end" x-suffix " register")
-       ((ISA (.sym ebpf x-endian)))
+       (endian-isas x-endian)
        (.str "end" x-suffix " $dst" x-endian ",$endsize")
        (+  (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) endsize
            OP_CLASS_ALU x-op-src OP_CODE_END)
@@ -508,7 +542,7 @@
 (define-pmacro (define-lddw x-endian)
   (dni (.sym lddw x-endian)
        (.str "lddw" x-endian)
-       ((ISA (.sym ebpf x-endian)))
+       (endian-isas x-endian)
        (.str "lddw $dst" x-endian ",$imm64")
        (+ imm64 (f-offset16 0) ((.sym f-src x-endian) 0)
           (.sym dst x-endian)
@@ -557,7 +591,7 @@
 (define-pmacro (dlind x-suffix x-size x-endian x-smode)
   (dni (.sym "ldind" x-suffix x-endian)
        (.str "ldind" x-suffix)
-       ((ISA (.sym ebpf x-endian)))
+       (endian-isas x-endian)
        (.str "ldind" x-suffix " $src" x-endian ",$imm32")
        (+ imm32 (f-offset16 0) ((.sym f-dst x-endian) 0) (.sym src x-endian)
           OP_CLASS_LD OP_MODE_IND (.sym OP_SIZE_ x-size))
@@ -598,7 +632,7 @@
 (define-pmacro (dxli x-basename x-suffix x-size x-endian x-mode)
   (dni (.sym x-basename x-suffix x-endian)
        (.str x-basename x-suffix)
-       ((ISA (.sym ebpf x-endian)))
+       (endian-isas x-endian)
        (.str x-basename x-suffix " $dst" x-endian ",[$src" x-endian "+$offset16]")
        (+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
           OP_CLASS_LDX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
@@ -610,7 +644,7 @@
 (define-pmacro (dxsi x-basename x-suffix x-size x-endian x-mode)
   (dni (.sym x-basename x-suffix x-endian)
        (.str x-basename x-suffix)
-       ((ISA (.sym ebpf x-endian)))
+       (endian-isas x-endian)
        (.str x-basename x-suffix " [$dst" x-endian "+$offset16],$src" x-endian)
        (+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
           OP_CLASS_STX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
@@ -643,7 +677,7 @@
 (define-pmacro (dsti x-suffix x-size x-endian x-mode)
   (dni (.sym "st" x-suffix x-endian)
        (.str "st" x-suffix)
-       ((ISA (.sym ebpf x-endian)))
+       (endian-isas x-endian)
        (.str "st" x-suffix " [$dst" x-endian "+$offset16],$imm32")
        (+ imm32 offset16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
           OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM)
@@ -677,7 +711,7 @@
   (begin
     (dni (.sym j x-cond x-suffix i x-endian)
          (.str j x-cond x-suffix " i")
-         ((ISA (.sym ebpf x-endian)))
+         (endian-isas x-endian)
          (.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16")
          (+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
             x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code))
@@ -688,7 +722,7 @@
          ())
     (dni (.sym j x-cond x-suffix r x-endian)
          (.str j x-cond x-suffix " r")
-         ((ISA (.sym ebpf x-endian)))
+         (endian-isas x-endian)
          (.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16")
          (+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
             x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code))
@@ -728,7 +762,7 @@
 (define-pmacro (define-call-insn x-endian)
   (dni (.sym call x-endian)
        "call"
-       ((ISA (.sym ebpf x-endian)))
+       (endian-isas x-endian)
        "call $disp32"
        (+ disp32 (f-offset16 0) (f-regs 0)
           OP_CLASS_JMP OP_SRC_K OP_CODE_CALL)
@@ -739,6 +773,20 @@
 (define-call-insn le)
 (define-call-insn be)
 
+(define-pmacro (define-callr-insn x-endian)
+  (dni (.sym callr x-endian)
+       "callr"
+       ((ISA (.sym xbpf x-endian)))
+       (.str "call $dst" x-endian)
+       (+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
+          OP_CLASS_JMP OP_SRC_X OP_CODE_CALL)
+       (c-call VOID
+               "bpfbf_callr" (ifield (.sym f-dst x-endian)))
+       ()))
+
+(define-callr-insn le)
+(define-callr-insn be)
+
 ;; The jump-always and `exit' instructions dont make use of either
 ;; source nor destination registers, so only one variant per
 ;; instruction is defined.
@@ -773,7 +821,7 @@
   (begin
     (dni (.str "xadddw" x-endian)
          "xadddw"
-         ((ISA (.sym ebpf x-endian)))
+         (endian-isas x-endian)
          (.str "xadddw [$dst" x-endian "+$offset16],$src" x-endian)
          (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
             offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX)
@@ -781,7 +829,7 @@
          ())
     (dni (.str "xaddw" x-endian)
          "xaddw"
-         ((ISA (.sym ebpf x-endian)))
+         (endian-isas x-endian)
          (.str "xaddw [$dst" x-endian "+$offset16],$src" x-endian)
          (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
             offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index d8c92dbe28ed91c68a12b2539b91a15cab06083c..4e367a4dade743075a219b24b822a134ae77a104 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,12 @@
+2020-08-26  David Faust  <david.faust@oracle.com>
+
+       * config/tc-bpf.c: Add option -mxbpf to select xbpf isa.
+       * testsuite/gas/bpf/indcall-1.d: New file.
+       * testsuite/gas/bpf/indcall-1.s: Likewise.
+       * testsuite/gas/bpf/indcall-bad-1.l: Likewise.
+       * testsuite/gas/bpf/indcall-bad-1.s: Likewise.
+       * testsuite/gas/bpf/bpf.exp: Run new tests.
+
 2020-08-25  Alan Modra  <amodra@gmail.com>
 
        PR26501

diff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c
index 026a631280deddbed87876e47790bbf0a91917ca..34b2adfc682add543bbe69d546cdb7cb8fbe471c 100644 (file)
--- a/gas/config/tc-bpf.c
+++ b/gas/config/tc-bpf.c
@@ -97,13 +97,15 @@ static CGEN_BITSET *bpf_isa;
 enum options
 {
   OPTION_LITTLE_ENDIAN = OPTION_MD_BASE,
-  OPTION_BIG_ENDIAN
+  OPTION_BIG_ENDIAN,
+  OPTION_XBPF
 };
 
 struct option md_longopts[] =
 {
   { "EL", no_argument, NULL, OPTION_LITTLE_ENDIAN },
   { "EB", no_argument, NULL, OPTION_BIG_ENDIAN },
+  { "mxbpf", no_argument, NULL, OPTION_XBPF },
   { NULL,          no_argument, NULL, 0 },
 };
 
@@ -117,6 +119,10 @@ extern int target_big_endian;
    arguments.  */
 static int set_target_endian = 0;
 
+static int target_xbpf = 0;
+
+static int set_xbpf = 0;
+
 int
 md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
 {
@@ -130,6 +136,10 @@ md_parse_option (int c, const char * arg ATTRIBUTE_UNUSED)
       set_target_endian = 1;
       target_big_endian = 0;
       break;
+    case OPTION_XBPF:
+      set_xbpf = 1;
+      target_xbpf = 1;
+      break;
     default:
       return 0;
     }
@@ -143,7 +153,8 @@ md_show_usage (FILE * stream)
   fprintf (stream, _("\nBPF options:\n"));
   fprintf (stream, _("\
   --EL                 generate code for a little endian machine\n\
-  --EB                 generate code for a big endian machine\n"));
+  --EB                 generate code for a big endian machine\n\
+  -mxbpf                generate xBPF instructions\n"));
 }
 
 \f
@@ -163,12 +174,27 @@ md_begin (void)
 #endif
     }
 
+  /* If not specified in the command line, use eBPF rather
+     than xBPF.  */
+  if (!set_xbpf)
+      target_xbpf = 0;
+
   /* Set the ISA, which depends on the target endianness. */
   bpf_isa = cgen_bitset_create (ISA_MAX);
   if (target_big_endian)
-    cgen_bitset_set (bpf_isa, ISA_EBPFBE);
+    {
+      if (target_xbpf)
+       cgen_bitset_set (bpf_isa, ISA_XBPFBE);
+      else
+       cgen_bitset_set (bpf_isa, ISA_EBPFBE);
+    }
   else
-    cgen_bitset_set (bpf_isa, ISA_EBPFLE);
+    {
+      if (target_xbpf)
+       cgen_bitset_set (bpf_isa, ISA_XBPFLE);
+      else
+       cgen_bitset_set (bpf_isa, ISA_EBPFLE);
+    }
 
   /* Set the machine number and endian.  */
   gas_cgen_cpu_desc = bpf_cgen_cpu_open (CGEN_CPU_OPEN_ENDIAN,

diff --git a/gas/testsuite/gas/bpf/bpf.exp b/gas/testsuite/gas/bpf/bpf.exp
index 6225d0b3589b40ead684355a6bb980363aa91793..242b1902ba024342b05899a825c2db25969eca05 100644 (file)
--- a/gas/testsuite/gas/bpf/bpf.exp
+++ b/gas/testsuite/gas/bpf/bpf.exp
@@ -38,4 +38,7 @@ if {[istarget bpf*-*-*]} {
     run_dump_test exit-be
     run_dump_test atomic-be
     run_dump_test data-be
+
+    run_dump_test indcall-1
+    run_list_test indcall-bad-1
 }

diff --git a/gas/testsuite/gas/bpf/indcall-1.d b/gas/testsuite/gas/bpf/indcall-1.d
new file mode 100644 (file)
index 0000000..e61e125
--- /dev/null
+++ b/gas/testsuite/gas/bpf/indcall-1.d
@@ -0,0 +1,22 @@
+#as: -mxbpf --EL
+#objdump: -mxbpf -dr
+#name: BPF indirect call 1
+
+.*: +file format .*bpf.*
+
+Disassembly of section \.text:
+
+0000000000000000 <main>:
+   0:  b7 00 00 00 01 00 00 00         mov %r0,1
+   8:  b7 01 00 00 01 00 00 00         mov %r1,1
+  10:  b7 02 00 00 02 00 00 00         mov %r2,2
+  18:  18 06 00 00 38 00 00 00         lddw %r6,0x38
+  20:  00 00 00 00 00 00 00 00[    ]*
+                       18: R_BPF_INSN_64       .text
+  28:  8d 06 00 00 00 00 00 00         call %r6
+  30:  95 00 00 00 00 00 00 00         exit
+
+0000000000000038 <bar>:
+  38:  b7 00 00 00 00 00 00 00         mov %r0,0
+  40:  95 00 00 00 00 00 00 00         exit
+#pass

diff --git a/gas/testsuite/gas/bpf/indcall-1.s b/gas/testsuite/gas/bpf/indcall-1.s
new file mode 100644 (file)
index 0000000..5d49e41
--- /dev/null
+++ b/gas/testsuite/gas/bpf/indcall-1.s
@@ -0,0 +1,14 @@
+
+    .text
+    .align 4
+main:
+    mov %r0, 1
+    mov %r1, 1
+    mov %r2, 2
+    lddw %r6, bar
+    call %r6
+    exit
+
+bar:
+    mov %r0, 0
+    exit

diff --git a/gas/testsuite/gas/bpf/indcall-bad-1.l b/gas/testsuite/gas/bpf/indcall-bad-1.l
new file mode 100644 (file)
index 0000000..510ec6e
--- /dev/null
+++ b/gas/testsuite/gas/bpf/indcall-bad-1.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.* Error: illegal operand `call %r6'
+#pass

diff --git a/gas/testsuite/gas/bpf/indcall-bad-1.s b/gas/testsuite/gas/bpf/indcall-bad-1.s
new file mode 100644 (file)
index 0000000..0cdc4ab
--- /dev/null
+++ b/gas/testsuite/gas/bpf/indcall-bad-1.s
@@ -0,0 +1 @@
+    call %r6

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index f1951d48817bdaf01aa80c50abd74075d989e3ce..af4dac6105dbee5704602480a34cf2277f21811b 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,12 @@
+2020-08-26  David Faust  <david.faust@oracle.com>
+
+       * bpf-desc.c: Regenerate.
+       * bpf-desc.h: Likewise.
+       * bpf-opc.c: Likewise.
+       * bpf-opc.h: Likewise.
+       * disassemble.c (disassemble_init_for_target): Set bits for xBPF
+       ISA when appropriate.
+
 2020-08-25  Alan Modra  <amodra@gmail.com>
 
        PR 26504

diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c
index 6319f100f3ca001ff09fb944acc8fb5f56e6186e..6914ce98e62d6074cb65986534b95defee1c2045 100644 (file)
--- a/opcodes/bpf-desc.c
+++ b/opcodes/bpf-desc.c
@@ -48,6 +48,7 @@ static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
 {
   { "base", MACH_BASE },
   { "bpf", MACH_BPF },
+  { "xbpf", MACH_XBPF },
   { "max", MACH_MAX },
   { 0, 0 }
 };
@@ -56,6 +57,8 @@ static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
 {
   { "ebpfle", ISA_EBPFLE },
   { "ebpfbe", ISA_EBPFBE },
+  { "xbpfle", ISA_XBPFLE },
+  { "xbpfbe", ISA_XBPFBE },
   { "max", ISA_MAX },
   { 0, 0 }
 };
@@ -121,6 +124,8 @@ const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] =
 static const CGEN_ISA bpf_cgen_isa_table[] = {
   { "ebpfle", 64, 64, 64, 128 },
   { "ebpfbe", 64, 64, 64, 128 },
+  { "xbpfle", 64, 64, 64, 128 },
+  { "xbpfbe", 64, 64, 64, 128 },
   { 0, 0, 0, 0, 0 }
 };
 
@@ -128,6 +133,7 @@ static const CGEN_ISA bpf_cgen_isa_table[] = {
 
 static const CGEN_MACH bpf_cgen_mach_table[] = {
   { "bpf", "bpf", MACH_BPF, 0 },
+  { "xbpf", "xbpf", MACH_XBPF, 0 },
   { 0, 0, 0, 0 }
 };
 
@@ -163,14 +169,14 @@ CGEN_KEYWORD bpf_cgen_opval_h_gpr =
 
 const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
 {
-  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
-  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
-  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
-  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
-  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
-  { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF), 0 } }, { { 1, "\xc0" } } } } },
-  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
-  { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
+  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
+  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
+  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
+  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
+  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
+  { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF)|(1<<MACH_XBPF), 0 } }, { { 1, "\xf0" } } } } },
+  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
+  { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 };
 
@@ -183,24 +189,24 @@ const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
 
 const CGEN_IFLD bpf_cgen_ifld_table[] =
 {
-  { BPF_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_OP_CODE, "f-op-code", 0, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_OP_SRC, "f-op-src", 0, 8, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
-  { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
-  { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
-  { BPF_F_SRCBE, "f-srcbe", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
-  { BPF_F_REGS, "f-regs", 8, 8, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_OFFSET16, "f-offset16", 16, 16, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_IMM32, "f-imm32", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_IMM64_A, "f-imm64-a", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_IMM64_B, "f-imm64-b", 64, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_IMM64_C, "f-imm64-c", 96, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
-  { BPF_F_IMM64, "f-imm64", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+  { BPF_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_OP_CODE, "f-op-code", 0, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_OP_SRC, "f-op-src", 0, 8, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }  },
+  { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }  },
+  { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }  },
+  { BPF_F_SRCBE, "f-srcbe", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }  },
+  { BPF_F_REGS, "f-regs", 8, 8, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_OFFSET16, "f-offset16", 16, 16, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_IMM32, "f-imm32", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_IMM64_A, "f-imm64-a", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_IMM64_B, "f-imm64-b", 64, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_IMM64_C, "f-imm64-c", 96, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
+  { BPF_F_IMM64, "f-imm64", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 };
 
@@ -233,47 +239,47 @@ const CGEN_OPERAND bpf_cgen_operand_table[] =
 /* pc: program counter */
   { "pc", BPF_OPERAND_PC, HW_H_PC, 0, 0,
     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_NIL] } },
-    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+    { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 /* dstle: destination register */
   { "dstle", BPF_OPERAND_DSTLE, HW_H_GPR, 3, 4,
     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTLE] } },
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }  },
 /* srcle: source register */
   { "srcle", BPF_OPERAND_SRCLE, HW_H_GPR, 7, 4,
     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCLE] } },
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }  },
 /* dstbe: destination register */
   { "dstbe", BPF_OPERAND_DSTBE, HW_H_GPR, 7, 4,
     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_DSTBE] } },
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }  },
 /* srcbe: source register */
   { "srcbe", BPF_OPERAND_SRCBE, HW_H_GPR, 3, 4,
     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_SRCBE] } },
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }  },
 /* disp16: 16-bit PC-relative address */
   { "disp16", BPF_OPERAND_DISP16, HW_H_SINT, 15, 16,
     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
-    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 /* disp32: 32-bit PC-relative address */
   { "disp32", BPF_OPERAND_DISP32, HW_H_SINT, 31, 32,
     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
-    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+    { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 /* imm32: 32-bit immediate */
   { "imm32", BPF_OPERAND_IMM32, HW_H_SINT, 31, 32,
     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 /* offset16: 16-bit offset */
   { "offset16", BPF_OPERAND_OFFSET16, HW_H_SINT, 15, 16,
     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 /* imm64: 64-bit immediate */
   { "imm64", BPF_OPERAND_IMM64, HW_H_SINT64, 31, 96,
     { 3, { (const PTR) &BPF_F_IMM64_MULTI_IFIELD[0] } },
-    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+    { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 /* endsize: endianness size immediate: 16, 32 or 64 */
   { "endsize", BPF_OPERAND_ENDSIZE, HW_H_UINT, 31, 32,
     { 0, { (const PTR) &bpf_cgen_ifld_table[BPF_F_IMM32] } },
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }  },
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 /* sentinel */
   { 0, 0, 0, 0, 0,
     { 0, { (const PTR) 0 } },
@@ -297,1197 +303,1207 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
 /* add $dstle,$imm32 */
   {
     BPF_INSN_ADDILE, "addile", "add", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* add $dstle,$srcle */
   {
     BPF_INSN_ADDRLE, "addrle", "add", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* add32 $dstle,$imm32 */
   {
     BPF_INSN_ADD32ILE, "add32ile", "add32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* add32 $dstle,$srcle */
   {
     BPF_INSN_ADD32RLE, "add32rle", "add32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* sub $dstle,$imm32 */
   {
     BPF_INSN_SUBILE, "subile", "sub", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* sub $dstle,$srcle */
   {
     BPF_INSN_SUBRLE, "subrle", "sub", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* sub32 $dstle,$imm32 */
   {
     BPF_INSN_SUB32ILE, "sub32ile", "sub32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* sub32 $dstle,$srcle */
   {
     BPF_INSN_SUB32RLE, "sub32rle", "sub32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mul $dstle,$imm32 */
   {
     BPF_INSN_MULILE, "mulile", "mul", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mul $dstle,$srcle */
   {
     BPF_INSN_MULRLE, "mulrle", "mul", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mul32 $dstle,$imm32 */
   {
     BPF_INSN_MUL32ILE, "mul32ile", "mul32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mul32 $dstle,$srcle */
   {
     BPF_INSN_MUL32RLE, "mul32rle", "mul32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* div $dstle,$imm32 */
   {
     BPF_INSN_DIVILE, "divile", "div", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* div $dstle,$srcle */
   {
     BPF_INSN_DIVRLE, "divrle", "div", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* div32 $dstle,$imm32 */
   {
     BPF_INSN_DIV32ILE, "div32ile", "div32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* div32 $dstle,$srcle */
   {
     BPF_INSN_DIV32RLE, "div32rle", "div32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* or $dstle,$imm32 */
   {
     BPF_INSN_ORILE, "orile", "or", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* or $dstle,$srcle */
   {
     BPF_INSN_ORRLE, "orrle", "or", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* or32 $dstle,$imm32 */
   {
     BPF_INSN_OR32ILE, "or32ile", "or32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* or32 $dstle,$srcle */
   {
     BPF_INSN_OR32RLE, "or32rle", "or32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* and $dstle,$imm32 */
   {
     BPF_INSN_ANDILE, "andile", "and", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* and $dstle,$srcle */
   {
     BPF_INSN_ANDRLE, "andrle", "and", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* and32 $dstle,$imm32 */
   {
     BPF_INSN_AND32ILE, "and32ile", "and32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* and32 $dstle,$srcle */
   {
     BPF_INSN_AND32RLE, "and32rle", "and32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* lsh $dstle,$imm32 */
   {
     BPF_INSN_LSHILE, "lshile", "lsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* lsh $dstle,$srcle */
   {
     BPF_INSN_LSHRLE, "lshrle", "lsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* lsh32 $dstle,$imm32 */
   {
     BPF_INSN_LSH32ILE, "lsh32ile", "lsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* lsh32 $dstle,$srcle */
   {
     BPF_INSN_LSH32RLE, "lsh32rle", "lsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* rsh $dstle,$imm32 */
   {
     BPF_INSN_RSHILE, "rshile", "rsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* rsh $dstle,$srcle */
   {
     BPF_INSN_RSHRLE, "rshrle", "rsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* rsh32 $dstle,$imm32 */
   {
     BPF_INSN_RSH32ILE, "rsh32ile", "rsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* rsh32 $dstle,$srcle */
   {
     BPF_INSN_RSH32RLE, "rsh32rle", "rsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mod $dstle,$imm32 */
   {
     BPF_INSN_MODILE, "modile", "mod", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mod $dstle,$srcle */
   {
     BPF_INSN_MODRLE, "modrle", "mod", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mod32 $dstle,$imm32 */
   {
     BPF_INSN_MOD32ILE, "mod32ile", "mod32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mod32 $dstle,$srcle */
   {
     BPF_INSN_MOD32RLE, "mod32rle", "mod32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* xor $dstle,$imm32 */
   {
     BPF_INSN_XORILE, "xorile", "xor", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* xor $dstle,$srcle */
   {
     BPF_INSN_XORRLE, "xorrle", "xor", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* xor32 $dstle,$imm32 */
   {
     BPF_INSN_XOR32ILE, "xor32ile", "xor32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* xor32 $dstle,$srcle */
   {
     BPF_INSN_XOR32RLE, "xor32rle", "xor32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* arsh $dstle,$imm32 */
   {
     BPF_INSN_ARSHILE, "arshile", "arsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* arsh $dstle,$srcle */
   {
     BPF_INSN_ARSHRLE, "arshrle", "arsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* arsh32 $dstle,$imm32 */
   {
     BPF_INSN_ARSH32ILE, "arsh32ile", "arsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* arsh32 $dstle,$srcle */
   {
     BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* neg $dstle */
   {
     BPF_INSN_NEGLE, "negle", "neg", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* neg32 $dstle */
   {
     BPF_INSN_NEG32LE, "neg32le", "neg32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mov $dstle,$imm32 */
   {
     BPF_INSN_MOVILE, "movile", "mov", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mov $dstle,$srcle */
   {
     BPF_INSN_MOVRLE, "movrle", "mov", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mov32 $dstle,$imm32 */
   {
     BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* mov32 $dstle,$srcle */
   {
     BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* add $dstbe,$imm32 */
   {
     BPF_INSN_ADDIBE, "addibe", "add", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* add $dstbe,$srcbe */
   {
     BPF_INSN_ADDRBE, "addrbe", "add", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* add32 $dstbe,$imm32 */
   {
     BPF_INSN_ADD32IBE, "add32ibe", "add32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* add32 $dstbe,$srcbe */
   {
     BPF_INSN_ADD32RBE, "add32rbe", "add32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* sub $dstbe,$imm32 */
   {
     BPF_INSN_SUBIBE, "subibe", "sub", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* sub $dstbe,$srcbe */
   {
     BPF_INSN_SUBRBE, "subrbe", "sub", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* sub32 $dstbe,$imm32 */
   {
     BPF_INSN_SUB32IBE, "sub32ibe", "sub32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* sub32 $dstbe,$srcbe */
   {
     BPF_INSN_SUB32RBE, "sub32rbe", "sub32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mul $dstbe,$imm32 */
   {
     BPF_INSN_MULIBE, "mulibe", "mul", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mul $dstbe,$srcbe */
   {
     BPF_INSN_MULRBE, "mulrbe", "mul", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mul32 $dstbe,$imm32 */
   {
     BPF_INSN_MUL32IBE, "mul32ibe", "mul32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mul32 $dstbe,$srcbe */
   {
     BPF_INSN_MUL32RBE, "mul32rbe", "mul32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* div $dstbe,$imm32 */
   {
     BPF_INSN_DIVIBE, "divibe", "div", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* div $dstbe,$srcbe */
   {
     BPF_INSN_DIVRBE, "divrbe", "div", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* div32 $dstbe,$imm32 */
   {
     BPF_INSN_DIV32IBE, "div32ibe", "div32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* div32 $dstbe,$srcbe */
   {
     BPF_INSN_DIV32RBE, "div32rbe", "div32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* or $dstbe,$imm32 */
   {
     BPF_INSN_ORIBE, "oribe", "or", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* or $dstbe,$srcbe */
   {
     BPF_INSN_ORRBE, "orrbe", "or", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* or32 $dstbe,$imm32 */
   {
     BPF_INSN_OR32IBE, "or32ibe", "or32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* or32 $dstbe,$srcbe */
   {
     BPF_INSN_OR32RBE, "or32rbe", "or32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* and $dstbe,$imm32 */
   {
     BPF_INSN_ANDIBE, "andibe", "and", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* and $dstbe,$srcbe */
   {
     BPF_INSN_ANDRBE, "andrbe", "and", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* and32 $dstbe,$imm32 */
   {
     BPF_INSN_AND32IBE, "and32ibe", "and32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* and32 $dstbe,$srcbe */
   {
     BPF_INSN_AND32RBE, "and32rbe", "and32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* lsh $dstbe,$imm32 */
   {
     BPF_INSN_LSHIBE, "lshibe", "lsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* lsh $dstbe,$srcbe */
   {
     BPF_INSN_LSHRBE, "lshrbe", "lsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* lsh32 $dstbe,$imm32 */
   {
     BPF_INSN_LSH32IBE, "lsh32ibe", "lsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* lsh32 $dstbe,$srcbe */
   {
     BPF_INSN_LSH32RBE, "lsh32rbe", "lsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* rsh $dstbe,$imm32 */
   {
     BPF_INSN_RSHIBE, "rshibe", "rsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* rsh $dstbe,$srcbe */
   {
     BPF_INSN_RSHRBE, "rshrbe", "rsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* rsh32 $dstbe,$imm32 */
   {
     BPF_INSN_RSH32IBE, "rsh32ibe", "rsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* rsh32 $dstbe,$srcbe */
   {
     BPF_INSN_RSH32RBE, "rsh32rbe", "rsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mod $dstbe,$imm32 */
   {
     BPF_INSN_MODIBE, "modibe", "mod", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mod $dstbe,$srcbe */
   {
     BPF_INSN_MODRBE, "modrbe", "mod", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mod32 $dstbe,$imm32 */
   {
     BPF_INSN_MOD32IBE, "mod32ibe", "mod32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mod32 $dstbe,$srcbe */
   {
     BPF_INSN_MOD32RBE, "mod32rbe", "mod32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* xor $dstbe,$imm32 */
   {
     BPF_INSN_XORIBE, "xoribe", "xor", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* xor $dstbe,$srcbe */
   {
     BPF_INSN_XORRBE, "xorrbe", "xor", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* xor32 $dstbe,$imm32 */
   {
     BPF_INSN_XOR32IBE, "xor32ibe", "xor32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* xor32 $dstbe,$srcbe */
   {
     BPF_INSN_XOR32RBE, "xor32rbe", "xor32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* arsh $dstbe,$imm32 */
   {
     BPF_INSN_ARSHIBE, "arshibe", "arsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* arsh $dstbe,$srcbe */
   {
     BPF_INSN_ARSHRBE, "arshrbe", "arsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* arsh32 $dstbe,$imm32 */
   {
     BPF_INSN_ARSH32IBE, "arsh32ibe", "arsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* arsh32 $dstbe,$srcbe */
   {
     BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* neg $dstbe */
   {
     BPF_INSN_NEGBE, "negbe", "neg", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* neg32 $dstbe */
   {
     BPF_INSN_NEG32BE, "neg32be", "neg32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mov $dstbe,$imm32 */
   {
     BPF_INSN_MOVIBE, "movibe", "mov", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mov $dstbe,$srcbe */
   {
     BPF_INSN_MOVRBE, "movrbe", "mov", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mov32 $dstbe,$imm32 */
   {
     BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* mov32 $dstbe,$srcbe */
   {
     BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* endle $dstle,$endsize */
   {
     BPF_INSN_ENDLELE, "endlele", "endle", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* endbe $dstle,$endsize */
   {
     BPF_INSN_ENDBELE, "endbele", "endbe", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* endle $dstbe,$endsize */
   {
     BPF_INSN_ENDLEBE, "endlebe", "endle", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* endbe $dstbe,$endsize */
   {
     BPF_INSN_ENDBEBE, "endbebe", "endbe", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* lddw $dstle,$imm64 */
   {
     BPF_INSN_LDDWLE, "lddwle", "lddw", 128,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* lddw $dstbe,$imm64 */
   {
     BPF_INSN_LDDWBE, "lddwbe", "lddw", 128,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* ldabsw $imm32 */
   {
     BPF_INSN_LDABSW, "ldabsw", "ldabsw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
   },
 /* ldabsh $imm32 */
   {
     BPF_INSN_LDABSH, "ldabsh", "ldabsh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
   },
 /* ldabsb $imm32 */
   {
     BPF_INSN_LDABSB, "ldabsb", "ldabsb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
   },
 /* ldabsdw $imm32 */
   {
     BPF_INSN_LDABSDW, "ldabsdw", "ldabsdw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
   },
 /* ldindw $srcle,$imm32 */
   {
     BPF_INSN_LDINDWLE, "ldindwle", "ldindw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* ldindh $srcle,$imm32 */
   {
     BPF_INSN_LDINDHLE, "ldindhle", "ldindh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* ldindb $srcle,$imm32 */
   {
     BPF_INSN_LDINDBLE, "ldindble", "ldindb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* ldinddw $srcle,$imm32 */
   {
     BPF_INSN_LDINDDWLE, "ldinddwle", "ldinddw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* ldindw $srcbe,$imm32 */
   {
     BPF_INSN_LDINDWBE, "ldindwbe", "ldindw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* ldindh $srcbe,$imm32 */
   {
     BPF_INSN_LDINDHBE, "ldindhbe", "ldindh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* ldindb $srcbe,$imm32 */
   {
     BPF_INSN_LDINDBBE, "ldindbbe", "ldindb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* ldinddw $srcbe,$imm32 */
   {
     BPF_INSN_LDINDDWBE, "ldinddwbe", "ldinddw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* ldxw $dstle,[$srcle+$offset16] */
   {
     BPF_INSN_LDXWLE, "ldxwle", "ldxw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* ldxh $dstle,[$srcle+$offset16] */
   {
     BPF_INSN_LDXHLE, "ldxhle", "ldxh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* ldxb $dstle,[$srcle+$offset16] */
   {
     BPF_INSN_LDXBLE, "ldxble", "ldxb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* ldxdw $dstle,[$srcle+$offset16] */
   {
     BPF_INSN_LDXDWLE, "ldxdwle", "ldxdw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* stxw [$dstle+$offset16],$srcle */
   {
     BPF_INSN_STXWLE, "stxwle", "stxw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* stxh [$dstle+$offset16],$srcle */
   {
     BPF_INSN_STXHLE, "stxhle", "stxh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* stxb [$dstle+$offset16],$srcle */
   {
     BPF_INSN_STXBLE, "stxble", "stxb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* stxdw [$dstle+$offset16],$srcle */
   {
     BPF_INSN_STXDWLE, "stxdwle", "stxdw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* ldxw $dstbe,[$srcbe+$offset16] */
   {
     BPF_INSN_LDXWBE, "ldxwbe", "ldxw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* ldxh $dstbe,[$srcbe+$offset16] */
   {
     BPF_INSN_LDXHBE, "ldxhbe", "ldxh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* ldxb $dstbe,[$srcbe+$offset16] */
   {
     BPF_INSN_LDXBBE, "ldxbbe", "ldxb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* ldxdw $dstbe,[$srcbe+$offset16] */
   {
     BPF_INSN_LDXDWBE, "ldxdwbe", "ldxdw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* stxw [$dstbe+$offset16],$srcbe */
   {
     BPF_INSN_STXWBE, "stxwbe", "stxw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* stxh [$dstbe+$offset16],$srcbe */
   {
     BPF_INSN_STXHBE, "stxhbe", "stxh", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* stxb [$dstbe+$offset16],$srcbe */
   {
     BPF_INSN_STXBBE, "stxbbe", "stxb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* stxdw [$dstbe+$offset16],$srcbe */
   {
     BPF_INSN_STXDWBE, "stxdwbe", "stxdw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* stb [$dstle+$offset16],$imm32 */
   {
     BPF_INSN_STBLE, "stble", "stb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* sth [$dstle+$offset16],$imm32 */
   {
     BPF_INSN_STHLE, "sthle", "sth", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* stw [$dstle+$offset16],$imm32 */
   {
     BPF_INSN_STWLE, "stwle", "stw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* stdw [$dstle+$offset16],$imm32 */
   {
     BPF_INSN_STDWLE, "stdwle", "stdw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* stb [$dstbe+$offset16],$imm32 */
   {
     BPF_INSN_STBBE, "stbbe", "stb", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* sth [$dstbe+$offset16],$imm32 */
   {
     BPF_INSN_STHBE, "sthbe", "sth", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* stw [$dstbe+$offset16],$imm32 */
   {
     BPF_INSN_STWBE, "stwbe", "stw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* stdw [$dstbe+$offset16],$imm32 */
   {
     BPF_INSN_STDWBE, "stdwbe", "stdw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jeq $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JEQILE, "jeqile", "jeq", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jeq $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JEQRLE, "jeqrle", "jeq", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jeq32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JEQ32ILE, "jeq32ile", "jeq32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jeq32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JEQ32RLE, "jeq32rle", "jeq32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jgt $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JGTILE, "jgtile", "jgt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jgt $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JGTRLE, "jgtrle", "jgt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jgt32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JGT32ILE, "jgt32ile", "jgt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jgt32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JGT32RLE, "jgt32rle", "jgt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jge $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JGEILE, "jgeile", "jge", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jge $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JGERLE, "jgerle", "jge", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jge32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JGE32ILE, "jge32ile", "jge32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jge32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JGE32RLE, "jge32rle", "jge32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jlt $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JLTILE, "jltile", "jlt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jlt $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JLTRLE, "jltrle", "jlt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jlt32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JLT32ILE, "jlt32ile", "jlt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jlt32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JLT32RLE, "jlt32rle", "jlt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jle $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JLEILE, "jleile", "jle", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jle $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JLERLE, "jlerle", "jle", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jle32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JLE32ILE, "jle32ile", "jle32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jle32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JLE32RLE, "jle32rle", "jle32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jset $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JSETILE, "jsetile", "jset", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jset $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JSETRLE, "jsetrle", "jset", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jset32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JSET32ILE, "jset32ile", "jset32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jset32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JSET32RLE, "jset32rle", "jset32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jne $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JNEILE, "jneile", "jne", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jne $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JNERLE, "jnerle", "jne", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jne32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JNE32ILE, "jne32ile", "jne32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jne32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JNE32RLE, "jne32rle", "jne32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsgt $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsgt $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsgt32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JSGT32ILE, "jsgt32ile", "jsgt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsgt32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JSGT32RLE, "jsgt32rle", "jsgt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsge $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JSGEILE, "jsgeile", "jsge", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsge $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JSGERLE, "jsgerle", "jsge", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsge32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JSGE32ILE, "jsge32ile", "jsge32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsge32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JSGE32RLE, "jsge32rle", "jsge32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jslt $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JSLTILE, "jsltile", "jslt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jslt $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jslt32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JSLT32ILE, "jslt32ile", "jslt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jslt32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JSLT32RLE, "jslt32rle", "jslt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsle $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JSLEILE, "jsleile", "jsle", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsle $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JSLERLE, "jslerle", "jsle", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsle32 $dstle,$imm32,$disp16 */
   {
     BPF_INSN_JSLE32ILE, "jsle32ile", "jsle32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jsle32 $dstle,$srcle,$disp16 */
   {
     BPF_INSN_JSLE32RLE, "jsle32rle", "jsle32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* jeq $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JEQIBE, "jeqibe", "jeq", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jeq $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jeq32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JEQ32IBE, "jeq32ibe", "jeq32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jeq32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JEQ32RBE, "jeq32rbe", "jeq32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jgt $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JGTIBE, "jgtibe", "jgt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jgt $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jgt32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JGT32IBE, "jgt32ibe", "jgt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jgt32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JGT32RBE, "jgt32rbe", "jgt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jge $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JGEIBE, "jgeibe", "jge", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jge $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JGERBE, "jgerbe", "jge", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jge32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JGE32IBE, "jge32ibe", "jge32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jge32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JGE32RBE, "jge32rbe", "jge32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jlt $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JLTIBE, "jltibe", "jlt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jlt $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JLTRBE, "jltrbe", "jlt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jlt32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JLT32IBE, "jlt32ibe", "jlt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jlt32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JLT32RBE, "jlt32rbe", "jlt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jle $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JLEIBE, "jleibe", "jle", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jle $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JLERBE, "jlerbe", "jle", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jle32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JLE32IBE, "jle32ibe", "jle32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jle32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JLE32RBE, "jle32rbe", "jle32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jset $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JSETIBE, "jsetibe", "jset", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jset $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JSETRBE, "jsetrbe", "jset", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jset32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JSET32IBE, "jset32ibe", "jset32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jset32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JSET32RBE, "jset32rbe", "jset32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jne $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JNEIBE, "jneibe", "jne", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jne $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JNERBE, "jnerbe", "jne", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jne32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JNE32IBE, "jne32ibe", "jne32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jne32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JNE32RBE, "jne32rbe", "jne32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsgt $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsgt $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsgt32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JSGT32IBE, "jsgt32ibe", "jsgt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsgt32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JSGT32RBE, "jsgt32rbe", "jsgt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsge $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsge $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsge32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JSGE32IBE, "jsge32ibe", "jsge32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsge32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JSGE32RBE, "jsge32rbe", "jsge32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jslt $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jslt $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jslt32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JSLT32IBE, "jslt32ibe", "jslt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jslt32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JSLT32RBE, "jslt32rbe", "jslt32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsle $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsle $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JSLERBE, "jslerbe", "jsle", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsle32 $dstbe,$imm32,$disp16 */
   {
     BPF_INSN_JSLE32IBE, "jsle32ibe", "jsle32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* jsle32 $dstbe,$srcbe,$disp16 */
   {
     BPF_INSN_JSLE32RBE, "jsle32rbe", "jsle32", 64,
-    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* call $disp32 */
   {
     BPF_INSN_CALLLE, "callle", "call", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* call $disp32 */
   {
     BPF_INSN_CALLBE, "callbe", "call", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
+  },
+/* call $dstle */
+  {
+    BPF_INSN_CALLRLE, "callrle", "call", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
+  },
+/* call $dstbe */
+  {
+    BPF_INSN_CALLRBE, "callrbe", "call", 64,
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
   },
 /* ja $disp16 */
   {
     BPF_INSN_JA, "ja", "ja", 64,
-    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+    { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
   },
 /* exit */
   {
     BPF_INSN_EXIT, "exit", "exit", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
   },
 /* xadddw [$dstle+$offset16],$srcle */
   {
     BPF_INSN_XADDDWLE, "xadddwle", "xadddw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* xaddw [$dstle+$offset16],$srcle */
   {
     BPF_INSN_XADDWLE, "xaddwle", "xaddw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
   },
 /* xadddw [$dstbe+$offset16],$srcbe */
   {
     BPF_INSN_XADDDWBE, "xadddwbe", "xadddw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* xaddw [$dstbe+$offset16],$srcbe */
   {
     BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
   },
 /* brkpt */
   {
     BPF_INSN_BRKPT, "brkpt", "brkpt", 64,
-    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+    { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
   },
 };
 

diff --git a/opcodes/bpf-desc.h b/opcodes/bpf-desc.h
index 38cf8c8e73b57029bcdc9f1c40b7cf953997799f..dd24996492b42442ca00195e68d122c43bad3232 100644 (file)
--- a/opcodes/bpf-desc.h
+++ b/opcodes/bpf-desc.h
@@ -99,12 +99,13 @@ typedef enum insn_op_size {
 
 /* Enum declaration for machine type selection.  */
 typedef enum mach_attr {
-  MACH_BASE, MACH_BPF, MACH_MAX
+  MACH_BASE, MACH_BPF, MACH_XBPF, MACH_MAX
 } MACH_ATTR;
 
 /* Enum declaration for instruction set selection.  */
 typedef enum isa_attr {
-  ISA_EBPFLE, ISA_EBPFBE, ISA_MAX
+  ISA_EBPFLE, ISA_EBPFBE, ISA_XBPFLE, ISA_XBPFBE
+ , ISA_MAX
 } ISA_ATTR;
 
 /* Number of architecture variants.  */

diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
index 00f3b25f768f79502fedbab4b33809487254ed04..72d5cd2e0c7d4020de7f2c21ba6adf45eaec8506 100644 (file)
--- a/opcodes/bpf-opc.c
+++ b/opcodes/bpf-opc.c
@@ -1552,6 +1552,18 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
     { { MNEM, ' ', OP (DISP32), 0 } },
     & ifmt_callle, { 0x85 }
   },
+/* call $dstle */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTLE), 0 } },
+    & ifmt_negle, { 0x8d }
+  },
+/* call $dstbe */
+  {
+    { 0, 0, 0, 0 },
+    { { MNEM, ' ', OP (DSTBE), 0 } },
+    & ifmt_negbe, { 0x8d }
+  },
 /* ja $disp16 */
   {
     { 0, 0, 0, 0 },

diff --git a/opcodes/bpf-opc.h b/opcodes/bpf-opc.h
index ec0c2d328e87e317962ef15c34bc3e03193c360c..5d5150c68564f319747b86c70439368c2dd5597a 100644 (file)
--- a/opcodes/bpf-opc.h
+++ b/opcodes/bpf-opc.h
@@ -106,8 +106,9 @@ typedef enum cgen_insn_type {
  , BPF_INSN_JSGERBE, BPF_INSN_JSGE32IBE, BPF_INSN_JSGE32RBE, BPF_INSN_JSLTIBE
  , BPF_INSN_JSLTRBE, BPF_INSN_JSLT32IBE, BPF_INSN_JSLT32RBE, BPF_INSN_JSLEIBE
  , BPF_INSN_JSLERBE, BPF_INSN_JSLE32IBE, BPF_INSN_JSLE32RBE, BPF_INSN_CALLLE
- , BPF_INSN_CALLBE, BPF_INSN_JA, BPF_INSN_EXIT, BPF_INSN_XADDDWLE
- , BPF_INSN_XADDWLE, BPF_INSN_XADDDWBE, BPF_INSN_XADDWBE, BPF_INSN_BRKPT
+ , BPF_INSN_CALLBE, BPF_INSN_CALLRLE, BPF_INSN_CALLRBE, BPF_INSN_JA
+ , BPF_INSN_EXIT, BPF_INSN_XADDDWLE, BPF_INSN_XADDWLE, BPF_INSN_XADDDWBE
+ , BPF_INSN_XADDWBE, BPF_INSN_BRKPT
 } CGEN_INSN_TYPE;
 
 /* Index of `invalid' insn place holder.  */

diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c
index 299c23db137e1c73cbf09ad456dcac4f21c29fd7..fd566a9979aa129ac1f084ef8194049f51380078 100644 (file)
--- a/opcodes/disassemble.c
+++ b/opcodes/disassemble.c
@@ -663,11 +663,19 @@ disassemble_init_for_target (struct disassemble_info * info)
       info->endian_code = BFD_ENDIAN_LITTLE;
       if (!info->private_data)
        {
-         info->private_data = cgen_bitset_create (ISA_EBPFMAX);
+         info->private_data = cgen_bitset_create (ISA_MAX);
          if (info->endian == BFD_ENDIAN_BIG)
-           cgen_bitset_set (info->private_data, ISA_EBPFBE);
+           {
+             cgen_bitset_set (info->private_data, ISA_EBPFBE);
+             if (info->mach == bfd_mach_xbpf)
+               cgen_bitset_set (info->private_data, ISA_XBPFBE);
+           }
          else
-           cgen_bitset_set (info->private_data, ISA_EBPFLE);
+           {
+             cgen_bitset_set (info->private_data, ISA_EBPFLE);
+             if (info->mach == bfd_mach_xbpf)
+               cgen_bitset_set (info->private_data, ISA_XBPFLE);
+           }
        }
       break;
 #endif