// check that the physical address is ok (catch bad physical addresses)
if (req->paddr & ~PAddrImplMask)
- return new MachineCheckFault;
+ return genMachineCheckFault();
checkCacheability(req);
fault(req, write ? MM_STAT_WR_MASK : 0);
DPRINTF(TLB, "Alignment Fault on %#x, size = %d", req->vaddr,
req->size);
- return new AlignmentFault;
+ return genAlignmentFault();
}
if (pc & 0x1) {
// check that the physical address is ok (catch bad physical addresses)
if (req->paddr & ~PAddrImplMask)
- return new MachineCheckFault;
+ return genMachineCheckFault();
checkCacheability(req);
FaultVect AlphaFault::_vect = 0x0000;
FaultStat AlphaFault::_stat;
+FaultVect AlphaMachineCheckFault::_vect = 0x0401;
+
+FaultVect AlphaAlignmentFault::_vect = 0x0301;
+
FaultName ResetFault::_name = "reset";
FaultVect ResetFault::_vect = 0x0001;
FaultStat ResetFault::_stat;
#include "sim/faults.hh"
-// The reasoning behind the name and vect functions is in sim/faults.hh
+// The design of the "name" and "vect" functions is in sim/faults.hh
typedef const Addr FaultVect;
virtual FaultStat & stat() {return _stat;}
};
+class AlphaMachineCheckFault : public MachineCheckFault
+{
+ private:
+ static FaultVect _vect;
+ public:
+ FaultVect vect() {return _vect;}
+};
+
+class AlphaAlignmentFault : public AlignmentFault
+{
+ private:
+ static FaultVect _vect;
+ public:
+ FaultVect vect() {return _vect;}
+};
+
+static inline Fault genMachineCheckFault()
+{
+ return new AlphaMachineCheckFault;
+}
+
+static inline Fault genAlignmentFault()
+{
+ return new AlphaAlignmentFault;
+}
+
class ResetFault : public AlphaFault
{
private:
FaultStat & stat() {return _stat;}
};
-//Fault * ListOfFaults[];
-//int NumFaults;
-
#endif // __FAULTS_HH__
#include "cpu/o3/alpha_cpu.hh"
using namespace std;
+using namespace TheISA;
#define NOHASH
#ifndef NOHASH
break;
default:
- fault = MachineCheckFault;
+ fault = genMachineCheckFault();
break;
}
}
break;
default:
- return new MachineCheckFault;
+ return genMachineCheckFault();
}
return NoFault;
val = *(uint64_t *)data;
break;
default:
- return new MachineCheckFault;
+ return genMachineCheckFault();
}
Addr daddr = req->paddr - (addr & EV5::PAddrImplMask);
inline Fault
PciDev::readBar(MemReqPtr &req, uint8_t *data)
{
+ using namespace TheISA;
if (isBAR(req->paddr, 0))
return readBar0(req, req->paddr - BARAddrs[0], data);
if (isBAR(req->paddr, 1))
return readBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return readBar5(req, req->paddr - BARAddrs[5], data);
- return new MachineCheckFault;
+ return genMachineCheckFault();
}
inline Fault
PciDev::writeBar(MemReqPtr &req, const uint8_t *data)
{
+ using namespace TheISA;
if (isBAR(req->paddr, 0))
return writeBar0(req, req->paddr - BARAddrs[0], data);
if (isBAR(req->paddr, 1))
return writeBar4(req, req->paddr - BARAddrs[4], data);
if (isBAR(req->paddr, 5))
return writeBar5(req, req->paddr - BARAddrs[5], data);
- return new MachineCheckFault;
+ return genMachineCheckFault();
}
#endif // __DEV_PCIDEV_HH__
assert(config.command & PCI_CMD_MSE);
Fault fault = readBar(req, data);
- if (fault->isA<MachineCheckFault>()) {
+ if (fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return new MachineCheckFault;
+ return genMachineCheckFault();
}
return fault;
assert(config.command & PCI_CMD_MSE);
Fault fault = writeBar(req, data);
- if (fault->isA<MachineCheckFault>()) {
+ if (fault->isMachineCheckFault()) {
panic("address does not map to a BAR pa=%#x va=%#x size=%d",
req->paddr, req->vaddr, req->size);
- return new MachineCheckFault;
+ return genMachineCheckFault();
}
return fault;