if buildEnv['TARGET_ISA'] == "x86":
cpu_seq.pio_slave_port = piobus.master
+ ruby.number_of_virtual_networks = ruby.network.number_of_virtual_networks
ruby._cpu_ports = cpu_sequencers
ruby.num_of_sequencers = len(cpu_sequencers)
using m5::stl_helpers::operator<<;
Profiler::Profiler(const RubySystemParams *p, RubySystem *rs)
- : m_ruby_system(rs)
+ : m_ruby_system(rs), m_hot_lines(p->hot_lines),
+ m_all_instructions(p->all_instructions),
+ m_num_vnets(p->number_of_virtual_networks)
{
- m_hot_lines = p->hot_lines;
- m_all_instructions = p->all_instructions;
-
m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers, this);
m_address_profiler_ptr->setHotLines(m_hot_lines);
m_address_profiler_ptr->setAllInstructions(m_all_instructions);
.desc("delay histogram for all message")
.flags(Stats::nozero | Stats::pdf | Stats::oneline);
- uint32_t numVNets = Network::getNumberOfVirtualNetworks();
- for (int i = 0; i < numVNets; i++) {
+ for (int i = 0; i < m_num_vnets; i++) {
delayVCHistogram.push_back(new Stats::Histogram());
delayVCHistogram[i]
->init(10)
m_inst_profiler_ptr->collateStats();
}
- uint32_t numVNets = Network::getNumberOfVirtualNetworks();
for (uint32_t i = 0; i < MachineType_NUM; i++) {
for (map<uint32_t, AbstractController*>::iterator it =
m_ruby_system->m_abstract_controls[i].begin();
AbstractController *ctr = (*it).second;
delayHistogram.add(ctr->getDelayHist());
- for (uint32_t i = 0; i < numVNets; i++) {
+ for (uint32_t i = 0; i < m_num_vnets; i++) {
delayVCHistogram[i]->add(ctr->getDelayVCHist(i));
}
}
void addAddressTraceSample(const RubyRequest& msg, NodeID id);
// added by SS
- bool getHotLines() { return m_hot_lines; }
- bool getAllInstructions() { return m_all_instructions; }
+ bool getHotLines() const { return m_hot_lines; }
+ bool getAllInstructions() const { return m_all_instructions; }
private:
// Private copy constructor and assignment operator
Stats::Scalar m_IncompleteTimes[MachineType_NUM];
//added by SS
- bool m_hot_lines;
- bool m_all_instructions;
+ const bool m_hot_lines;
+ const bool m_all_instructions;
+ const uint32_t m_num_vnets;
};
#endif // __MEM_RUBY_PROFILER_PROFILER_HH__
memory_size_bits = Param.UInt32(64,
"number of bits that a memory address requires");
- # Profiler related configuration variables
- hot_lines = Param.Bool(False, "")
- all_instructions = Param.Bool(False, "")
- num_of_sequencers = Param.Int("")
phys_mem = Param.SimpleMemory(NULL, "")
access_backing_store = Param.Bool(False, "Use phys_mem as the functional \
store and only use ruby for timing.")
+
+ # Profiler related configuration variables
+ hot_lines = Param.Bool(False, "")
+ all_instructions = Param.Bool(False, "")
+ num_of_sequencers = Param.Int("")
+ number_of_virtual_networks = Param.Unsigned("")