WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is not active!
-Command: 1, Timestamp: 3080, Bank: 4
+Command: 1, Timestamp: 3178, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7386, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: Returning zero for read from miscreg pmcr
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[2]
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 29 2015 17:36:13
-gem5 started Jul 29 2015 17:36:59
+gem5 compiled Jul 31 2015 14:34:49
+gem5 started Jul 31 2015 14:34:58
gem5 executing on e104799-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5_3/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
---------- Begin Simulation Statistics ----------
-sim_seconds 2.823452 # Number of seconds simulated
-sim_ticks 2823451688000 # Number of ticks simulated
-final_tick 2823451688000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.823474 # Number of seconds simulated
+sim_ticks 2823473696000 # Number of ticks simulated
+final_tick 2823473696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 255579 # Simulator instruction rate (inst/s)
-host_op_rate 310019 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 5872606908 # Simulator tick rate (ticks/s)
-host_mem_usage 578280 # Number of bytes of host memory used
-host_seconds 480.78 # Real time elapsed on the host
-sim_insts 122878254 # Number of instructions simulated
-sim_ops 149051775 # Number of ops (including micro ops) simulated
+host_inst_rate 536168 # Simulator instruction rate (inst/s)
+host_op_rate 650376 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 12315198448 # Simulator tick rate (ticks/s)
+host_mem_usage 577764 # Number of bytes of host memory used
+host_seconds 229.27 # Real time elapsed on the host
+sim_insts 122925898 # Number of instructions simulated
+sim_ops 149109939 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 538148 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 3049124 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 121344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 892800 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 2112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 537380 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 3052900 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 891264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 373376 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 2020416 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker 4416 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 355840 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 3621312 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 373952 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 2012736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker 4224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 356480 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 3623360 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10980232 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 538148 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 121344 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 373376 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 355840 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1388708 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8266880 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10976712 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 537380 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 373952 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 356480 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1388836 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8247936 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8284404 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
+system.physmem.bytes_written::total 8265460 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 16862 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 48162 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1896 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 13950 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 33 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 16850 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 48221 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 13926 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 5834 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 31569 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker 69 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 5560 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 56583 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 5843 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 31449 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker 66 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 5570 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 56615 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 180539 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 129170 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 180484 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 128874 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 133551 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 133255 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 190599 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1079928 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 42977 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 316209 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 748 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 190326 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1081257 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 42864 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 315662 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 703 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 132241 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 715584 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker 1564 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 126030 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 1282583 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 132444 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 712858 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker 1496 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 126256 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 1283299 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3888939 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 190599 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 42977 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 132241 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 126030 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 491848 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2927934 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3887662 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 190326 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 42864 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 132444 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 126256 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 491889 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2921202 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6207 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2934141 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2927934 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::total 2927408 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2921202 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 190599 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1086134 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 42977 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 316209 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 748 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 190326 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1087463 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 42864 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 315662 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 703 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 132241 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 715584 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker 1564 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 126030 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 1282583 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 132444 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 712858 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker 1496 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 126256 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 1283299 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6823080 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 115495 # Number of read requests accepted
-system.physmem.writeReqs 70322 # Number of write requests accepted
-system.physmem.readBursts 115495 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 70322 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 7384064 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4499904 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 7391680 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 4500608 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::total 6815070 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 115392 # Number of read requests accepted
+system.physmem.writeReqs 70006 # Number of write requests accepted
+system.physmem.readBursts 115392 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 70006 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 7377600 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue
+system.physmem.bytesWritten 4479552 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 7385088 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 4480384 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 16728 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 7953 # Per bank write bursts
-system.physmem.perBankRdBursts::1 7174 # Per bank write bursts
-system.physmem.perBankRdBursts::2 7640 # Per bank write bursts
-system.physmem.perBankRdBursts::3 7504 # Per bank write bursts
-system.physmem.perBankRdBursts::4 7829 # Per bank write bursts
-system.physmem.perBankRdBursts::5 7364 # Per bank write bursts
-system.physmem.perBankRdBursts::6 7486 # Per bank write bursts
-system.physmem.perBankRdBursts::7 7817 # Per bank write bursts
-system.physmem.perBankRdBursts::8 7059 # Per bank write bursts
-system.physmem.perBankRdBursts::9 7674 # Per bank write bursts
-system.physmem.perBankRdBursts::10 7129 # Per bank write bursts
-system.physmem.perBankRdBursts::11 6171 # Per bank write bursts
-system.physmem.perBankRdBursts::12 6502 # Per bank write bursts
-system.physmem.perBankRdBursts::13 7092 # Per bank write bursts
-system.physmem.perBankRdBursts::14 6785 # Per bank write bursts
-system.physmem.perBankRdBursts::15 6197 # Per bank write bursts
-system.physmem.perBankWrBursts::0 4825 # Per bank write bursts
-system.physmem.perBankWrBursts::1 4280 # Per bank write bursts
-system.physmem.perBankWrBursts::2 4678 # Per bank write bursts
-system.physmem.perBankWrBursts::3 4464 # Per bank write bursts
-system.physmem.perBankWrBursts::4 4644 # Per bank write bursts
-system.physmem.perBankWrBursts::5 4512 # Per bank write bursts
-system.physmem.perBankWrBursts::6 4517 # Per bank write bursts
-system.physmem.perBankWrBursts::7 4571 # Per bank write bursts
-system.physmem.perBankWrBursts::8 4335 # Per bank write bursts
-system.physmem.perBankWrBursts::9 5017 # Per bank write bursts
-system.physmem.perBankWrBursts::10 4515 # Per bank write bursts
-system.physmem.perBankWrBursts::11 3667 # Per bank write bursts
-system.physmem.perBankWrBursts::12 3925 # Per bank write bursts
-system.physmem.perBankWrBursts::13 4539 # Per bank write bursts
-system.physmem.perBankWrBursts::14 4104 # Per bank write bursts
-system.physmem.perBankWrBursts::15 3718 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 16729 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 7736 # Per bank write bursts
+system.physmem.perBankRdBursts::1 7063 # Per bank write bursts
+system.physmem.perBankRdBursts::2 7688 # Per bank write bursts
+system.physmem.perBankRdBursts::3 7632 # Per bank write bursts
+system.physmem.perBankRdBursts::4 7697 # Per bank write bursts
+system.physmem.perBankRdBursts::5 7461 # Per bank write bursts
+system.physmem.perBankRdBursts::6 7652 # Per bank write bursts
+system.physmem.perBankRdBursts::7 7853 # Per bank write bursts
+system.physmem.perBankRdBursts::8 7016 # Per bank write bursts
+system.physmem.perBankRdBursts::9 7651 # Per bank write bursts
+system.physmem.perBankRdBursts::10 6943 # Per bank write bursts
+system.physmem.perBankRdBursts::11 6411 # Per bank write bursts
+system.physmem.perBankRdBursts::12 6488 # Per bank write bursts
+system.physmem.perBankRdBursts::13 7344 # Per bank write bursts
+system.physmem.perBankRdBursts::14 6713 # Per bank write bursts
+system.physmem.perBankRdBursts::15 5927 # Per bank write bursts
+system.physmem.perBankWrBursts::0 4604 # Per bank write bursts
+system.physmem.perBankWrBursts::1 4172 # Per bank write bursts
+system.physmem.perBankWrBursts::2 4724 # Per bank write bursts
+system.physmem.perBankWrBursts::3 4597 # Per bank write bursts
+system.physmem.perBankWrBursts::4 4526 # Per bank write bursts
+system.physmem.perBankWrBursts::5 4564 # Per bank write bursts
+system.physmem.perBankWrBursts::6 4573 # Per bank write bursts
+system.physmem.perBankWrBursts::7 4592 # Per bank write bursts
+system.physmem.perBankWrBursts::8 4263 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4993 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4344 # Per bank write bursts
+system.physmem.perBankWrBursts::11 3939 # Per bank write bursts
+system.physmem.perBankWrBursts::12 3901 # Per bank write bursts
+system.physmem.perBankWrBursts::13 4724 # Per bank write bursts
+system.physmem.perBankWrBursts::14 4019 # Per bank write bursts
+system.physmem.perBankWrBursts::15 3458 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
-system.physmem.totGap 2821880880500 # Total gap between requests
+system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
+system.physmem.totGap 2821902889500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 115495 # Read request sizes (log2)
+system.physmem.readPktSize::6 115392 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 70322 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 87424 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 24888 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2511 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 550 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 70006 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 87082 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 25035 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2573 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 583 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 66 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 64 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 64 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 64 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 62 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 61 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 61 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 63 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 63 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 62 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 62 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 60 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 59 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 61 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 61 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 60 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 59 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 59 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1175 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1398 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 3306 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 3844 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3887 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 3903 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 3887 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4346 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 4451 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 4886 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 4583 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 4539 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4149 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 4345 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 4484 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 3901 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 3868 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 3722 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 63 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 44 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 49 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 28 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 28 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 25 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 20 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 25 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 13 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 35 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 20 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 25 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 28 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 24 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 12 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 32 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 16 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 11 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 19 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 12 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 39789 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 298.674709 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 174.286017 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 326.421202 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 15628 39.28% 39.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 9455 23.76% 63.04% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 3888 9.77% 72.81% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 2213 5.56% 78.37% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1604 4.03% 82.40% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 939 2.36% 84.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 730 1.83% 86.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 629 1.58% 88.18% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4703 11.82% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 39789 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 3745 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 30.804539 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 621.520984 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 3744 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.wrQLenPdf::15 1142 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1373 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 3178 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 3727 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 3775 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 3833 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 3936 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4298 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 4359 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 4769 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 4543 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 4412 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4145 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4333 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 4426 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 3858 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 3891 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 3738 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 101 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 82 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 86 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 71 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 60 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 49 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 75 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 49 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 50 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 38 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 40 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 47 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 58 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 47 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 39680 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 298.819355 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 174.296873 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 326.728623 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 15567 39.23% 39.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 9452 23.82% 63.05% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 3895 9.82% 72.87% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 2106 5.31% 78.18% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1684 4.24% 82.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 926 2.33% 84.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 731 1.84% 86.60% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 606 1.53% 88.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4713 11.88% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 39680 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 3702 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 31.134792 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 625.115005 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 3701 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 3745 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 3745 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 18.774633 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.746790 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 9.292289 # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 3702 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 3702 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 18.906807 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.729572 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 10.893119 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 6 0.16% 0.16% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 3 0.08% 0.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11 1 0.03% 0.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 5 0.13% 0.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 3351 89.48% 89.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 51 1.36% 91.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 76 2.03% 93.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 45 1.20% 94.47% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 29 0.77% 95.25% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 68 1.82% 97.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 12 0.32% 97.38% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 10 0.27% 97.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 5 0.13% 97.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 4 0.11% 97.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 3 0.08% 97.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 1 0.03% 98.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 57 1.52% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 4 0.11% 99.63% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 2 0.05% 99.68% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 5 0.13% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 1 0.03% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 1 0.03% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 1 0.03% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 3 0.08% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::192-195 1 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 3745 # Writes before turning the bus around for reads
-system.physmem.totQLat 1373444750 # Total ticks spent queuing
-system.physmem.totMemAccLat 3536744750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 576880000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 11904.08 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::4-7 2 0.05% 0.22% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 2 0.05% 0.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 7 0.19% 0.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 3319 89.65% 90.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 56 1.51% 91.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 61 1.65% 93.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 52 1.40% 94.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 33 0.89% 95.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 54 1.46% 97.03% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 14 0.38% 97.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 4 0.11% 97.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 10 0.27% 97.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 2 0.05% 97.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 1 0.03% 97.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 1 0.03% 97.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 54 1.46% 99.35% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 3 0.08% 99.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 3 0.08% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.03% 99.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 2 0.05% 99.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.03% 99.62% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.03% 99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.03% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 5 0.14% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.03% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.03% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.03% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 4 0.11% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 3702 # Writes before turning the bus around for reads
+system.physmem.totQLat 1386684000 # Total ticks spent queuing
+system.physmem.totMemAccLat 3548090250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 576375000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12029.36 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30654.08 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 2.62 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 30779.36 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 2.61 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.62 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 28.79 # Average write queue length when enqueuing
-system.physmem.readRowHits 95547 # Number of row buffer hits during reads
-system.physmem.writeRowHits 50351 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.81 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 71.60 # Row buffer hit rate for writes
-system.physmem.avgGap 15186343.99 # Average gap between requests
-system.physmem.pageHitRate 78.57 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 160211520 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 87256125 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 473982600 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 236461680 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 179691539040 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 72230311935 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 1621102009500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 1873981772400 # Total energy per rank (pJ)
-system.physmem_0.averagePower 667.506366 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 2640519481750 # Time in different power states
-system.physmem_0.memoryStateTime::REF 91866840000 # Time in different power states
+system.physmem.avgWrQLen 19.44 # Average write queue length when enqueuing
+system.physmem.readRowHits 95329 # Number of row buffer hits during reads
+system.physmem.writeRowHits 50259 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes
+system.physmem.avgGap 15220783.88 # Average gap between requests
+system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined
+system.physmem_0.actEnergy 160733160 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 87536625 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 474099600 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 235560960 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 179692556160 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 72207385965 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 1621122462750 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 1873980335220 # Total energy per rank (pJ)
+system.physmem_0.averagePower 667.505718 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 2640566607500 # Time in different power states
+system.physmem_0.memoryStateTime::REF 91867360000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 18811132750 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 18778047250 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 140593320 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 76547625 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 425950200 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 219153600 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 179691539040 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 71075732760 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 1618530580500 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 1870160097045 # Total energy per rank (pJ)
-system.physmem_1.averagePower 667.565551 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 2642231800750 # Time in different power states
-system.physmem_1.memoryStateTime::REF 91866840000 # Time in different power states
+system.physmem_1.actEnergy 139247640 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 75805125 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 425045400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 217993680 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 179692556160 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 71111774430 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 1616695526250 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 1868357948685 # Total energy per rank (pJ)
+system.physmem_1.averagePower 667.638582 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 2642185763250 # Time in different power states
+system.physmem_1.memoryStateTime::REF 91867360000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 17099623500 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 17159721000 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 5044 # Table walker walks requested
-system.cpu0.dtb.walker.walksShort 5044 # Table walker walks initiated with short descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 5044 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 5044 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 5044 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 56727881876 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 1.269097 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -15265283124 -26.91% -26.91% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 71993165000 126.91% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 56727881876 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 2868 68.19% 68.19% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::1M 1338 31.81% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 4206 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5044 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 5013 # Table walker walks requested
+system.cpu0.dtb.walker.walksShort 5013 # Table walker walks initiated with short descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 5013 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 5013 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 5013 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 56727642376 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.269102 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -15265500874 -26.91% -26.91% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 71993143250 126.91% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 56727642376 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 2853 68.40% 68.40% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::1M 1318 31.60% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 4171 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5013 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5044 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4206 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5013 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4171 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4206 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 9250 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4171 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 9184 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 12055693 # DTB read hits
-system.cpu0.dtb.read_misses 4324 # DTB read misses
-system.cpu0.dtb.write_hits 9053768 # DTB write hits
-system.cpu0.dtb.write_misses 720 # DTB write misses
+system.cpu0.dtb.read_hits 12054005 # DTB read hits
+system.cpu0.dtb.read_misses 4307 # DTB read misses
+system.cpu0.dtb.write_hits 9056572 # DTB write hits
+system.cpu0.dtb.write_misses 706 # DTB write misses
system.cpu0.dtb.flush_tlb 172 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva 358 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2916 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 2897 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 817 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 829 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 183 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 12060017 # DTB read accesses
-system.cpu0.dtb.write_accesses 9054488 # DTB write accesses
+system.cpu0.dtb.perms_faults 179 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 12058312 # DTB read accesses
+system.cpu0.dtb.write_accesses 9057278 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 21109461 # DTB hits
-system.cpu0.dtb.misses 5044 # DTB misses
-system.cpu0.dtb.accesses 21114505 # DTB accesses
+system.cpu0.dtb.hits 21110577 # DTB hits
+system.cpu0.dtb.misses 5013 # DTB misses
+system.cpu0.dtb.accesses 21115590 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 2455 # Table walker walks requested
-system.cpu0.itb.walker.walksShort 2455 # Table walker walks initiated with short descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 2455 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 2455 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 2455 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 56727881876 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 1.269099 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -15265389124 -26.91% -26.91% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 71993271000 126.91% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 56727881876 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 1346 75.11% 75.11% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::1M 446 24.89% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 1792 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 2456 # Table walker walks requested
+system.cpu0.itb.walker.walksShort 2456 # Table walker walks initiated with short descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 2456 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 2456 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 2456 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 56727642376 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 1.269104 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -15265627374 -26.91% -26.91% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 71993269750 126.91% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 56727642376 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 1347 75.13% 75.13% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::1M 446 24.87% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 1793 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2455 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2455 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2456 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2456 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1792 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1792 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 4247 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 56652194 # ITB inst hits
-system.cpu0.itb.inst_misses 2455 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1793 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1793 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 4249 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 56651895 # ITB inst hits
+system.cpu0.itb.inst_misses 2456 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 172 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 369 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva 358 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1791 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1793 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 56654649 # ITB inst accesses
-system.cpu0.itb.hits 56652194 # DTB hits
-system.cpu0.itb.misses 2455 # DTB misses
-system.cpu0.itb.accesses 56654649 # DTB accesses
-system.cpu0.numCycles 68394939 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 56654351 # ITB inst accesses
+system.cpu0.itb.hits 56651895 # DTB hits
+system.cpu0.itb.misses 2456 # DTB misses
+system.cpu0.itb.accesses 56654351 # DTB accesses
+system.cpu0.numCycles 68396174 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 55195414 # Number of instructions committed
-system.cpu0.committedOps 66855615 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 58673965 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4653 # Number of float alu accesses
-system.cpu0.num_func_calls 5764786 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 7314754 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 58673965 # number of integer instructions
-system.cpu0.num_fp_insts 4653 # number of float instructions
-system.cpu0.num_int_register_reads 108155823 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 40952580 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3548 # number of times the floating registers were read
+system.cpu0.committedInsts 55195315 # Number of instructions committed
+system.cpu0.committedOps 66856964 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 58675450 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 4621 # Number of float alu accesses
+system.cpu0.num_func_calls 5764530 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 7314757 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 58675450 # number of integer instructions
+system.cpu0.num_fp_insts 4621 # number of float instructions
+system.cpu0.num_int_register_reads 108161484 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 40950551 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 3516 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1106 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 203459813 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 24562816 # number of times the CC registers were written
-system.cpu0.num_mem_refs 21693456 # number of memory refs
-system.cpu0.num_load_insts 12204686 # Number of load instructions
-system.cpu0.num_store_insts 9488770 # Number of store instructions
-system.cpu0.num_idle_cycles 64604124.391568 # Number of idle cycles
-system.cpu0.num_busy_cycles 3790814.608432 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.055425 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.944575 # Percentage of idle cycles
-system.cpu0.Branches 13394268 # Number of branches fetched
+system.cpu0.num_cc_register_reads 203464939 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 24566154 # number of times the CC registers were written
+system.cpu0.num_mem_refs 21694661 # number of memory refs
+system.cpu0.num_load_insts 12202966 # Number of load instructions
+system.cpu0.num_store_insts 9491695 # Number of store instructions
+system.cpu0.num_idle_cycles 64604771.704346 # Number of idle cycles
+system.cpu0.num_busy_cycles 3791402.295654 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.055433 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.944567 # Percentage of idle cycles
+system.cpu0.Branches 13394190 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2179 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 46192687 67.99% 67.99% # Class of executed instruction
-system.cpu0.op_class::IntMult 50556 0.07% 68.07% # Class of executed instruction
-system.cpu0.op_class::IntDiv 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 3909 0.01% 68.07% # Class of executed instruction
+system.cpu0.op_class::IntAlu 46192822 67.99% 67.99% # Class of executed instruction
+system.cpu0.op_class::IntMult 50582 0.07% 68.06% # Class of executed instruction
+system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 3903 0.01% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.07% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.07% # Class of executed instruction
-system.cpu0.op_class::MemRead 12204686 17.96% 86.03% # Class of executed instruction
-system.cpu0.op_class::MemWrite 9488770 13.97% 100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead 12202966 17.96% 86.03% # Class of executed instruction
+system.cpu0.op_class::MemWrite 9491695 13.97% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 67942787 # Class of executed instruction
+system.cpu0.op_class::total 67944147 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3087 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 832854 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.996678 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 45941048 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 833366 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 55.127097 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.replacements 833490 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.996671 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 45958483 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 834002 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 55.105963 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.291122 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.712491 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.320971 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data 14.672094 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.938069 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.022876 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data 0.010393 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data 0.028656 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.294893 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.112781 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.133577 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data 11.455419 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.943935 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.021705 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011980 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu3.data 0.022374 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 88 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 193272549 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 193272549 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 11424997 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 3591571 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 4056566 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data 6785067 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 25858201 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 8716576 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 2652345 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 3172859 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data 4239682 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 18781462 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177203 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 53725 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data 68062 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data 87970 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 386960 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 215942 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74003 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70208 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 90799 # number of LoadLockedReq hits
+system.cpu0.dcache.tags.tag_accesses 193340724 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 193340724 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 11422910 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 3593204 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data 4066922 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu3.data 6785601 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 25868637 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 8719261 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 2659250 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data 3172966 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu3.data 4237084 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 18788561 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177218 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data 53891 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data 68030 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu3.data 87717 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 386856 # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 215939 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74279 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70102 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 90632 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 450952 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216982 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 75596 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data 72811 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data 95206 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 460595 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 20141573 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 6243916 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 7229425 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data 11024749 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 44639663 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 20318776 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 6297641 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 7297487 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data 11112719 # number of overall hits
-system.cpu0.dcache.overall_hits::total 45026623 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 170763 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 51416 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 83405 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data 222894 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 528478 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 111802 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 33494 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 105638 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data 1237063 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1487997 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54554 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data 16796 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data 18757 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data 47065 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 137172 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3717 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2279 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3522 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8436 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 17954 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 1 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu3.data 17 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 18 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 282565 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 84910 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 189043 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data 1459957 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2016475 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 337119 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 101706 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data 207800 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data 1507022 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2153647 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 824607500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1194074500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3363398500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 5382080500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1236116500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5104811996 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 62105608982 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 68446537478 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 27718500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 44847000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 123322000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 195887500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 465000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 465000 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 2060724000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 6298886496 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data 65469007482 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 73828617978 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 2060724000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 6298886496 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data 65469007482 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 73828617978 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 11595760 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 3642987 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 4139971 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data 7007961 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 26386679 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 8828378 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 2685839 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data 3278497 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu3.data 5476745 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 20269459 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 231757 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 70521 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86819 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 135035 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 524132 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 219659 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 76282 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 73730 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 99235 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 468906 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216983 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 75596 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 72811 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 95223 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 460613 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 20424138 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 6328826 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 7418468 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data 12484706 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 46656138 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 20655895 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 6399347 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 7505287 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data 12619741 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 47180270 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014726 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014114 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.020146 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031806 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.020028 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012664 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.012471 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.032221 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.225876 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.073411 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235393 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.238170 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.216047 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.348539 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.261713 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016922 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.029876 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.047769 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.085010 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038289 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000005 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000179 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000039 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013835 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013416 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.025483 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data 0.116940 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.043220 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016321 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015893 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.027687 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119418 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.045647 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16037.955111 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14316.581740 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15089.677156 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10184.114571 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36905.609960 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48323.633503 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 50204.079325 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 45999.109862 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12162.571303 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12733.390119 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14618.539592 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10910.521332 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 27352.941176 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 25833.333333 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24269.508892 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33319.861069 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44843.106668 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 36612.711776 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20261.577488 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30312.254552 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43442.635530 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 34280.742377 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 334085 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 49646 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 14251 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 808 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.442916 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 61.443069 # average number of cycles each access was blocked
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216972 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 75904 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data 72697 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu3.data 95027 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 460600 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 20142171 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 6252454 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data 7239888 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu3.data 11022685 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 44657198 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 20319389 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 6306345 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data 7307918 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu3.data 11110402 # number of overall hits
+system.cpu0.dcache.overall_hits::total 45044054 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 171223 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 51523 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data 83889 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu3.data 223011 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 529646 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 111924 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 33653 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data 105580 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu3.data 1235287 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1486444 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54469 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data 16872 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data 18830 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu3.data 46816 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 136987 # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3702 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2319 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3513 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8435 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 17969 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu3.data 21 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 283147 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 85176 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data 189469 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu3.data 1458298 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 2016090 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 337616 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 102048 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data 208299 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu3.data 1505114 # number of overall misses
+system.cpu0.dcache.overall_misses::total 2153077 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 825879500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1199033500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3362095000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 5387008000 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1242542000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5087689996 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 62077343955 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 68407575951 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28207500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 45088000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 123538000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 196833500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 598500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 598500 # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu1.data 2068421500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 6286723496 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data 65439438955 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 73794583951 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 2068421500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 6286723496 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data 65439438955 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 73794583951 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 11594133 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 3644727 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data 4150811 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data 7008612 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 26398283 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 8831185 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 2692903 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data 3278546 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data 5472371 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 20275005 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 231687 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 70763 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 86860 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 134533 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 523843 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 219641 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 76598 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 73615 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 99067 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 468921 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 216972 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 75904 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 72697 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 95048 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 460621 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 20425318 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 6337630 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data 7429357 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data 12480983 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 46673288 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 20657005 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 6408393 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data 7516217 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data 12615516 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 47197131 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.014768 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.014136 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.020210 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.031820 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.020064 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.012674 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.012497 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.032203 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.225732 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.073314 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235097 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.238430 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.216786 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.347989 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.261504 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016855 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.030275 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.047721 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.085144 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038320 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000221 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000046 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013863 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013440 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.025503 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data 0.116842 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.043196 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016344 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015924 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.027713 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data 0.119307 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.045619 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16029.336413 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14293.095638 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15075.915538 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10170.959471 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 36922.176329 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48188.009055 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 50253.377519 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 46020.957366 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12163.648124 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12834.614290 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14645.880261 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10954.059770 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 28500 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 28500 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24284.088241 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33180.749864 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44873.845370 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 36602.822270 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20269.103755 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30181.246650 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43478.061433 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 34274.010614 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 338196 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 50180 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 13872 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 843 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.379758 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 59.525504 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 691721 # number of writebacks
-system.cpu0.dcache.writebacks::total 691721 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 98 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 8313 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 110368 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 118779 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 48697 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1139929 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1188626 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1601 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2421 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5282 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9304 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data 98 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data 57010 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data 1250297 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1307405 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data 98 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data 57010 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data 1250297 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1307405 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 51318 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75092 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112526 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 238936 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 33494 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 56941 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 97134 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 187569 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 16471 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15216 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 32231 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 63918 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 678 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1101 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 3154 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4933 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 17 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 17 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 84812 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data 132033 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data 209660 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 426505 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 101283 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data 147249 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data 241891 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 490423 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 4113 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6742 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7559 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18414 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3215 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5150 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6001 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14366 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 7328 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 11892 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13560 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32780 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 771744500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1005172000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1614519000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3391435500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1202622500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2680384000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4914737428 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8797743928 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 211413000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 208273000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 499697000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 919383000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8610500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 15891500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 52341000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76843000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 448000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 448000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1974367000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3685556000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6529256428 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 12189179428 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2185780000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3893829000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 7028953428 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 13108562428 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 709683000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1313422000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1530005000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3553110000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 546320500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 978935500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1200341982 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725597982 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1256003500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2292357500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2730346982 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6278707982 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014087 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018138 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016057 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009055 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012471 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017368 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017736 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009254 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.233562 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.175261 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.238686 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121950 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.008888 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.014933 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.031783 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010520 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000179 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000037 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013401 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017798 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016793 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.009141 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.015827 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019619 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019168 # mshr miss rate for overall accesses
+system.cpu0.dcache.writebacks::writebacks 692577 # number of writebacks
+system.cpu0.dcache.writebacks::total 692577 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 93 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 8510 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 110579 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 119182 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 48694 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1138393 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1187087 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1619 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2417 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5353 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9389 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data 93 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 57204 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data 1248972 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1306269 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data 93 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 57204 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data 1248972 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1306269 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 51430 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75379 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112432 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 239241 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 33653 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 56886 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 96894 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 187433 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 16552 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15262 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 32143 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 63957 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 700 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1096 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 3082 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4878 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 21 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 85083 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 132265 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data 209326 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 426674 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 101635 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 147527 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data 241469 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 490631 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 4098 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6759 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7555 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18412 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3203 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5165 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 5997 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14365 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 7301 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 11924 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13552 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32777 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 773027500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1007573000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1610752500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3391353000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1208889000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2669627000 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4928516402 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8807032402 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 214952000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 207552500 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 496800000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 919304500 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8874500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 16213500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 51414500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76502500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 577500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 577500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1981916500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3677200000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6539268902 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 12198385402 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2196868500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3884752500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 7036068902 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 13117689902 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 706453000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1317087500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1529047000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3552587500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 543393000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 982352000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1199505482 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725250482 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1249846000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2299439500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2728552482 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6277837982 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014111 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018160 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016042 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009063 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012497 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017351 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017706 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009245 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.233908 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.175708 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.238923 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122092 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.009139 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.014888 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.031110 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010403 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000221 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013425 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017803 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016772 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.009142 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.015860 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019628 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019141 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.010395 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15038.475778 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13385.873329 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14347.964026 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14193.907574 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35905.609960 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47073.005392 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50597.498590 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46904.040263 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12835.468399 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13687.762881 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15503.614533 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14383.788604 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12699.852507 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14433.696639 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16595.117311 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15577.336307 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 26352.941176 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 26352.941176 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23279.335471 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27913.900313 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 31142.117848 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28579.218129 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21580.916837 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26443.840026 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29058.350364 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26729.093921 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172546.316557 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194811.925245 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202408.387353 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192956.989247 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169928.615863 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190084.563107 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200023.659723 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189725.600863 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171397.857533 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 192764.673730 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 201353.022271 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191540.817023 # average overall mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15030.672759 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13366.759973 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14326.459549 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14175.467416 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35922.176329 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46929.420244 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50865.031911 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46987.629724 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12986.466892 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13599.298912 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15455.931307 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14373.790203 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12677.857143 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14793.339416 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16682.186892 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15683.169332 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 27500 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27500 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23293.918879 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27801.761615 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 31239.640092 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28589.474404 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21615.275250 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26332.484901 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29138.601237 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26736.365827 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172389.702294 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194864.255067 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202388.749173 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192949.570932 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169651.264440 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190193.998064 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200017.589128 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189714.617612 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171188.330366 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 192841.286481 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 201339.468861 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191531.805290 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 1978248 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.476093 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 92919349 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1978760 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 46.958372 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 12310007500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 437.578218 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.969081 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 27.366613 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst 33.562181 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.854645 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025330 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.053450 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst 0.065551 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 1976565 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.476096 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 92948208 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 1977077 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 47.012943 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 12310006500 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 437.069776 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.930889 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 27.368710 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst 34.106720 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.853652 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.025256 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst 0.053455 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst 0.066615 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.998977 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 203 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 253 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 260 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 96919206 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 96919206 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 55909224 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 17523727 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 10076714 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst 9409684 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 92919349 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 55909224 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 17523727 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 10076714 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst 9409684 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 92919349 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 55909224 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 17523727 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 10076714 # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst 9409684 # number of overall hits
-system.cpu0.icache.overall_hits::total 92919349 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 744762 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 210607 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 478701 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst 586999 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 2021069 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 744762 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 210607 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 478701 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst 586999 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 2021069 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 744762 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 210607 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 478701 # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst 586999 # number of overall misses
-system.cpu0.icache.overall_misses::total 2021069 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2873833000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6639070000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7864379492 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 17377282492 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 2873833000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 6639070000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst 7864379492 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 17377282492 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 2873833000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 6639070000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst 7864379492 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 17377282492 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 56653986 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 17734334 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 10555415 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst 9996683 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 94940418 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 56653986 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 17734334 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 10555415 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst 9996683 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 94940418 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 56653986 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 17734334 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 10555415 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst 9996683 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 94940418 # number of overall (read+write) accesses
+system.cpu0.icache.tags.tag_accesses 96944326 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 96944326 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 55908893 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 17531533 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 10096307 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu3.inst 9411475 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 92948208 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 55908893 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 17531533 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 10096307 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu3.inst 9411475 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 92948208 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 55908893 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 17531533 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 10096307 # number of overall hits
+system.cpu0.icache.overall_hits::cpu3.inst 9411475 # number of overall hits
+system.cpu0.icache.overall_hits::total 92948208 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 744795 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 210904 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 477702 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu3.inst 585610 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 2019011 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 744795 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 210904 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst 477702 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu3.inst 585610 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 2019011 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 744795 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 210904 # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst 477702 # number of overall misses
+system.cpu0.icache.overall_misses::cpu3.inst 585610 # number of overall misses
+system.cpu0.icache.overall_misses::total 2019011 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 2877146000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 6627355500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 7849748489 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 17354249989 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 2877146000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst 6627355500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu3.inst 7849748489 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 17354249989 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 2877146000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst 6627355500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu3.inst 7849748489 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 17354249989 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 56653688 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 17742437 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst 10574009 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu3.inst 9997085 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 94967219 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 56653688 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 17742437 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst 10574009 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu3.inst 9997085 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 94967219 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 56653688 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 17742437 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst 10574009 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu3.inst 9997085 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 94967219 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013146 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011876 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.045351 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.058719 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.021288 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011887 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.045177 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.058578 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.021260 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013146 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011876 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.045351 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst 0.058719 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.021288 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011887 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst 0.045177 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu3.inst 0.058578 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.021260 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013146 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011876 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.045351 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu3.inst 0.058719 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.021288 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13645.477121 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13868.928621 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13397.602878 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 8598.064931 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13645.477121 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13868.928621 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13397.602878 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 8598.064931 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13645.477121 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13868.928621 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13397.602878 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 8598.064931 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 3152 # number of cycles access was blocked
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011887 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst 0.045177 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu3.inst 0.058578 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.021260 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13641.969806 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13873.409573 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13404.396252 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 8595.421218 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13641.969806 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13873.409573 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13404.396252 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 8595.421218 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13641.969806 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13873.409573 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13404.396252 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 8595.421218 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 3398 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 204 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 209 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.450980 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.258373 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 42281 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 42281 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst 42281 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 42281 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst 42281 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 42281 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 210607 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 478701 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 544718 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 1234026 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 210607 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 478701 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst 544718 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 1234026 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 210607 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 478701 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst 544718 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 1234026 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2663226000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6160369000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 6946186993 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 15769781993 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2663226000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6160369000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 6946186993 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 15769781993 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2663226000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6160369000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 6946186993 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 15769781993 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045351 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054490 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012998 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045351 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054490 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.012998 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011876 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045351 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054490 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.012998 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12645.477121 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12868.928621 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12751.895463 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12779.132687 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12645.477121 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12868.928621 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12751.895463 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12779.132687 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12645.477121 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12868.928621 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12751.895463 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12779.132687 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 41904 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 41904 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst 41904 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 41904 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst 41904 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 41904 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 210904 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 477702 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 543706 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 1232312 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 210904 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 477702 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst 543706 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 1232312 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 210904 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 477702 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst 543706 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 1232312 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2666242000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6149653500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 6934315992 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 15750211492 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2666242000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6149653500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 6934315992 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 15750211492 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2666242000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6149653500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 6934315992 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 15750211492 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011887 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045177 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054386 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012976 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011887 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045177 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054386 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.012976 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011887 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045177 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054386 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.012976 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.025821 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.025821 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.025821 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 1892 # Table walker walks requested
-system.cpu1.dtb.walker.walksShort 1892 # Table walker walks initiated with short descriptors
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 543 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1348 # Level at which table walker walks with short descriptors terminate
-system.cpu1.dtb.walker.walksSquashedBefore 1 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 1891 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 1891 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 1891 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 1530 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 11241.830065 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 9576.039480 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 6337.675963 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.98% 0.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::4096-6143 582 38.04% 39.02% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::10240-12287 519 33.92% 72.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::12288-14335 132 8.63% 81.57% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::14336-16383 18 1.18% 82.75% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::22528-24575 264 17.25% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 1530 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1775778416 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.436843 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.495995 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1000042500 56.32% 56.32% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 775735916 43.68% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1775778416 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 996 65.14% 65.14% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::1M 533 34.86% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 1529 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1892 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walks 1944 # Table walker walks requested
+system.cpu1.dtb.walker.walksShort 1944 # Table walker walks initiated with short descriptors
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 547 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1397 # Level at which table walker walks with short descriptors terminate
+system.cpu1.dtb.walker.walkWaitTime::samples 1944 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 1944 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 1944 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 1569 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 12632.887189 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 11014.350507 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 6231.121643 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.96% 0.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::4096-6143 406 25.88% 26.83% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::10240-12287 522 33.27% 60.10% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::12288-14335 230 14.66% 74.76% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::14336-16383 77 4.91% 79.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::22528-24575 319 20.33% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 1569 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 1032 65.77% 65.77% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::1M 537 34.23% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 1569 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1944 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1892 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1529 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1944 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1569 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1529 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 3421 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1569 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 3513 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 3793903 # DTB read hits
-system.cpu1.dtb.read_misses 1653 # DTB read misses
-system.cpu1.dtb.write_hits 2764720 # DTB write hits
-system.cpu1.dtb.write_misses 239 # DTB write misses
+system.cpu1.dtb.read_hits 3796186 # DTB read hits
+system.cpu1.dtb.read_misses 1676 # DTB read misses
+system.cpu1.dtb.write_hits 2772085 # DTB write hits
+system.cpu1.dtb.write_misses 268 # DTB write misses
system.cpu1.dtb.flush_tlb 152 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva 168 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 1225 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 1249 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 239 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 3795556 # DTB read accesses
-system.cpu1.dtb.write_accesses 2764959 # DTB write accesses
+system.cpu1.dtb.perms_faults 75 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 3797862 # DTB read accesses
+system.cpu1.dtb.write_accesses 2772353 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 6558623 # DTB hits
-system.cpu1.dtb.misses 1892 # DTB misses
-system.cpu1.dtb.accesses 6560515 # DTB accesses
+system.cpu1.dtb.hits 6568271 # DTB hits
+system.cpu1.dtb.misses 1944 # DTB misses
+system.cpu1.dtb.accesses 6570215 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 978 # Table walker walks requested
-system.cpu1.itb.walker.walksShort 978 # Table walker walks initiated with short descriptors
+system.cpu1.itb.walker.walks 1001 # Table walker walks requested
+system.cpu1.itb.walker.walksShort 1001 # Table walker walks initiated with short descriptors
system.cpu1.itb.walker.walksShortTerminationLevel::Level1 197 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walksShortTerminationLevel::Level2 781 # Level at which table walker walks with short descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 978 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 978 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 978 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 708 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 11807.909605 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 9972.994087 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 6711.668965 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::4096-6143 268 37.85% 37.85% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 27.54% 65.40% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::12288-14335 96 13.56% 78.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::14336-16383 3 0.42% 79.38% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::22528-24575 146 20.62% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 708 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1000001500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1000001500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1000001500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 511 72.18% 72.18% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::1M 197 27.82% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 708 # Table walker page sizes translated
+system.cpu1.itb.walker.walksShortTerminationLevel::Level2 804 # Level at which table walker walks with short descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 1001 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 1001 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 1001 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 723 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 12766.251729 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 11015.623409 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 6540.201330 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::4096-6143 211 29.18% 29.18% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 26.97% 56.15% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::12288-14335 151 20.89% 77.04% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::14336-16383 4 0.55% 77.59% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::22528-24575 162 22.41% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 723 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 526 72.75% 72.75% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::1M 197 27.25% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 723 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 978 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 978 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1001 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1001 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 708 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 708 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 1686 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 17734334 # ITB inst hits
-system.cpu1.itb.inst_misses 978 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 723 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 723 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 1724 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 17742437 # ITB inst hits
+system.cpu1.itb.inst_misses 1001 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 152 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 151 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva 168 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 735 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 750 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 17735312 # ITB inst accesses
-system.cpu1.itb.hits 17734334 # DTB hits
-system.cpu1.itb.misses 978 # DTB misses
-system.cpu1.itb.accesses 17735312 # DTB accesses
-system.cpu1.numCycles 143538852 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 17743438 # ITB inst accesses
+system.cpu1.itb.hits 17742437 # DTB hits
+system.cpu1.itb.misses 1001 # DTB misses
+system.cpu1.itb.accesses 17743438 # DTB accesses
+system.cpu1.numCycles 143583360 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 17131755 # Number of instructions committed
-system.cpu1.committedOps 20672467 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 18427801 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 1229 # Number of float alu accesses
-system.cpu1.num_func_calls 2005849 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 2182476 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 18427801 # number of integer instructions
-system.cpu1.num_fp_insts 1229 # number of float instructions
-system.cpu1.num_int_register_reads 34218314 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 12924255 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 840 # number of times the floating registers were read
+system.cpu1.committedInsts 17142475 # Number of instructions committed
+system.cpu1.committedOps 20690900 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 18446976 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 1261 # Number of float alu accesses
+system.cpu1.num_func_calls 2007420 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 2180791 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 18446976 # number of integer instructions
+system.cpu1.num_fp_insts 1261 # number of float instructions
+system.cpu1.num_int_register_reads 34256544 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 12938178 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 872 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 390 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 75293665 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 7369592 # number of times the CC registers were written
-system.cpu1.num_mem_refs 6757135 # number of memory refs
-system.cpu1.num_load_insts 3837451 # Number of load instructions
-system.cpu1.num_store_insts 2919684 # Number of store instructions
-system.cpu1.num_idle_cycles 136561451.428475 # Number of idle cycles
-system.cpu1.num_busy_cycles 6977400.571525 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.048610 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.951390 # Percentage of idle cycles
-system.cpu1.Branches 4295209 # Number of branches fetched
+system.cpu1.num_cc_register_reads 75360742 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 7365753 # number of times the CC registers were written
+system.cpu1.num_mem_refs 6767228 # number of memory refs
+system.cpu1.num_load_insts 3839902 # Number of load instructions
+system.cpu1.num_store_insts 2927326 # Number of store instructions
+system.cpu1.num_idle_cycles 136602426.841061 # Number of idle cycles
+system.cpu1.num_busy_cycles 6980933.158939 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.048619 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.951381 # Percentage of idle cycles
+system.cpu1.Branches 4294582 # Number of branches fetched
system.cpu1.op_class::No_OpClass 47 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 14510863 68.17% 68.17% # Class of executed instruction
-system.cpu1.op_class::IntMult 16280 0.08% 68.25% # Class of executed instruction
-system.cpu1.op_class::IntDiv 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 958 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.25% # Class of executed instruction
-system.cpu1.op_class::MemRead 3837451 18.03% 86.28% # Class of executed instruction
-system.cpu1.op_class::MemWrite 2919684 13.72% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 14519635 68.15% 68.15% # Class of executed instruction
+system.cpu1.op_class::IntMult 16307 0.08% 68.23% # Class of executed instruction
+system.cpu1.op_class::IntDiv 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.23% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 962 0.00% 68.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 68.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.24% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.24% # Class of executed instruction
+system.cpu1.op_class::MemRead 3839902 18.02% 86.26% # Class of executed instruction
+system.cpu1.op_class::MemWrite 2927326 13.74% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 21285283 # Class of executed instruction
+system.cpu1.op_class::total 21304179 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 5610171 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 2857915 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 501995 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 3283896 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 2333083 # Number of BTB hits
+system.cpu2.branchPred.lookups 5611894 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 2863788 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 506095 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 3300567 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 2344817 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 71.046190 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 1583798 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 327364 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 71.042854 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 1575596 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 331093 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.dtb.walker.walks 12445 # Table walker walks requested
-system.cpu2.dtb.walker.walksShort 12445 # Table walker walks initiated with short descriptors
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7726 # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4719 # Level at which table walker walks with short descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples 12445 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0 12445 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total 12445 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples 2100 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 12636.428571 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 10856.238054 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 6881.912938 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-8191 609 29.00% 29.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1011 48.14% 77.14% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::16384-24575 478 22.76% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walks 12465 # Table walker walks requested
+system.cpu2.dtb.walker.walksShort 12465 # Table walker walks initiated with short descriptors
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7792 # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4673 # Level at which table walker walks with short descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples 12465 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0 12465 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total 12465 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples 2089 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 13064.145524 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 11307.663622 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 6855.441685 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-8191 538 25.75% 25.75% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1043 49.93% 75.68% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::16384-24575 506 24.22% 99.90% # Table walker service (enqueue to completion) latency
system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total 2100 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walksPending::samples 2000071000 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::0 2000071000 100.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::total 2000071000 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K 1328 63.24% 63.24% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::1M 772 36.76% 100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total 2100 # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12445 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkCompletionTime::total 2089 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walksPending::samples 2000070000 # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::0 2000070000 100.00% 100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::total 2000070000 # Table walker pending requests distribution
+system.cpu2.dtb.walker.walkPageSizes::4K 1323 63.33% 63.33% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::1M 766 36.67% 100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total 2089 # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12465 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12445 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2100 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12465 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2089 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2100 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total 14545 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2089 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total 14554 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 4343761 # DTB read hits
-system.cpu2.dtb.read_misses 11112 # DTB read misses
-system.cpu2.dtb.write_hits 3378115 # DTB write hits
-system.cpu2.dtb.write_misses 1333 # DTB write misses
+system.cpu2.dtb.read_hits 4354485 # DTB read hits
+system.cpu2.dtb.read_misses 11147 # DTB read misses
+system.cpu2.dtb.write_hits 3379229 # DTB write hits
+system.cpu2.dtb.write_misses 1318 # DTB write misses
system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA
+system.cpu2.dtb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 1535 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 222 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_entries 1531 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 193 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 294 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 123 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 4354873 # DTB read accesses
-system.cpu2.dtb.write_accesses 3379448 # DTB write accesses
+system.cpu2.dtb.perms_faults 117 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 4365632 # DTB read accesses
+system.cpu2.dtb.write_accesses 3380547 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 7721876 # DTB hits
-system.cpu2.dtb.misses 12445 # DTB misses
-system.cpu2.dtb.accesses 7734321 # DTB accesses
+system.cpu2.dtb.hits 7733714 # DTB hits
+system.cpu2.dtb.misses 12465 # DTB misses
+system.cpu2.dtb.accesses 7746179 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.walker.walks 1343 # Table walker walks requested
-system.cpu2.itb.walker.walksShort 1343 # Table walker walks initiated with short descriptors
-system.cpu2.itb.walker.walksShortTerminationLevel::Level1 245 # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1098 # Level at which table walker walks with short descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples 1343 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0 1343 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total 1343 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples 890 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 12592.696629 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 10799.035256 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 6603.898577 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::4096-6143 278 31.24% 31.24% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::10240-12287 236 26.52% 57.75% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::12288-14335 167 18.76% 76.52% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::14336-16383 5 0.56% 77.08% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::22528-24575 204 22.92% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total 890 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walksPending::samples 2000056500 # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::0 2000056500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::total 2000056500 # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K 648 72.81% 72.81% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::1M 242 27.19% 100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total 890 # Table walker page sizes translated
+system.cpu2.itb.walker.walks 1328 # Table walker walks requested
+system.cpu2.itb.walker.walksShort 1328 # Table walker walks initiated with short descriptors
+system.cpu2.itb.walker.walksShortTerminationLevel::Level1 246 # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1082 # Level at which table walker walks with short descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples 1328 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0 1328 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total 1328 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples 881 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 12986.379115 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 11270.183591 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 6464.618437 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::4096-6143 240 27.24% 27.24% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::10240-12287 238 27.01% 54.26% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::12288-14335 191 21.68% 75.94% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::14336-16383 6 0.68% 76.62% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::22528-24575 206 23.38% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total 881 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walksPending::samples 2000055500 # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::0 2000055500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::total 2000055500 # Table walker pending requests distribution
+system.cpu2.itb.walker.walkPageSizes::4K 640 72.64% 72.64% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::1M 241 27.36% 100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total 881 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1343 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1343 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1328 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1328 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 890 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total 890 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total 2233 # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits 10557278 # ITB inst hits
-system.cpu2.itb.inst_misses 1343 # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 881 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total 881 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total 2209 # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits 10575904 # ITB inst hits
+system.cpu2.itb.inst_misses 1328 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 930 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries 923 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 1750 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 1777 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 10558621 # ITB inst accesses
-system.cpu2.itb.hits 10557278 # DTB hits
-system.cpu2.itb.misses 1343 # DTB misses
-system.cpu2.itb.accesses 10558621 # DTB accesses
-system.cpu2.numCycles 1381989702 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 10577232 # ITB inst accesses
+system.cpu2.itb.hits 10575904 # DTB hits
+system.cpu2.itb.misses 1328 # DTB misses
+system.cpu2.itb.accesses 10577232 # DTB accesses
+system.cpu2.numCycles 1381990575 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 19375420 # Number of instructions committed
-system.cpu2.committedOps 23493929 # Number of ops (including micro ops) committed
-system.cpu2.discardedOps 1397443 # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.committedInsts 19415856 # Number of instructions committed
+system.cpu2.committedOps 23538274 # Number of ops (including micro ops) committed
+system.cpu2.discardedOps 1407481 # Number of ops (including micro ops) which were discarded before commit
system.cpu2.numFetchSuspends 550 # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles 4259392331 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi 71.326955 # CPI: cycles per instruction
-system.cpu2.ipc 0.014020 # IPC: instructions per cycle
+system.cpu2.quiesceCycles 4259391923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi 71.178452 # CPI: cycles per instruction
+system.cpu2.ipc 0.014049 # IPC: instructions per cycle
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.tickCycles 41311098 # Number of cycles that the object actually ticked
-system.cpu2.idleCycles 1340678604 # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups 13646054 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 7543734 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 320434 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 8619119 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 6472050 # Number of BTB hits
+system.cpu2.tickCycles 41337448 # Number of cycles that the object actually ticked
+system.cpu2.idleCycles 1340653127 # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups 13659827 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 7557018 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 321485 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 8617850 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 6480530 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 75.089461 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 3094994 # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect 16257 # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct 75.198919 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 3094736 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 16291 # Number of incorrect RAS predictions.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.dtb.walker.walks 35143 # Table walker walks requested
-system.cpu3.dtb.walker.walksShort 35143 # Table walker walks initiated with short descriptors
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 12076 # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7806 # Level at which table walker walks with short descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore 15261 # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples 19882 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean 462.453476 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 3227.731349 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-16383 19738 99.28% 99.28% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::16384-32767 120 0.60% 99.88% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::32768-49151 15 0.08% 99.95% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::49152-65535 2 0.01% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-81919 3 0.02% 99.98% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walks 35471 # Table walker walks requested
+system.cpu3.dtb.walker.walksShort 35471 # Table walker walks initiated with short descriptors
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11945 # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7769 # Level at which table walker walks with short descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore 15757 # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples 19714 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean 617.099523 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 4045.428418 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-16383 19501 98.92% 98.92% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::16384-32767 152 0.77% 99.69% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::32768-49151 42 0.21% 99.90% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::49152-65535 8 0.04% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-81919 7 0.04% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::131072-147455 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total 19882 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples 6311 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 11174.694977 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 9013.738443 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 7509.952707 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-16383 5234 82.93% 82.93% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::16384-32767 989 15.67% 98.61% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::32768-49151 83 1.32% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::49152-65535 2 0.03% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::81920-98303 2 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-147455 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total 6311 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -8699062064 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean 0.943227 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-1 -8742325064 100.50% 100.50% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::2-3 30532500 -0.35% 100.15% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-5 6165000 -0.07% 100.08% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::6-7 1932500 -0.02% 100.05% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-9 1510500 -0.02% 100.04% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::10-11 932000 -0.01% 100.03% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-13 478000 -0.01% 100.02% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::14-15 1202000 -0.01% 100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-17 269000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::18-19 118500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-21 46500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::22-23 12000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-25 31500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::26-27 8000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-29 6000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::30-31 19000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -8699062064 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K 1800 71.51% 71.51% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::1M 717 28.49% 100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total 2517 # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 35143 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkWaitTime::total 19714 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples 6425 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 12552.451362 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 10392.470797 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 7297.231216 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-8191 1902 29.60% 29.60% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::8192-16383 3093 48.14% 77.74% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::16384-24575 1290 20.08% 97.82% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::24576-32767 56 0.87% 98.69% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::32768-40959 42 0.65% 99.35% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::40960-49151 37 0.58% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::49152-57343 1 0.02% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::81920-90111 1 0.02% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total 6425 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -8701578064 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean 1.155310 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-1 -8749138564 100.55% 100.55% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::2-3 32608500 -0.37% 100.17% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-5 7394500 -0.08% 100.09% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::6-7 2262500 -0.03% 100.06% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-9 1618000 -0.02% 100.04% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::10-11 1153500 -0.01% 100.03% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-13 459000 -0.01% 100.02% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::14-15 1335500 -0.02% 100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-17 300000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::18-19 181000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-21 108000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::22-23 25500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-25 53500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::26-27 12000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-29 19000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::30-31 30000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -8701578064 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K 1781 71.41% 71.41% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::1M 713 28.59% 100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total 2494 # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 35471 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 35143 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2517 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 35471 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2494 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2517 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total 37660 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2494 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total 37965 # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
-system.cpu3.dtb.read_hits 7578904 # DTB read hits
-system.cpu3.dtb.read_misses 29166 # DTB read misses
-system.cpu3.dtb.write_hits 5839969 # DTB write hits
-system.cpu3.dtb.write_misses 5977 # DTB write misses
+system.cpu3.dtb.read_hits 7577935 # DTB read hits
+system.cpu3.dtb.read_misses 29413 # DTB read misses
+system.cpu3.dtb.write_hits 5839655 # DTB write hits
+system.cpu3.dtb.write_misses 6058 # DTB write misses
system.cpu3.dtb.flush_tlb 158 # Number of times complete TLB was flushed
-system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA
+system.cpu3.dtb.flush_tlb_mva 224 # Number of times TLB was flushed by MVA
system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries 1718 # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults 425 # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults 723 # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults 415 # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults 739 # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults 310 # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses 7608070 # DTB read accesses
-system.cpu3.dtb.write_accesses 5845946 # DTB write accesses
+system.cpu3.dtb.perms_faults 327 # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses 7607348 # DTB read accesses
+system.cpu3.dtb.write_accesses 5845713 # DTB write accesses
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu3.dtb.hits 13418873 # DTB hits
-system.cpu3.dtb.misses 35143 # DTB misses
-system.cpu3.dtb.accesses 13454016 # DTB accesses
+system.cpu3.dtb.hits 13417590 # DTB hits
+system.cpu3.dtb.misses 35471 # DTB misses
+system.cpu3.dtb.accesses 13453061 # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.itb.walker.walks 4732 # Table walker walks requested
-system.cpu3.itb.walker.walksShort 4732 # Table walker walks initiated with short descriptors
-system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1951 # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2718 # Level at which table walker walks with short descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples 4669 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean 1610.409081 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev 7290.700462 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-16383 4501 96.40% 96.40% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::16384-32767 127 2.72% 99.12% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-49151 19 0.41% 99.53% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::49152-65535 9 0.19% 99.72% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-81919 6 0.13% 99.85% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::81920-98303 3 0.06% 99.91% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::98304-114687 2 0.04% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walks 4217 # Table walker walks requested
+system.cpu3.itb.walker.walksShort 4217 # Table walker walks initiated with short descriptors
+system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1465 # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2667 # Level at which table walker walks with short descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore 85 # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples 4132 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean 1732.090997 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev 7203.300582 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-16383 3973 96.15% 96.15% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::16384-32767 122 2.95% 99.10% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-49151 16 0.39% 99.49% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::49152-65535 12 0.29% 99.78% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-81919 4 0.10% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::81920-98303 2 0.05% 99.93% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-114687 1 0.02% 99.95% # Table walker wait (enqueue to first request) latency
system.cpu3.itb.walker.walkWaitTime::114688-131071 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::147456-163839 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total 4669 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples 1251 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 12846.922462 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 10663.579337 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 7853.199891 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-4095 16 1.28% 1.28% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::4096-8191 403 32.21% 33.49% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::8192-12287 333 26.62% 60.11% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::12288-16383 200 15.99% 76.10% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::16384-20479 15 1.20% 77.30% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::20480-24575 250 19.98% 97.28% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::24576-28671 6 0.48% 97.76% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::28672-32767 4 0.32% 98.08% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-36863 2 0.16% 98.24% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::36864-40959 7 0.56% 98.80% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::40960-45055 12 0.96% 99.76% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkWaitTime::131072-147455 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total 4132 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples 1265 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 13666.007905 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 11737.085754 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 7328.478477 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-4095 21 1.66% 1.66% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::4096-8191 283 22.37% 24.03% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::8192-12287 342 27.04% 51.07% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::12288-16383 308 24.35% 75.42% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::16384-20479 17 1.34% 76.76% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::20480-24575 261 20.63% 97.39% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::24576-28671 6 0.47% 97.87% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::28672-32767 7 0.55% 98.42% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::32768-36863 1 0.08% 98.50% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::36864-40959 7 0.55% 99.05% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::40960-45055 9 0.71% 99.76% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::45056-49151 2 0.16% 99.92% # Table walker service (enqueue to completion) latency
system.cpu3.itb.walker.walkCompletionTime::57344-61439 1 0.08% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total 1251 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -394920472 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean -1.156632 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0 -848106296 214.75% 214.75% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1 450855824 -114.16% 100.59% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2 1608500 -0.41% 100.18% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3 392000 -0.10% 100.08% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4 207000 -0.05% 100.03% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5 65000 -0.02% 100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::6 26500 -0.01% 100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::7 31000 -0.01% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -394920472 # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K 859 72.31% 72.31% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::1M 329 27.69% 100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total 1188 # Table walker page sizes translated
+system.cpu3.itb.walker.walkCompletionTime::total 1265 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -8974548064 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean 0.863052 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::stdev 0.342327 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0 -1226005296 13.66% 13.66% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1 -7750612268 86.36% 100.02% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2 1421000 -0.02% 100.01% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3 452500 -0.01% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4 116500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5 31500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::6 48000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -8974548064 # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K 850 72.03% 72.03% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::1M 330 27.97% 100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total 1180 # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4732 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4732 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4217 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4217 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1188 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1188 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total 5920 # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits 9997642 # ITB inst hits
-system.cpu3.itb.inst_misses 4732 # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1180 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1180 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total 5397 # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits 9998093 # ITB inst hits
+system.cpu3.itb.inst_misses 4217 # ITB inst misses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
system.cpu3.itb.flush_tlb 158 # Number of times complete TLB was flushed
-system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA
+system.cpu3.itb.flush_tlb_mva 224 # Number of times TLB was flushed by MVA
system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries 1217 # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_entries 1209 # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults 676 # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults 709 # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.inst_accesses 10002374 # ITB inst accesses
-system.cpu3.itb.hits 9997642 # DTB hits
-system.cpu3.itb.misses 4732 # DTB misses
-system.cpu3.itb.accesses 10002374 # DTB accesses
-system.cpu3.numCycles 55587045 # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses 10002310 # ITB inst accesses
+system.cpu3.itb.hits 9998093 # DTB hits
+system.cpu3.itb.misses 4217 # DTB misses
+system.cpu3.itb.accesses 10002310 # DTB accesses
+system.cpu3.numCycles 55588609 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 20927206 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 54552679 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 13646054 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 9567044 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 32032256 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 1608040 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles 79957 # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles 938 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles 213 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles 310222 # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles 78152 # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines 9996683 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 215580 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes 2118 # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples 54233142 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.214742 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.347105 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles 20911805 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 54608834 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 13659827 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 9575266 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 32188027 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 1609304 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles 73500 # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles 636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles 188 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles 174621 # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles 79934 # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles 246 # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines 9997086 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 214812 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes 2061 # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples 54233591 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.215961 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.348203 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 39601274 73.02% 73.02% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 1868483 3.45% 76.47% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 1208105 2.23% 78.69% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 3698353 6.82% 85.51% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 956006 1.76% 87.28% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 647778 1.19% 88.47% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 2970918 5.48% 93.95% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 646722 1.19% 95.14% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 2635503 4.86% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 39592641 73.00% 73.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 1866738 3.44% 76.45% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 1209172 2.23% 78.68% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 3694476 6.81% 85.49% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 961111 1.77% 87.26% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 647261 1.19% 88.45% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 2977203 5.49% 93.94% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 646450 1.19% 95.13% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 2638539 4.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 54233142 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.245490 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 0.981392 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 14598894 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 29797113 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 8084772 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 1033348 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 718831 # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved 1078244 # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred 86337 # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts 47705679 # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts 276961 # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles 718831 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 15136583 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 3024863 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 21172664 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 8572569 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 5607363 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 45758805 # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents 705 # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents 1147656 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents 110939 # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents 3950348 # Number of times rename has blocked due to SQ full
-system.cpu3.rename.RenamedOperands 47566105 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 210305694 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 51528880 # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups 3583 # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps 39455162 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 8110943 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 731184 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 676901 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 5765226 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 8100915 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 6455257 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 1173886 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 1646906 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 43984199 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 534989 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 41793570 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 55806 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 6489424 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 14897600 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 57980 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 54233142 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 0.770628 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.467625 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 54233591 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.245731 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 0.982375 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 14602129 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 29778773 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 8106369 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 1026636 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 719503 # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved 1079419 # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred 86358 # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts 47749839 # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts 276699 # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles 719503 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 15137242 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 3025598 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 21153466 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 8589840 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 5607720 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 45799280 # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents 610 # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents 1145187 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents 113658 # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents 3954911 # Number of times rename has blocked due to SQ full
+system.cpu3.rename.RenamedOperands 47609045 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 210470711 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 51575848 # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups 3589 # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps 39452126 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 8156919 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 730493 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 676284 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 5731608 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 8102362 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 6460033 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 1172202 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 1643889 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 44018542 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 534103 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 41806723 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 56092 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 6528844 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 14989618 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 58298 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 54233591 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 0.770864 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.468112 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 37814670 69.73% 69.73% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 5400070 9.96% 79.68% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 4120767 7.60% 87.28% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 3382476 6.24% 93.52% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 1384183 2.55% 96.07% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 849283 1.57% 97.64% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 885452 1.63% 99.27% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 261249 0.48% 99.75% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 134992 0.25% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 37808852 69.71% 69.71% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 5406123 9.97% 79.68% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 4124283 7.60% 87.29% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 3378417 6.23% 93.52% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 1383474 2.55% 96.07% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 844457 1.56% 97.63% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 890959 1.64% 99.27% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 261360 0.48% 99.75% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 135666 0.25% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 54233142 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 54233591 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 63553 10.11% 10.11% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 64650 10.11% 10.11% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntMult 0 0.00% 10.11% # attempts to use FU when none available
system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.11% # attempts to use FU when none available
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.11% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.11% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.11% # attempts to use FU when none available
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.11% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 286976 45.65% 55.76% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 278158 44.24% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 286710 44.85% 54.96% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 287936 45.04% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.FU_type_0::No_OpClass 64 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 27814370 66.55% 66.55% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 30310 0.07% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.62% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 2311 0.01% 66.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 1 0.00% 66.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.63% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 7807777 18.68% 85.31% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 6138736 14.69% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 27827699 66.56% 66.56% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 30281 0.07% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 2306 0.01% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.64% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 7806443 18.67% 85.31% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 6139930 14.69% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 41793570 # Type of FU issued
-system.cpu3.iq.rate 0.751858 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 628687 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.015043 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 138497118 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 51032224 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 40586618 # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads 7657 # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes 4185 # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses 3350 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 42418091 # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses 4102 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 178986 # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total 41806723 # Type of FU issued
+system.cpu3.iq.rate 0.752074 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 639296 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.015292 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 138534759 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 51105205 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 40599791 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads 7666 # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes 4221 # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses 3348 # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses 42441848 # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses 4107 # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads 178912 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 1277727 # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses 1461 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 28401 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 648748 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 1280236 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 1538 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 28536 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 657537 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads 106985 # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked 49122 # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads 107166 # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked 47571 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 718831 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 2574270 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 340639 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 44583748 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 79881 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 8100915 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 6455257 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 277620 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 23691 # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents 310856 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 28401 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 151779 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 129603 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 281382 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 41441394 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 7665414 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 317113 # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles 719503 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 2584673 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 329572 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 44617850 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 80448 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 8102362 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 6460033 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 277261 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 23890 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents 299738 # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents 28536 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 153085 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 129623 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 282708 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 41453550 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 7664420 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 317790 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 64560 # number of nop insts executed
-system.cpu3.iew.exec_refs 13741668 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 7578657 # Number of branches executed
-system.cpu3.iew.exec_stores 6076254 # Number of stores executed
-system.cpu3.iew.exec_rate 0.745523 # Inst execution rate
-system.cpu3.iew.wb_sent 41128495 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 40589968 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 21345679 # num instructions producing a value
-system.cpu3.iew.wb_consumers 37833149 # num instructions consuming a value
+system.cpu3.iew.exec_nop 65205 # number of nop insts executed
+system.cpu3.iew.exec_refs 13740951 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 7582733 # Number of branches executed
+system.cpu3.iew.exec_stores 6076531 # Number of stores executed
+system.cpu3.iew.exec_rate 0.745720 # Inst execution rate
+system.cpu3.iew.wb_sent 41141473 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 40603139 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 21356385 # num instructions producing a value
+system.cpu3.iew.wb_consumers 37848912 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 0.730206 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.564206 # average fanout of values written-back
+system.cpu3.iew.wb_rate 0.730422 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.564254 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 6509597 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 477009 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 235228 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 52878842 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 0.719887 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.616953 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 6551591 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 475805 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 236318 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 52873966 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 0.719843 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.617254 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 38356720 72.54% 72.54% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 6383323 12.07% 84.61% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 3220180 6.09% 90.70% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 1427186 2.70% 93.40% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 783029 1.48% 94.88% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 553691 1.05% 95.93% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 963741 1.82% 97.75% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 249255 0.47% 98.22% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 941717 1.78% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 38351228 72.53% 72.53% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 6390419 12.09% 84.62% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 3217103 6.08% 90.70% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 1425073 2.70% 93.40% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 785450 1.49% 94.88% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 547204 1.03% 95.92% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 964459 1.82% 97.74% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 247730 0.47% 98.21% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 945300 1.79% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 52878842 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 31212680 # Number of instructions committed
-system.cpu3.commit.committedOps 38066779 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 52873966 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 31209379 # Number of instructions committed
+system.cpu3.commit.committedOps 38060928 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 12629697 # Number of memory references committed
-system.cpu3.commit.loads 6823188 # Number of loads committed
-system.cpu3.commit.membars 185407 # Number of memory barriers committed
-system.cpu3.commit.branches 7131780 # Number of branches committed
+system.cpu3.commit.refs 12624622 # Number of memory references committed
+system.cpu3.commit.loads 6822126 # Number of loads committed
+system.cpu3.commit.membars 184951 # Number of memory barriers committed
+system.cpu3.commit.branches 7133186 # Number of branches committed
system.cpu3.commit.fp_insts 3315 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 33217803 # Number of committed integer instructions.
-system.cpu3.commit.function_calls 1242593 # Number of function calls committed.
+system.cpu3.commit.int_insts 33210326 # Number of committed integer instructions.
+system.cpu3.commit.function_calls 1242319 # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu 25405548 66.74% 66.74% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult 29226 0.08% 66.82% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu 25404774 66.75% 66.75% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult 29228 0.08% 66.82% # Class of committed instruction
system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction
system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction
system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc 2308 0.01% 66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.82% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead 6823188 17.92% 84.75% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite 5806509 15.25% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc 2304 0.01% 66.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead 6822126 17.92% 84.75% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite 5802496 15.25% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total 38066779 # Class of committed instruction
-system.cpu3.commit.bw_lim_events 941717 # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads 90938636 # The number of ROB reads
-system.cpu3.rob.rob_writes 90509785 # The number of ROB writes
-system.cpu3.timesIdled 219189 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 1353903 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 5161759281 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 31175665 # Number of Instructions Simulated
-system.cpu3.committedOps 38029764 # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi 1.783027 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 1.783027 # CPI: Total CPI of All Threads
-system.cpu3.ipc 0.560844 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 0.560844 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 45482682 # number of integer regfile reads
-system.cpu3.int_regfile_writes 25425363 # number of integer regfile writes
-system.cpu3.fp_regfile_reads 14224 # number of floating regfile reads
-system.cpu3.fp_regfile_writes 12010 # number of floating regfile writes
-system.cpu3.cc_regfile_reads 146149493 # number of cc regfile reads
-system.cpu3.cc_regfile_writes 16057585 # number of cc regfile writes
-system.cpu3.misc_regfile_reads 75089133 # number of misc regfile reads
-system.cpu3.misc_regfile_writes 354942 # number of misc regfile writes
+system.cpu3.commit.op_class_0::total 38060928 # Class of committed instruction
+system.cpu3.commit.bw_lim_events 945300 # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads 90970787 # The number of ROB reads
+system.cpu3.rob.rob_writes 90587481 # The number of ROB writes
+system.cpu3.timesIdled 219785 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 1355018 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 5161755203 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 31172252 # Number of Instructions Simulated
+system.cpu3.committedOps 38023801 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 1.783272 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 1.783272 # CPI: Total CPI of All Threads
+system.cpu3.ipc 0.560767 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.560767 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 45496208 # number of integer regfile reads
+system.cpu3.int_regfile_writes 25431004 # number of integer regfile writes
+system.cpu3.fp_regfile_reads 14216 # number of floating regfile reads
+system.cpu3.fp_regfile_writes 12004 # number of floating regfile writes
+system.cpu3.cc_regfile_reads 146184815 # number of cc regfile reads
+system.cpu3.cc_regfile_writes 16067235 # number of cc regfile writes
+system.cpu3.misc_regfile_reads 75058867 # number of misc regfile reads
+system.cpu3.misc_regfile_writes 353976 # number of misc regfile writes
system.iobus.trans_dist::ReadReq 30152 # Transaction distribution
system.iobus.trans_dist::ReadResp 30152 # Transaction distribution
system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 23980000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.occupancy 23971000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 3354000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 3350000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 85000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 18876000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.occupancy 18885000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 75000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 72450078 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 72461073 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 50566000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 50561000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36410 # number of replacements
-system.iocache.tags.tagsinuse 1.001831 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.001949 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 248566208509 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 1.001831 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.062614 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.062614 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 248566131009 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 1.001949 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.062622 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.062622 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.overall_misses::total 220 # number of overall misses
system.iocache.ReadReq_miss_latency::realview.ide 16046914 # number of ReadReq miss cycles
system.iocache.ReadReq_miss_latency::total 16046914 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 1650207164 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 1650207164 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 1649931159 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 1649931159 # number of WriteLineReq miss cycles
system.iocache.demand_miss_latency::realview.ide 16046914 # number of demand (read+write) miss cycles
system.iocache.demand_miss_latency::total 16046914 # number of demand (read+write) miss cycles
system.iocache.overall_miss_latency::realview.ide 16046914 # number of overall miss cycles
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
system.iocache.ReadReq_avg_miss_latency::realview.ide 72940.518182 # average ReadReq miss latency
system.iocache.ReadReq_avg_miss_latency::total 72940.518182 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45555.630632 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 45555.630632 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45548.011236 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 45548.011236 # average WriteLineReq miss latency
system.iocache.demand_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency
system.iocache.demand_avg_miss_latency::total 72940.518182 # average overall miss latency
system.iocache.overall_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency
system.iocache.overall_mshr_misses::total 135 # number of overall MSHR misses
system.iocache.ReadReq_mshr_miss_latency::realview.ide 9296914 # number of ReadReq MSHR miss cycles
system.iocache.ReadReq_mshr_miss_latency::total 9296914 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 951007164 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 951007164 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 950731159 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 950731159 # number of WriteLineReq MSHR miss cycles
system.iocache.demand_mshr_miss_latency::realview.ide 9296914 # number of demand (read+write) MSHR miss cycles
system.iocache.demand_mshr_miss_latency::total 9296914 # number of demand (read+write) MSHR miss cycles
system.iocache.overall_mshr_miss_latency::realview.ide 9296914 # number of overall MSHR miss cycles
system.iocache.overall_mshr_miss_rate::total 0.613636 # mshr miss rate for overall accesses
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68866.029630 # average ReadReq mshr miss latency
system.iocache.ReadReq_avg_mshr_miss_latency::total 68866.029630 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68006.805206 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68006.805206 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67987.068006 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67987.068006 # average WriteLineReq mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency
system.iocache.demand_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 101303 # number of replacements
-system.l2c.tags.tagsinuse 65108.070418 # Cycle average of tags in use
-system.l2c.tags.total_refs 5168936 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 166462 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 31.051748 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 79214811500 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 48981.200793 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.935125 # Average occupied blocks per requestor
+system.l2c.tags.replacements 101236 # number of replacements
+system.l2c.tags.tagsinuse 65107.326464 # Cycle average of tags in use
+system.l2c.tags.total_refs 5169585 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 166405 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 31.066284 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 79214835000 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 49083.542399 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902823 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 4737.303132 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 1924.234554 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 793.012275 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 757.975635 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 22.711590 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006773 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 2669.581018 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 709.597353 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker 49.846649 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 2547.275002 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 1913.390425 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.747394 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy
+system.l2c.tags.occ_blocks::cpu0.inst 4686.027695 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 1888.757570 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 762.533127 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 823.027459 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker 21.612176 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006778 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 2605.585835 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 671.628280 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.dtb.walker 48.673794 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst 2617.148912 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data 1895.879520 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.748955 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.072286 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.029361 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.012100 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.011566 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000347 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.071503 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.028820 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.011635 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.012558 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000330 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.040735 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.010828 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000761 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.038868 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.029196 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.993470 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 50 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 65109 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 50 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
+system.l2c.tags.occ_percent::cpu2.inst 0.039758 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.010248 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000743 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst 0.039935 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data 0.028929 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.993459 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 65117 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1023::4 52 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2282 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 8086 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 54700 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000763 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.993484 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 45646881 # Number of tag accesses
-system.l2c.tags.data_accesses 45646881 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 4200 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 2163 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 1338 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 747 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 13212 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 1162 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.dtb.walker 20914 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.itb.walker 4752 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 48488 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 691721 # number of Writeback hits
-system.l2c.Writeback_hits::total 691721 # number of Writeback hits
+system.l2c.tags.age_task_id_blocks_1024::2 2279 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 8100 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 54698 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024 0.993607 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 45651328 # Number of tag accesses
+system.l2c.tags.data_accesses 45651328 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker 4883 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 2386 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 1737 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 894 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker 13247 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker 1208 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.dtb.walker 21839 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.itb.walker 4721 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 50915 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 692577 # number of Writeback hits
+system.l2c.Writeback_hits::total 692577 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 6 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data 9 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3.data 21 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 1 # number of SCUpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data 7 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3.data 25 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 49 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data 10 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 11 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 67332 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 21178 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 26251 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3.data 44047 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 158808 # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst 736913 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst 208708 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst 472854 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst 539069 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total 1957544 # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 224011 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 66058 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data 89648 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data 143036 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 522753 # number of ReadSharedReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 4200 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 2163 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 736913 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 291343 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 1338 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 747 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 208708 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 87236 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker 13212 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker 1162 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 472854 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 115899 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.dtb.walker 20914 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.itb.walker 4752 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 539069 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data 187083 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2687593 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 4200 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 2163 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 736913 # number of overall hits
-system.l2c.overall_hits::cpu0.data 291343 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 1338 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 747 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 208708 # number of overall hits
-system.l2c.overall_hits::cpu1.data 87236 # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker 13212 # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker 1162 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 472854 # number of overall hits
-system.l2c.overall_hits::cpu2.data 115899 # number of overall hits
-system.l2c.overall_hits::cpu3.dtb.walker 20914 # number of overall hits
-system.l2c.overall_hits::cpu3.itb.walker 4752 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 539069 # number of overall hits
-system.l2c.overall_hits::cpu3.data 187083 # number of overall hits
-system.l2c.overall_hits::total 2687593 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
+system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0.data 67466 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 21347 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data 26309 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3.data 43752 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 158874 # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst 736958 # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst 209010 # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst 471846 # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst 538057 # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total 1955871 # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data 224298 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data 66271 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data 89985 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data 142818 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total 523372 # number of ReadSharedReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 4883 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 2386 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 736958 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 291764 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 1737 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 894 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 209010 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 87618 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker 13247 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker 1208 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 471846 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 116294 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.dtb.walker 21839 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.itb.walker 4721 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst 538057 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data 186570 # number of demand (read+write) hits
+system.l2c.demand_hits::total 2689032 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 4883 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 2386 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 736958 # number of overall hits
+system.l2c.overall_hits::cpu0.data 291764 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 1737 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 894 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 209010 # number of overall hits
+system.l2c.overall_hits::cpu1.data 87618 # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker 13247 # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker 1208 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 471846 # number of overall hits
+system.l2c.overall_hits::cpu2.data 116294 # number of overall hits
+system.l2c.overall_hits::cpu3.dtb.walker 21839 # number of overall hits
+system.l2c.overall_hits::cpu3.itb.walker 4721 # number of overall hits
+system.l2c.overall_hits::cpu3.inst 538057 # number of overall hits
+system.l2c.overall_hits::cpu3.data 186570 # number of overall hits
+system.l2c.overall_hits::total 2689032 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker 33 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker 31 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.dtb.walker 69 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 108 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 1068 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 470 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 477 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data 737 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2752 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu3.data 7 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 7 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 43391 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 11840 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 30205 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data 52337 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 137773 # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst 7845 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst 1896 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst 5840 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst 5565 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total 21146 # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 5023 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 2409 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data 1760 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data 4867 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 14059 # number of ReadSharedReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
+system.l2c.ReadReq_misses::cpu3.dtb.walker 66 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 104 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 1067 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 483 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 474 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data 722 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2746 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu3.data 11 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 11 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 43380 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 11817 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 30097 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data 52401 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 137695 # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst 7833 # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst 1891 # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst 5849 # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst 5574 # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total 21147 # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data 5096 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data 2411 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data 1751 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data 4833 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total 14091 # number of ReadSharedReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 7845 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 48414 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 1896 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 14249 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker 33 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 7833 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 48476 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 1891 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 14228 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker 31 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 5840 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 31965 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.dtb.walker 69 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst 5565 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data 57204 # number of demand (read+write) misses
-system.l2c.demand_misses::total 173086 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
+system.l2c.demand_misses::cpu2.inst 5849 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 31848 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.dtb.walker 66 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst 5574 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data 57234 # number of demand (read+write) misses
+system.l2c.demand_misses::total 173037 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 7845 # number of overall misses
-system.l2c.overall_misses::cpu0.data 48414 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 1896 # number of overall misses
-system.l2c.overall_misses::cpu1.data 14249 # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker 33 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 7833 # number of overall misses
+system.l2c.overall_misses::cpu0.data 48476 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 1891 # number of overall misses
+system.l2c.overall_misses::cpu1.data 14228 # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker 31 # number of overall misses
system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 5840 # number of overall misses
-system.l2c.overall_misses::cpu2.data 31965 # number of overall misses
-system.l2c.overall_misses::cpu3.dtb.walker 69 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 5565 # number of overall misses
-system.l2c.overall_misses::cpu3.data 57204 # number of overall misses
-system.l2c.overall_misses::total 173086 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2811000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker 82500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 6272000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 9165500 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 31000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data 154500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3.data 184500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 370000 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::cpu3.data 194000 # number of SCUpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency::total 194000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 915490000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 2302823000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data 4277288000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 7495601000 # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst 155074500 # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst 475343000 # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst 458780500 # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total 1089198000 # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data 195409500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data 145904000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data 422430000 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 763743500 # number of ReadSharedReq miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 155074500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 1110899500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker 2811000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker 82500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 475343000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 2448727000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.dtb.walker 6272000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst 458780500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data 4699718000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 9357708000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 155074500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 1110899500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker 2811000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker 82500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 475343000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 2448727000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.dtb.walker 6272000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst 458780500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data 4699718000 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 9357708000 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 4204 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 2164 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 1338 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 747 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker 13245 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker 1163 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.dtb.walker 20983 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.itb.walker 4752 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 48596 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 691721 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 691721 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 1079 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 476 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 486 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data 758 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2799 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 1 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu3.data 17 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 18 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 110723 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 33018 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 56456 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data 96384 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 296581 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst 744758 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst 210604 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst 478694 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst 544634 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total 1978690 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 229034 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 68467 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data 91408 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data 147903 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 536812 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 4204 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 2164 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 744758 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 339757 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 1338 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 747 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 210604 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 101485 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker 13245 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker 1163 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 478694 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 147864 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.dtb.walker 20983 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.itb.walker 4752 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst 544634 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data 244287 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2860679 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 4204 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 2164 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 744758 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 339757 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 1338 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 747 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 210604 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 101485 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker 13245 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker 1163 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 478694 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 147864 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.dtb.walker 20983 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.itb.walker 4752 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst 544634 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data 244287 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2860679 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000951 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000462 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.002492 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000860 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003288 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.002222 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989805 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.987395 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 0.981481 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data 0.972296 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.983208 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.411765 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.388889 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.391888 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.358592 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 0.535018 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data 0.543005 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.464538 # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010534 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.009003 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.012200 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010218 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total 0.010687 # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.021931 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.035185 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.019254 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.032907 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.026190 # miss rate for ReadSharedReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000951 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000462 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.010534 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.142496 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.009003 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.140405 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker 0.002492 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker 0.000860 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.012200 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.216178 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003288 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.010218 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data 0.234167 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.060505 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000951 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000462 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.010534 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.142496 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.009003 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.140405 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker 0.002492 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker 0.000860 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.012200 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.216178 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003288 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.010218 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data 0.234167 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.060505 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85181.818182 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 82500 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 90898.550725 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 84865.740741 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 65.957447 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 323.899371 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 250.339213 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 134.447674 # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 27714.285714 # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total 27714.285714 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77321.790541 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 76239.794736 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 81725.891816 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 54405.442285 # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81790.348101 # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 81394.349315 # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 82440.341420 # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 51508.464958 # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 81116.438356 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82900 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 86794.740086 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 54324.169571 # average ReadSharedReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 81790.348101 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 77963.330760 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85181.818182 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker 82500 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 81394.349315 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 76606.507117 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 90898.550725 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 82440.341420 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 82157.156842 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 54063.921981 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 81790.348101 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 77963.330760 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85181.818182 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker 82500 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 81394.349315 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 76606.507117 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 90898.550725 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 82440.341420 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 82157.156842 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 54063.921981 # average overall miss latency
+system.l2c.overall_misses::cpu2.inst 5849 # number of overall misses
+system.l2c.overall_misses::cpu2.data 31848 # number of overall misses
+system.l2c.overall_misses::cpu3.dtb.walker 66 # number of overall misses
+system.l2c.overall_misses::cpu3.inst 5574 # number of overall misses
+system.l2c.overall_misses::cpu3.data 57234 # number of overall misses
+system.l2c.overall_misses::total 173037 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 2620000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.itb.walker 83000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 5711000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 8414000 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 61500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data 184500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3.data 275500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 521500 # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu3.data 256000 # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total 256000 # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data 919344500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 2291625500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data 4294703000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 7505673000 # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst 154460000 # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst 476710500 # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst 459124500 # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total 1090295000 # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data 197936000 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data 143845500 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data 418005000 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total 759786500 # number of ReadSharedReq miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 154460000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 1117280500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker 2620000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.itb.walker 83000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 476710500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 2435471000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.dtb.walker 5711000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst 459124500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data 4712708000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 9364168500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 154460000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 1117280500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker 2620000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.itb.walker 83000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 476710500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 2435471000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.dtb.walker 5711000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst 459124500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data 4712708000 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 9364168500 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 4888 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 2387 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 1737 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 894 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker 13278 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker 1209 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.dtb.walker 21905 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.itb.walker 4721 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 51019 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 692577 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 692577 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 1078 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 489 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 481 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data 747 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 2795 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu3.data 21 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 21 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 110846 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 33164 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 56406 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data 96153 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 296569 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst 744791 # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst 210901 # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst 477695 # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst 543631 # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total 1977018 # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data 229394 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data 68682 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data 91736 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data 147651 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total 537463 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 4888 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 2387 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 744791 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 340240 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 1737 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 894 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 210901 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 101846 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker 13278 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker 1209 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 477695 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 148142 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.dtb.walker 21905 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.itb.walker 4721 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst 543631 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data 243804 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2862069 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 4888 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 2387 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 744791 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 340240 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 1737 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 894 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 210901 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 101846 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker 13278 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker 1209 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 477695 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 148142 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.dtb.walker 21905 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.itb.walker 4721 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst 543631 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data 243804 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2862069 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001023 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000419 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.002335 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000827 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003013 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.002038 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.989796 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.987730 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data 0.985447 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data 0.966533 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.982469 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.523810 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 0.523810 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.391354 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.356320 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 0.533578 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data 0.544975 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.464293 # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.010517 # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.008966 # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.012244 # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.010253 # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total 0.010696 # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.022215 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.035104 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.019087 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.032733 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total 0.026218 # miss rate for ReadSharedReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001023 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000419 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.010517 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.142476 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.008966 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.139701 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker 0.002335 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker 0.000827 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.012244 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.214983 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003013 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst 0.010253 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data 0.234754 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.060459 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001023 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000419 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.010517 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.142476 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.008966 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.139701 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker 0.002335 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.itb.walker 0.000827 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.012244 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.214983 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003013 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst 0.010253 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data 0.234754 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.060459 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84516.129032 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 83000 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 86530.303030 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 80903.846154 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 127.329193 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 389.240506 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 381.578947 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 189.912600 # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 23272.727273 # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::total 23272.727273 # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 77798.468308 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 76141.326378 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 81958.416824 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 54509.408475 # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81681.649921 # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 81502.906480 # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 82368.945102 # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 51557.904194 # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82097.055164 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 82150.485437 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 86489.757914 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 53919.984387 # average ReadSharedReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 81681.649921 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 78526.883610 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84516.129032 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.itb.walker 83000 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 81502.906480 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 76471.709370 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 86530.303030 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 82368.945102 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 82341.056016 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 54116.567555 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 81681.649921 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 78526.883610 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84516.129032 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker 83000 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 81502.906480 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 76471.709370 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 86530.303030 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 82368.945102 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 82341.056016 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 54116.567555 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 92980 # number of writebacks
-system.l2c.writebacks::total 92980 # number of writebacks
+system.l2c.writebacks::writebacks 92684 # number of writebacks
+system.l2c.writebacks::total 92684 # number of writebacks
system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 3 # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 5 # number of ReadCleanReq MSHR hits
-system.l2c.ReadCleanReq_mshr_hits::total 8 # number of ReadCleanReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu2.data 23 # number of ReadSharedReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 4 # number of ReadCleanReq MSHR hits
+system.l2c.ReadCleanReq_mshr_hits::total 7 # number of ReadCleanReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu2.data 25 # number of ReadSharedReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu3.data 42 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total 65 # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total 67 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu2.data 23 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.inst 5 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.data 25 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst 4 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.data 42 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 3 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu2.data 23 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.inst 5 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.data 25 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.inst 4 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.data 42 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 73 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 33 # number of ReadReq MSHR misses
+system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 31 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 69 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 470 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 477 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data 737 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 1684 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 7 # number of SCUpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses::total 7 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 11840 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 30205 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data 52337 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 94382 # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1896 # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5837 # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 5560 # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total 13293 # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2409 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1737 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data 4825 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total 8971 # number of ReadSharedReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 1896 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 14249 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker 33 # number of demand (read+write) MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 66 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 483 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 474 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data 722 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 1679 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 11 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 11 # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data 11817 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 30097 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3.data 52401 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 94315 # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 1891 # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 5846 # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 5570 # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total 13307 # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2411 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data 1726 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3.data 4791 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total 8928 # number of ReadSharedReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 1891 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 14228 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker 31 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 5837 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 31942 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.dtb.walker 69 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst 5560 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data 57162 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 116749 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 1896 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 14249 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker 33 # number of overall MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 5846 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data 31823 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.dtb.walker 66 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst 5570 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data 57192 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 116648 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 1891 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 14228 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker 31 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 5837 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 31942 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.dtb.walker 69 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst 5560 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data 57162 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 116749 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data 4113 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data 6742 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3.data 7559 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total 18414 # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3215 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data 5150 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3.data 6001 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total 14366 # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data 7328 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data 11892 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3.data 13560 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total 32780 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2481000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 72500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 5582000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 8135500 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 9755000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9901500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 15296000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 34952500 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 247500 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 247500 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 797090000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 2000773000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 3753918000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 6551781000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 136114500 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 416910500 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 402899000 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total 955924000 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 171319500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 126899000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 371197500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 669416000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 136114500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 968409500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2481000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 72500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 416910500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 2127672000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 5582000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst 402899000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data 4125115500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 8185256500 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 136114500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 968409500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2481000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 72500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 416910500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 2127672000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 5582000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst 402899000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data 4125115500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 8185256500 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 658270500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1229145000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1435515500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 3322931000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 509348000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 919708500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1131292500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 2560349000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1167618500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2148853500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data 2566808000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 5883280000 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002492 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000860 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003288 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.002120 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.987395 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.981481 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.972296 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.601643 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.411765 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.388889 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.358592 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.535018 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.543005 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.318233 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012194 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010209 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006718 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.035185 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.019003 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.032623 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016712 # mshr miss rate for ReadSharedReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.140405 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002492 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000860 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012194 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.216023 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003288 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010209 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data 0.233995 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.040812 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009003 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.140405 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002492 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000860 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012194 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.216023 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003288 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010209 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data 0.233995 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.040812 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75181.818182 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 72500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 80898.550725 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 78985.436893 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20755.319149 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20757.861635 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20754.409769 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20755.641330 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 35357.142857 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 35357.142857 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67321.790541 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66239.794736 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 71725.891816 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 69417.696171 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71790.348101 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 71425.475415 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72463.848921 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71911.833296 # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 71116.438356 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73056.419113 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 76932.124352 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74619.997771 # average ReadSharedReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71790.348101 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67963.330760 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75181.818182 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 72500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 71425.475415 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66610.481498 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 80898.550725 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72463.848921 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72165.345859 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 70109.863896 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71790.348101 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67963.330760 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75181.818182 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 72500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71425.475415 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66610.481498 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 80898.550725 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72463.848921 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72165.345859 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 70109.863896 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 160046.316557 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 182311.628597 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 189908.122768 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180456.772021 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158428.615863 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178584.174757 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 188517.330445 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178222.817764 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159336.585699 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 180697.401615 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 189292.625369 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 179477.730323 # average overall mshr uncacheable latency
+system.l2c.overall_mshr_misses::cpu2.inst 5846 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data 31823 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.dtb.walker 66 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst 5570 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data 57192 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 116648 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 4098 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data 6759 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu3.data 7555 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total 18412 # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 3203 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data 5165 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3.data 5997 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total 14365 # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 7301 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data 11924 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3.data 13552 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total 32777 # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 2310000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 73000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 5051000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 7434000 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 10024500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9843000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 14997500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 34865000 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 331000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 331000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 801174500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1990655500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 3770693000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 6562523000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 135550000 # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 418188000 # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 403211000 # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total 956949000 # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 173826000 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 124796000 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 367209500 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total 665831500 # number of ReadSharedReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 135550000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 975000500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 2310000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 73000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 418188000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 2115451500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 5051000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst 403211000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data 4137902500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 8192737500 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 135550000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 975000500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 2310000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 73000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 418188000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 2115451500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 5051000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst 403211000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data 4137902500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 8192737500 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 655228000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1232598000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1434609000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 3322435000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 506558500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 922952500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1130501000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 2560012000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1161786500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2155550500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data 2565110000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 5882447000 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002335 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000827 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003013 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.001921 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.987730 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985447 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.966533 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.600716 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.523810 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.523810 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.356320 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.533578 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.544975 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.318020 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.008966 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012238 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010246 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006731 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.035104 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.018815 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.032448 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.016611 # mshr miss rate for ReadSharedReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008966 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.139701 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002335 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000827 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012238 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.214814 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003013 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010246 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data 0.234582 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.040757 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008966 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.139701 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002335 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000827 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012238 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.214814 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003013 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010246 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data 0.234582 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.040757 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74516.129032 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 73000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 76530.303030 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 75857.142857 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20754.658385 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20765.822785 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20772.160665 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20765.336510 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 30090.909091 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 30090.909091 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67798.468308 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66141.326378 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 71958.416824 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 69580.904416 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71681.649921 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 71534.040369 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72389.766607 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71913.203577 # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72097.055164 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72303.592121 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 76645.689835 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74577.900986 # average ReadSharedReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71681.649921 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68526.883610 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74516.129032 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 73000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 71534.040369 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66475.552274 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 76530.303030 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72389.766607 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72351.071828 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 70234.701838 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71681.649921 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68526.883610 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74516.129032 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 73000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 71534.040369 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66475.552274 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 76530.303030 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72389.766607 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72351.071828 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 70234.701838 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 159889.702294 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 182363.959166 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 189888.682991 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180449.435151 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 158151.264440 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 178693.610842 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 188511.088878 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178211.764706 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 159127.037392 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 180774.111037 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 189279.073200 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 179468.743326 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.membus.trans_dist::ReadReq 40114 # Transaction distribution
-system.membus.trans_dist::ReadResp 75574 # Transaction distribution
+system.membus.trans_dist::ReadResp 75602 # Transaction distribution
system.membus.trans_dist::WriteReq 27565 # Transaction distribution
system.membus.trans_dist::WriteResp 27565 # Transaction distribution
-system.membus.trans_dist::Writeback 129170 # Transaction distribution
-system.membus.trans_dist::CleanEvict 8408 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4530 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4537 # Transaction distribution
-system.membus.trans_dist::ReadExReq 135995 # Transaction distribution
-system.membus.trans_dist::ReadExResp 135995 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 35460 # Transaction distribution
+system.membus.trans_dist::Writeback 128874 # Transaction distribution
+system.membus.trans_dist::CleanEvict 8637 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4529 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 11 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4540 # Transaction distribution
+system.membus.trans_dist::ReadExReq 135912 # Transaction distribution
+system.membus.trans_dist::ReadExResp 135912 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 35488 # Transaction distribution
system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution
system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480552 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 588004 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480381 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 587833 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109028 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 109028 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 697032 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 696861 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16952892 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 17116017 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16930428 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17093553 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19437617 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19415153 # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops 336 # Total snoops (count)
-system.membus.snoop_fanout::samples 417611 # Request fanout histogram
+system.membus.snoop_fanout::samples 417491 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 417611 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 417491 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 417611 # Request fanout histogram
-system.membus.reqLayer0.occupancy 56684000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 417491 # Request fanout histogram
+system.membus.reqLayer0.occupancy 56695500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 698000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 701000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 502688198 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 501323202 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 664974257 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 664397755 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 25114094 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 25144064 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 112988 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2628707 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 112246 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2626935 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 762046 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 2097370 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2799 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 18 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2817 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 296581 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 296581 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 1978788 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 536947 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 762585 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 2095941 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2795 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 296569 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296569 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 1977107 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 537598 # Transaction distribution
system.toL2Bus.trans_dist::InvalidateReq 13984 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5930770 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2618508 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 27177 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 101121 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 8677576 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126672504 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97797817 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 44504 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 177192 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 224692017 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 129673 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 5878617 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.031442 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.174509 # Request fanout histogram
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5926014 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2620361 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26770 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102262 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 8675407 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126565496 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97893497 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 45160 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 182440 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 224686593 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 127382 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 5875721 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.031320 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.174182 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 5693781 96.86% 96.86% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 184836 3.14% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 5691691 96.87% 96.87% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 184030 3.13% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 5878617 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2191894997 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 5875721 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2190361997 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.snoopLayer0.occupancy 178500 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 1851402273 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 1848817301 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 767013811 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 767245312 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 11591991 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 11020987 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 48212755 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 48078267 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
WARNING: Bank is already active!
Command: 0, Timestamp: 8760, Bank: 1
WARNING: Bank is not active!
-Command: 1, Timestamp: 5114, Bank: 5
+Command: 1, Timestamp: 5113, Bank: 5
WARNING: Bank is already active!
-Command: 0, Timestamp: 8083, Bank: 5
+Command: 0, Timestamp: 8082, Bank: 5
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 11235, Bank: 0
+Command: 0, Timestamp: 9156, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9340, Bank: 4
-WARNING: Bank is already active!
-Command: 0, Timestamp: 12338, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6589, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7558, Bank: 4
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10171, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7012, Bank: 7
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10303, Bank: 6
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 6
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8446, Bank: 6
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7635, Bank: 2
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10805, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10011, Bank: 1
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11449, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6626, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 9676, Bank: 5
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10242, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10403, Bank: 7
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11427, Bank: 7
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9128, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: Bank is already active!
-Command: 0, Timestamp: 8447, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 7453, Bank: 0
+Command: 0, Timestamp: 9256, Bank: 6
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10632, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11488, Bank: 1
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6826, Bank: 1
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7179, Bank: 6
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8996, Bank: 7
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11485, Bank: 4
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 9421, Bank: 2
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 4
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10203, Bank: 6
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8184, Bank: 5
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6448, Bank: 2
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6813, Bank: 1
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7188, Bank: 5
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7000, Bank: 1
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7487, Bank: 6
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10743, Bank: 3
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8640, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10536, Bank: 5
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11000, Bank: 4
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7339, Bank: 7
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 12368, Bank: 3
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8175, Bank: 5
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10565, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 10659, Bank: 2
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 7794, Bank: 5
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10622, Bank: 2
+WARNING: Bank is already active!
+Command: 0, Timestamp: 8145, Bank: 1
+WARNING: Bank is already active!
+Command: 0, Timestamp: 6448, Bank: 7
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
WARNING: One or more banks are active! REF requires all banks to be precharged.
Command: 4, Timestamp: 12458, Bank: 0
WARNING: One or more banks are active! REF requires all banks to be precharged.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10803, Bank: 6
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jul 29 2015 17:36:13
-gem5 started Jul 29 2015 18:34:05
+gem5 compiled Jul 31 2015 14:34:49
+gem5 started Jul 31 2015 14:34:58
gem5 executing on e104799-lin
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full -re /work/gem5/outgoing/gem5_3/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview64-switcheroo-full
---------- Begin Simulation Statistics ----------
-sim_seconds 51.276915 # Number of seconds simulated
-sim_ticks 51276914665000 # Number of ticks simulated
-final_tick 51276914665000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 51.316635 # Number of seconds simulated
+sim_ticks 51316634750000 # Number of ticks simulated
+final_tick 51316634750000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 268578 # Simulator instruction rate (inst/s)
-host_op_rate 315601 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 16108564651 # Simulator tick rate (ticks/s)
-host_mem_usage 678484 # Number of bytes of host memory used
-host_seconds 3183.21 # Real time elapsed on the host
-sim_insts 854941205 # Number of instructions simulated
-sim_ops 1004625181 # Number of ops (including micro ops) simulated
+host_inst_rate 555955 # Simulator instruction rate (inst/s)
+host_op_rate 653275 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 33346498264 # Simulator tick rate (ticks/s)
+host_mem_usage 678992 # Number of bytes of host memory used
+host_seconds 1538.89 # Real time elapsed on the host
+sim_insts 855554018 # Number of instructions simulated
+sim_ops 1005318688 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::cpu0.dtb.walker 83328 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 90048 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 2407092 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 43660040 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 20288 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 19392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 699200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 6175552 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.dtb.walker 32448 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.itb.walker 28928 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 1537920 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 8615616 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.dtb.walker 64768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.itb.walker 60352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.inst 1793920 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu3.data 16163456 # Number of bytes read from this memory
-system.physmem.bytes_read::realview.ide 420032 # Number of bytes read from this memory
-system.physmem.bytes_read::total 81872380 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 2407092 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 699200 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 1537920 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu3.inst 1793920 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 6438132 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 69681088 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu0.dtb.walker 86272 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 87040 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 2475252 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 44191944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 26688 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 26112 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 701824 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 6588352 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.dtb.walker 27264 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.itb.walker 23232 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 1769600 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 8688000 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.dtb.walker 64576 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.itb.walker 58944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.inst 1797376 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3.data 16165440 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 417344 # Number of bytes read from this memory
+system.physmem.bytes_read::total 83195260 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 2475252 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 701824 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu2.inst 1769600 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu3.inst 1797376 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 6744052 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 70299712 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 20580 # Number of bytes written to this memory
-system.physmem.bytes_written::total 69701668 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.dtb.walker 1302 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 1407 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 78018 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 682201 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 317 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 303 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 10925 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 96493 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.dtb.walker 507 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.itb.walker 452 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 24030 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 134619 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.dtb.walker 1012 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.itb.walker 943 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.inst 28030 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu3.data 252554 # Number of read requests responded to by this memory
-system.physmem.num_reads::realview.ide 6563 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 1319676 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 1088767 # Number of write requests responded to by this memory
+system.physmem.bytes_written::total 70320292 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.dtb.walker 1348 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 1360 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 79083 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 690512 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 417 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 408 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 10966 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 102943 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.dtb.walker 426 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.itb.walker 363 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 27650 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 135750 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.dtb.walker 1009 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.itb.walker 921 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.inst 28084 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3.data 252585 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 6521 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 1340346 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 1098433 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 2573 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 1091340 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.dtb.walker 1625 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 1756 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 46943 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 851456 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 396 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 378 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 13636 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 120435 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.dtb.walker 633 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.itb.walker 564 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 29992 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 168021 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.dtb.walker 1263 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.itb.walker 1177 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.inst 34985 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu3.data 315219 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::realview.ide 8191 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1596671 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 46943 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 13636 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 29992 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu3.inst 34985 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 125556 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1358917 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 1101006 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.dtb.walker 1681 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 1696 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 48235 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 861162 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 520 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 509 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 13676 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 128386 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.dtb.walker 531 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.itb.walker 453 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 34484 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 169302 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.dtb.walker 1258 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.itb.walker 1149 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.inst 35025 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3.data 315014 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 8133 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 1621214 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 48235 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 13676 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 34484 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu3.inst 35025 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 131420 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1369921 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 401 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1359319 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1358917 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 1625 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 1756 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 46943 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 851857 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 396 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 378 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 13636 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 120435 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.dtb.walker 633 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.itb.walker 564 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 29992 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 168021 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.dtb.walker 1263 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.itb.walker 1177 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.inst 34985 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu3.data 315219 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 8191 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 2955990 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 550245 # Number of read requests accepted
-system.physmem.writeReqs 481237 # Number of write requests accepted
-system.physmem.readBursts 550245 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 481237 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 35190464 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 25216 # Total number of bytes read from write queue
-system.physmem.bytesWritten 30797568 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 35215680 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 30799168 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 394 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::total 1370322 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1369921 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 1681 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 1696 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 48235 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 861563 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 520 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 509 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 13676 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 128386 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.dtb.walker 531 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.itb.walker 453 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.inst 34484 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 169302 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.dtb.walker 1258 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.itb.walker 1149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.inst 35025 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3.data 315014 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 8133 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 2991536 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 565119 # Number of read requests accepted
+system.physmem.writeReqs 485303 # Number of write requests accepted
+system.physmem.readBursts 565119 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 485303 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 36124864 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 42752 # Total number of bytes read from write queue
+system.physmem.bytesWritten 31057472 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 36167616 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 31059392 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 668 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 68304 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 35436 # Per bank write bursts
-system.physmem.perBankRdBursts::1 39868 # Per bank write bursts
-system.physmem.perBankRdBursts::2 34215 # Per bank write bursts
-system.physmem.perBankRdBursts::3 34743 # Per bank write bursts
-system.physmem.perBankRdBursts::4 34056 # Per bank write bursts
-system.physmem.perBankRdBursts::5 38097 # Per bank write bursts
-system.physmem.perBankRdBursts::6 32100 # Per bank write bursts
-system.physmem.perBankRdBursts::7 33790 # Per bank write bursts
-system.physmem.perBankRdBursts::8 31750 # Per bank write bursts
-system.physmem.perBankRdBursts::9 37588 # Per bank write bursts
-system.physmem.perBankRdBursts::10 34493 # Per bank write bursts
-system.physmem.perBankRdBursts::11 35548 # Per bank write bursts
-system.physmem.perBankRdBursts::12 32409 # Per bank write bursts
-system.physmem.perBankRdBursts::13 32208 # Per bank write bursts
-system.physmem.perBankRdBursts::14 31335 # Per bank write bursts
-system.physmem.perBankRdBursts::15 32215 # Per bank write bursts
-system.physmem.perBankWrBursts::0 29077 # Per bank write bursts
-system.physmem.perBankWrBursts::1 32864 # Per bank write bursts
-system.physmem.perBankWrBursts::2 29906 # Per bank write bursts
-system.physmem.perBankWrBursts::3 31279 # Per bank write bursts
-system.physmem.perBankWrBursts::4 30178 # Per bank write bursts
-system.physmem.perBankWrBursts::5 33497 # Per bank write bursts
-system.physmem.perBankWrBursts::6 28885 # Per bank write bursts
-system.physmem.perBankWrBursts::7 30667 # Per bank write bursts
-system.physmem.perBankWrBursts::8 29490 # Per bank write bursts
-system.physmem.perBankWrBursts::9 32863 # Per bank write bursts
-system.physmem.perBankWrBursts::10 29440 # Per bank write bursts
-system.physmem.perBankWrBursts::11 30986 # Per bank write bursts
-system.physmem.perBankWrBursts::12 28208 # Per bank write bursts
-system.physmem.perBankWrBursts::13 28238 # Per bank write bursts
-system.physmem.perBankWrBursts::14 27304 # Per bank write bursts
-system.physmem.perBankWrBursts::15 28330 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 65964 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 37092 # Per bank write bursts
+system.physmem.perBankRdBursts::1 38221 # Per bank write bursts
+system.physmem.perBankRdBursts::2 34232 # Per bank write bursts
+system.physmem.perBankRdBursts::3 34199 # Per bank write bursts
+system.physmem.perBankRdBursts::4 32555 # Per bank write bursts
+system.physmem.perBankRdBursts::5 36931 # Per bank write bursts
+system.physmem.perBankRdBursts::6 31211 # Per bank write bursts
+system.physmem.perBankRdBursts::7 33972 # Per bank write bursts
+system.physmem.perBankRdBursts::8 32403 # Per bank write bursts
+system.physmem.perBankRdBursts::9 38255 # Per bank write bursts
+system.physmem.perBankRdBursts::10 35917 # Per bank write bursts
+system.physmem.perBankRdBursts::11 41761 # Per bank write bursts
+system.physmem.perBankRdBursts::12 35252 # Per bank write bursts
+system.physmem.perBankRdBursts::13 36878 # Per bank write bursts
+system.physmem.perBankRdBursts::14 32220 # Per bank write bursts
+system.physmem.perBankRdBursts::15 33352 # Per bank write bursts
+system.physmem.perBankWrBursts::0 29650 # Per bank write bursts
+system.physmem.perBankWrBursts::1 31742 # Per bank write bursts
+system.physmem.perBankWrBursts::2 28889 # Per bank write bursts
+system.physmem.perBankWrBursts::3 30829 # Per bank write bursts
+system.physmem.perBankWrBursts::4 29399 # Per bank write bursts
+system.physmem.perBankWrBursts::5 32279 # Per bank write bursts
+system.physmem.perBankWrBursts::6 27374 # Per bank write bursts
+system.physmem.perBankWrBursts::7 30609 # Per bank write bursts
+system.physmem.perBankWrBursts::8 28675 # Per bank write bursts
+system.physmem.perBankWrBursts::9 32426 # Per bank write bursts
+system.physmem.perBankWrBursts::10 29991 # Per bank write bursts
+system.physmem.perBankWrBursts::11 34263 # Per bank write bursts
+system.physmem.perBankWrBursts::12 30290 # Per bank write bursts
+system.physmem.perBankWrBursts::13 31646 # Per bank write bursts
+system.physmem.perBankWrBursts::14 28165 # Per bank write bursts
+system.physmem.perBankWrBursts::15 29046 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 12 # Number of times write queue was full causing retry
-system.physmem.totGap 51275914443000 # Total gap between requests
+system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
+system.physmem.totGap 51315634470500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 550245 # Read request sizes (log2)
+system.physmem.readPktSize::6 565119 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 481237 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 388368 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 101483 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 36821 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 22989 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 129 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 19 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 11 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 485303 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 399408 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 101730 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 37111 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 23215 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 366 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 278 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 258 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 310 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 421 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 535 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 237 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 100 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 87 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 82 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 69 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 65 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 51 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::18 46 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 24 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::20 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 588 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 572 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 570 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 568 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 569 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 567 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 562 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 558 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 556 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 558 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 557 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 557 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 551 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 553 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 549 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 7785 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 8646 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 19148 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 23177 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 26333 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 27904 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 27768 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 28936 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 29500 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 30869 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 30606 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 30707 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 29539 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 30452 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32548 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 28468 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 28582 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 27212 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 466 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 291 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 337 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 261 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 228 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 210 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 235 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 258 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 175 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 176 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 126 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 156 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 182 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 117 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 118 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 143 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 140 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 103 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 85 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 83 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 586 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 574 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 574 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 571 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 568 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 566 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 566 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 563 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 562 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 564 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 560 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 559 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 552 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 551 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 546 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 7847 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 8616 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 19482 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 23454 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 26479 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 28098 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 28044 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 29307 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 29679 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 31078 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 30832 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 30867 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 29853 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 30684 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 32884 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 28794 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 28945 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 27599 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::33 433 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::34 285 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 342 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 241 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 209 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 226 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 192 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::41 269 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 186 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::43 136 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::44 146 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 134 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 160 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 136 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 124 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 107 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 81 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 127 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 89 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 89 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 58 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 115 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 47 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 45 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 38 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 22 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 13 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 35 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 273820 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 240.988445 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 145.225402 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 282.507263 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 125281 45.75% 45.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 68336 24.96% 70.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 24972 9.12% 79.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 12598 4.60% 84.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 9315 3.40% 87.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 5687 2.08% 89.91% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 4750 1.73% 91.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3875 1.42% 93.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 19006 6.94% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 273820 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 27019 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 20.349051 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 10.037322 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-15 3255 12.05% 12.05% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::16-31 21302 78.84% 90.89% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::32-47 1883 6.97% 97.86% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::48-63 429 1.59% 99.44% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::64-79 82 0.30% 99.75% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::80-95 50 0.19% 99.93% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::96-111 5 0.02% 99.95% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::112-127 5 0.02% 99.97% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::128-143 2 0.01% 99.98% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::144-159 2 0.01% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::160-175 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::208-223 1 0.00% 99.99% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::240-255 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::336-351 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 27019 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 27019 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 17.810134 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 17.198144 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 7.395128 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3 20 0.07% 0.07% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 13 0.05% 0.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11 7 0.03% 0.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 44 0.16% 0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 25225 93.36% 93.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 422 1.56% 95.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 332 1.23% 96.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 185 0.68% 97.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 112 0.41% 97.56% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 204 0.76% 98.32% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 76 0.28% 98.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 16 0.06% 98.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 19 0.07% 98.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 18 0.07% 98.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 23 0.09% 98.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 14 0.05% 98.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 191 0.71% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 20 0.07% 99.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 23 0.09% 99.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 16 0.06% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 2 0.01% 99.86% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.00% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 1 0.00% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 2 0.01% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 2 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 1 0.00% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 2 0.01% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 2 0.01% 99.90% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 14 0.05% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 1 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::136-139 1 0.00% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrQLenPdf::58 44 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 33 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 25 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 8 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 6 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 278814 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 240.955476 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 145.236301 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 282.316846 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 127586 45.76% 45.76% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 69517 24.93% 70.69% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 25415 9.12% 79.81% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 12865 4.61% 84.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 9508 3.41% 87.83% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 5843 2.10% 89.93% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 4935 1.77% 91.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 3869 1.39% 93.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 19276 6.91% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 278814 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 27347 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 20.639193 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 13.469110 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-31 24770 90.58% 90.58% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::32-63 2374 8.68% 99.26% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::64-95 169 0.62% 99.88% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::96-127 20 0.07% 99.95% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::128-159 3 0.01% 99.96% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::160-191 2 0.01% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::192-223 2 0.01% 99.97% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::224-255 2 0.01% 99.98% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::256-287 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::320-351 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::704-735 1 0.00% 99.99% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::736-767 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::928-959 1 0.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::total 27347 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 27347 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 17.745018 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 17.170209 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 7.144032 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 15 0.05% 0.05% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 12 0.04% 0.10% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 8 0.03% 0.13% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 33 0.12% 0.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 25607 93.64% 93.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 450 1.65% 95.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 306 1.12% 96.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 171 0.63% 97.28% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 124 0.45% 97.73% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 194 0.71% 98.44% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 52 0.19% 98.63% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 11 0.04% 98.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 30 0.11% 98.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 23 0.08% 98.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 22 0.08% 98.94% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 11 0.04% 98.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 180 0.66% 99.64% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 15 0.05% 99.70% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 25 0.09% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 19 0.07% 99.86% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 6 0.02% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 2 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.01% 99.89% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 2 0.01% 99.90% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 2 0.01% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 1 0.00% 99.91% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 1 0.00% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 14 0.05% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 1 0.00% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::152-155 2 0.01% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::164-167 5 0.02% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::176-179 2 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 27019 # Writes before turning the bus around for reads
-system.physmem.totQLat 11443674557 # Total ticks spent queuing
-system.physmem.totMemAccLat 21753380807 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2749255000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 20812.32 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::148-151 3 0.01% 99.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::156-159 1 0.00% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::164-167 3 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::204-207 1 0.00% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 27347 # Writes before turning the bus around for reads
+system.physmem.totQLat 11691794846 # Total ticks spent queuing
+system.physmem.totMemAccLat 22275251096 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 2822255000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 20713.57 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 39562.32 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 0.69 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.60 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 0.69 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.60 # Average system write bandwidth in MiByte/s
+system.physmem.avgMemAccLat 39463.57 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 0.70 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgWrBW 0.61 # Average achieved write bandwidth in MiByte/s
+system.physmem.avgRdBWSys 0.70 # Average system read bandwidth in MiByte/s
+system.physmem.avgWrBWSys 0.61 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.01 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 6.72 # Average write queue length when enqueuing
-system.physmem.readRowHits 421327 # Number of row buffer hits during reads
-system.physmem.writeRowHits 335914 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 76.63 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 69.80 # Row buffer hit rate for writes
-system.physmem.avgGap 49710915.40 # Average gap between requests
+system.physmem.avgWrQLen 8.89 # Average write queue length when enqueuing
+system.physmem.readRowHits 432443 # Number of row buffer hits during reads
+system.physmem.writeRowHits 338466 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 76.61 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 69.74 # Row buffer hit rate for writes
+system.physmem.avgGap 48852398.82 # Average gap between requests
system.physmem.pageHitRate 73.44 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 1064213640 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 579096375 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2201979000 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 1596367440 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 3310527770160 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 1178433187650 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 30013431943500 # Energy for precharge background per rank (pJ)
-system.physmem_0.totalEnergy 34507834557765 # Total energy per rank (pJ)
-system.physmem_0.averagePower 666.879372 # Core power per rank (mW)
-system.physmem_0.memoryStateTime::IDLE 48871742574250 # Time in different power states
-system.physmem_0.memoryStateTime::REF 1692498860000 # Time in different power states
+system.physmem_0.actEnergy 1049600160 # Energy for activate commands per rank (pJ)
+system.physmem_0.preEnergy 571056750 # Energy for precharge commands per rank (pJ)
+system.physmem_0.readEnergy 2171551200 # Energy for read commands per rank (pJ)
+system.physmem_0.writeEnergy 1560196080 # Energy for write commands per rank (pJ)
+system.physmem_0.refreshEnergy 3312990217680 # Energy for refresh commands per rank (pJ)
+system.physmem_0.actBackEnergy 1178995763115 # Energy for active background per rank (pJ)
+system.physmem_0.preBackEnergy 29844954866250 # Energy for precharge background per rank (pJ)
+system.physmem_0.totalEnergy 34342293251235 # Total energy per rank (pJ)
+system.physmem_0.averagePower 667.290653 # Core power per rank (mW)
+system.physmem_0.memoryStateTime::IDLE 48908598729306 # Time in different power states
+system.physmem_0.memoryStateTime::REF 1693757780000 # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 121731845500 # Time in different power states
+system.physmem_0.memoryStateTime::ACT 121315217444 # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem_1.actEnergy 1005865560 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 547383375 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 2086788600 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 1521886320 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 3310527770160 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 1173650278320 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 29856307058250 # Energy for precharge background per rank (pJ)
-system.physmem_1.totalEnergy 34345647030585 # Total energy per rank (pJ)
-system.physmem_1.averagePower 667.211846 # Core power per rank (mW)
-system.physmem_1.memoryStateTime::IDLE 48878835578992 # Time in different power states
-system.physmem_1.memoryStateTime::REF 1692498860000 # Time in different power states
+system.physmem_1.actEnergy 1058233680 # Energy for activate commands per rank (pJ)
+system.physmem_1.preEnergy 575746875 # Energy for precharge commands per rank (pJ)
+system.physmem_1.readEnergy 2231096400 # Energy for read commands per rank (pJ)
+system.physmem_1.writeEnergy 1584372960 # Energy for write commands per rank (pJ)
+system.physmem_1.refreshEnergy 3312990217680 # Energy for refresh commands per rank (pJ)
+system.physmem_1.actBackEnergy 1180768405545 # Energy for active background per rank (pJ)
+system.physmem_1.preBackEnergy 30633804913500 # Energy for precharge background per rank (pJ)
+system.physmem_1.totalEnergy 35133012986640 # Total energy per rank (pJ)
+system.physmem_1.averagePower 665.617184 # Core power per rank (mW)
+system.physmem_1.memoryStateTime::IDLE 48905982752444 # Time in different power states
+system.physmem_1.memoryStateTime::REF 1693757780000 # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 114595771758 # Time in different power states
+system.physmem_1.memoryStateTime::ACT 123922534306 # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.dtb.walker.walks 90556 # Table walker walks requested
-system.cpu0.dtb.walker.walksLong 90556 # Table walker walks initiated with long descriptors
-system.cpu0.dtb.walker.walkWaitTime::samples 90556 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::0 90556 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walkWaitTime::total 90556 # Table walker wait (enqueue to first request) latency
-system.cpu0.dtb.walker.walksPending::samples 391820965788 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::mean 1.505629 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::0 -198115997962 -50.56% -50.56% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::1 589936963750 150.56% 100.00% # Table walker pending requests distribution
-system.cpu0.dtb.walker.walksPending::total 391820965788 # Table walker pending requests distribution
-system.cpu0.dtb.walker.walkPageSizes::4K 66622 84.81% 84.81% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::2M 11928 15.19% 100.00% # Table walker page sizes translated
-system.cpu0.dtb.walker.walkPageSizes::total 78550 # Table walker page sizes translated
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 90556 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walks 91446 # Table walker walks requested
+system.cpu0.dtb.walker.walksLong 91446 # Table walker walks initiated with long descriptors
+system.cpu0.dtb.walker.walkWaitTime::samples 91446 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::0 91446 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walkWaitTime::total 91446 # Table walker wait (enqueue to first request) latency
+system.cpu0.dtb.walker.walksPending::samples 388607264328 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::mean 1.523233 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::0 -203332229172 -52.32% -52.32% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::1 591939493500 152.32% 100.00% # Table walker pending requests distribution
+system.cpu0.dtb.walker.walksPending::total 388607264328 # Table walker pending requests distribution
+system.cpu0.dtb.walker.walkPageSizes::4K 66855 84.61% 84.61% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::2M 12161 15.39% 100.00% # Table walker page sizes translated
+system.cpu0.dtb.walker.walkPageSizes::total 79016 # Table walker page sizes translated
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 91446 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 90556 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 78550 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 91446 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 79016 # Table walker requests started/completed, data/inst
system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 78550 # Table walker requests started/completed, data/inst
-system.cpu0.dtb.walker.walkRequestOrigin::total 169106 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 79016 # Table walker requests started/completed, data/inst
+system.cpu0.dtb.walker.walkRequestOrigin::total 170462 # Table walker requests started/completed, data/inst
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 64673225 # DTB read hits
-system.cpu0.dtb.read_misses 68448 # DTB read misses
-system.cpu0.dtb.write_hits 58639149 # DTB write hits
-system.cpu0.dtb.write_misses 22108 # DTB write misses
-system.cpu0.dtb.flush_tlb 1188 # Number of times complete TLB was flushed
+system.cpu0.dtb.read_hits 64637193 # DTB read hits
+system.cpu0.dtb.read_misses 69043 # DTB read misses
+system.cpu0.dtb.write_hits 58569418 # DTB write hits
+system.cpu0.dtb.write_misses 22403 # DTB write misses
+system.cpu0.dtb.flush_tlb 1193 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 15858 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 413 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 41832 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_tlb_mva_asid 16284 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.dtb.flush_tlb_asid 407 # Number of times TLB was flushed by ASID
+system.cpu0.dtb.flush_entries 42446 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 2761 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 2875 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 7632 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 64741673 # DTB read accesses
-system.cpu0.dtb.write_accesses 58661257 # DTB write accesses
+system.cpu0.dtb.perms_faults 7756 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 64706236 # DTB read accesses
+system.cpu0.dtb.write_accesses 58591821 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 123312374 # DTB hits
-system.cpu0.dtb.misses 90556 # DTB misses
-system.cpu0.dtb.accesses 123402930 # DTB accesses
+system.cpu0.dtb.hits 123206611 # DTB hits
+system.cpu0.dtb.misses 91446 # DTB misses
+system.cpu0.dtb.accesses 123298057 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.walker.walks 54313 # Table walker walks requested
-system.cpu0.itb.walker.walksLong 54313 # Table walker walks initiated with long descriptors
-system.cpu0.itb.walker.walkWaitTime::samples 54313 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::0 54313 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walkWaitTime::total 54313 # Table walker wait (enqueue to first request) latency
-system.cpu0.itb.walker.walksPending::samples 391820965788 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::mean 1.505731 # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::0 -198155892462 -50.57% -50.57% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::1 589976858250 150.57% 100.00% # Table walker pending requests distribution
-system.cpu0.itb.walker.walksPending::total 391820965788 # Table walker pending requests distribution
-system.cpu0.itb.walker.walkPageSizes::4K 47491 95.01% 95.01% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::2M 2494 4.99% 100.00% # Table walker page sizes translated
-system.cpu0.itb.walker.walkPageSizes::total 49985 # Table walker page sizes translated
+system.cpu0.itb.walker.walks 53719 # Table walker walks requested
+system.cpu0.itb.walker.walksLong 53719 # Table walker walks initiated with long descriptors
+system.cpu0.itb.walker.walkWaitTime::samples 53719 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::0 53719 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walkWaitTime::total 53719 # Table walker wait (enqueue to first request) latency
+system.cpu0.itb.walker.walksPending::samples 388607264328 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::mean 1.523329 # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::0 -203369594172 -52.33% -52.33% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::1 591976858500 152.33% 100.00% # Table walker pending requests distribution
+system.cpu0.itb.walker.walksPending::total 388607264328 # Table walker pending requests distribution
+system.cpu0.itb.walker.walkPageSizes::4K 46750 94.94% 94.94% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::2M 2490 5.06% 100.00% # Table walker page sizes translated
+system.cpu0.itb.walker.walkPageSizes::total 49240 # Table walker page sizes translated
system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 54313 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Requested::total 54313 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 53719 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Requested::total 53719 # Table walker requests started/completed, data/inst
system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49985 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49985 # Table walker requests started/completed, data/inst
-system.cpu0.itb.walker.walkRequestOrigin::total 104298 # Table walker requests started/completed, data/inst
-system.cpu0.itb.inst_hits 343634485 # ITB inst hits
-system.cpu0.itb.inst_misses 54313 # ITB inst misses
+system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 49240 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin_Completed::total 49240 # Table walker requests started/completed, data/inst
+system.cpu0.itb.walker.walkRequestOrigin::total 102959 # Table walker requests started/completed, data/inst
+system.cpu0.itb.inst_hits 343542724 # ITB inst hits
+system.cpu0.itb.inst_misses 53719 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 1188 # Number of times complete TLB was flushed
+system.cpu0.itb.flush_tlb 1193 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 15858 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 413 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 29675 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_tlb_mva_asid 16284 # Number of times TLB was flushed by MVA & ASID
+system.cpu0.itb.flush_tlb_asid 407 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 30063 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 343688798 # ITB inst accesses
-system.cpu0.itb.hits 343634485 # DTB hits
-system.cpu0.itb.misses 54313 # DTB misses
-system.cpu0.itb.accesses 343688798 # DTB accesses
-system.cpu0.numCycles 414612673 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 343596443 # ITB inst accesses
+system.cpu0.itb.hits 343542724 # DTB hits
+system.cpu0.itb.misses 53719 # DTB misses
+system.cpu0.itb.accesses 343596443 # DTB accesses
+system.cpu0.numCycles 414507923 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 343491459 # Number of instructions committed
-system.cpu0.committedOps 404038438 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 371064332 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 366662 # Number of float alu accesses
-system.cpu0.num_func_calls 20606328 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 52246055 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 371064332 # number of integer instructions
-system.cpu0.num_fp_insts 366662 # number of float instructions
-system.cpu0.num_int_register_reads 542308147 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 294610052 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 579925 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 335816 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 90131130 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 89914881 # number of times the CC registers were written
-system.cpu0.num_mem_refs 123386712 # number of memory refs
-system.cpu0.num_load_insts 64730993 # Number of load instructions
-system.cpu0.num_store_insts 58655719 # Number of store instructions
-system.cpu0.num_idle_cycles 404807579.503922 # Number of idle cycles
-system.cpu0.num_busy_cycles 9805093.496078 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.023649 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.976351 # Percentage of idle cycles
-system.cpu0.Branches 76646162 # Number of branches fetched
+system.cpu0.committedInsts 343392928 # Number of instructions committed
+system.cpu0.committedOps 403926056 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 371010641 # Number of integer alu accesses
+system.cpu0.num_fp_alu_accesses 350352 # Number of float alu accesses
+system.cpu0.num_func_calls 20655596 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 52208909 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 371010641 # number of integer instructions
+system.cpu0.num_fp_insts 350352 # number of float instructions
+system.cpu0.num_int_register_reads 542983655 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 294627893 # number of times the integer registers were written
+system.cpu0.num_fp_register_reads 558017 # number of times the floating registers were read
+system.cpu0.num_fp_register_writes 311708 # number of times the floating registers were written
+system.cpu0.num_cc_register_reads 89970579 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 89777589 # number of times the CC registers were written
+system.cpu0.num_mem_refs 123282310 # number of memory refs
+system.cpu0.num_load_insts 64695790 # Number of load instructions
+system.cpu0.num_store_insts 58586520 # Number of store instructions
+system.cpu0.num_idle_cycles 404635948.136490 # Number of idle cycles
+system.cpu0.num_busy_cycles 9871974.863510 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.023816 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.976184 # Percentage of idle cycles
+system.cpu0.Branches 76586966 # Number of branches fetched
system.cpu0.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 279922003 69.24% 69.24% # Class of executed instruction
-system.cpu0.op_class::IntMult 872785 0.22% 69.46% # Class of executed instruction
-system.cpu0.op_class::IntDiv 43154 0.01% 69.47% # Class of executed instruction
-system.cpu0.op_class::FloatAdd 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::FloatCmp 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::FloatCvt 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::FloatMult 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::FloatDiv 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::FloatSqrt 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdAdd 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdAlu 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdCmp 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdCvt 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdMisc 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatCvt 1 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.47% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 49919 0.01% 69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMult 0 0.00% 69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.48% # Class of executed instruction
-system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.48% # Class of executed instruction
-system.cpu0.op_class::MemRead 64730993 16.01% 85.49% # Class of executed instruction
-system.cpu0.op_class::MemWrite 58655719 14.51% 100.00% # Class of executed instruction
+system.cpu0.op_class::IntAlu 279907726 69.26% 69.26% # Class of executed instruction
+system.cpu0.op_class::IntMult 889275 0.22% 69.48% # Class of executed instruction
+system.cpu0.op_class::IntDiv 42026 0.01% 69.49% # Class of executed instruction
+system.cpu0.op_class::FloatAdd 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::FloatCmp 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::FloatCvt 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::FloatMult 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::FloatDiv 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::FloatSqrt 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdAdd 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdAddAcc 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdAlu 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdCmp 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdCvt 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdMisc 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdMult 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdMultAcc 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdShift 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdSqrt 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdFloatAlu 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCmp 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdFloatCvt 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.49% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 46880 0.01% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMult 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::SimdFloatSqrt 0 0.00% 69.50% # Class of executed instruction
+system.cpu0.op_class::MemRead 64695790 16.01% 85.50% # Class of executed instruction
+system.cpu0.op_class::MemWrite 58586520 14.50% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 404274574 # Class of executed instruction
+system.cpu0.op_class::total 404168217 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 16555 # number of quiesce instructions executed
-system.cpu0.dcache.tags.replacements 9760623 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 511.999693 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 295406617 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 9761135 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 30.263552 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 16558 # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements 9753179 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 511.999716 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 295582609 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 9753691 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 30.304693 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 33050500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.408382 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.358891 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu2.data 7.391492 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_blocks::cpu3.data 3.840928 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.967594 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010467 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu2.data 0.014437 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::cpu3.data 0.007502 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.786963 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu1.data 5.350548 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.889749 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_blocks::cpu3.data 3.972456 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970287 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu1.data 0.010450 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011503 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::cpu3.data 0.007759 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999999 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 166 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 316 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 29 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 1251530357 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 1251530357 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 60440714 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu1.data 19079891 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu2.data 26457743 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::cpu3.data 46030584 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 152008932 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 55470897 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu1.data 17632949 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu2.data 23585193 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::cpu3.data 38751939 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 135440978 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 163149 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu1.data 46374 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu2.data 80888 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu3.data 112448 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 402859 # number of SoftPFReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu0.data 132862 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44988 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu2.data 52244 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::cpu3.data 99564 # number of WriteLineReq hits
-system.cpu0.dcache.WriteLineReq_hits::total 329658 # number of WriteLineReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1435046 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 431760 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 583467 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 975735 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 3426008 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1528481 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu1.data 469205 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu2.data 629772 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1126896 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 3754354 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 115911611 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu1.data 36712840 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu2.data 50042936 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::cpu3.data 84782523 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 287449910 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 116074760 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu1.data 36759214 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu2.data 50123824 # number of overall hits
-system.cpu0.dcache.overall_hits::cpu3.data 84894971 # number of overall hits
-system.cpu0.dcache.overall_hits::total 287852769 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 2074038 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu1.data 622706 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu2.data 950512 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::cpu3.data 3520436 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 7167692 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 834575 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu1.data 257970 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu2.data 650618 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::cpu3.data 3386065 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 5129228 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 508589 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu1.data 146296 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu2.data 212076 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu3.data 322320 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 1189281 # number of SoftPFReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu0.data 666999 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu1.data 114735 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu2.data 152937 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::cpu3.data 292722 # number of WriteLineReq misses
-system.cpu0.dcache.WriteLineReq_misses::total 1227393 # number of WriteLineReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 94072 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 37658 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 46539 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 187643 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 365912 # number of LoadLockedReq misses
+system.cpu0.dcache.tags.tag_accesses 1252278840 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 1252278840 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 60369359 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu1.data 19140658 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu2.data 26830987 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::cpu3.data 45818234 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 152159238 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 55384084 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu1.data 17587575 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu2.data 23765695 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu3.data 38719665 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 135457019 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 164079 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu1.data 46225 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu2.data 81077 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu3.data 111985 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 403366 # number of SoftPFReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu0.data 132348 # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu1.data 44500 # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu2.data 54331 # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::cpu3.data 98773 # number of WriteLineReq hits
+system.cpu0.dcache.WriteLineReq_hits::total 329952 # number of WriteLineReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1446319 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 438478 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 586341 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 962737 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 3433875 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1538701 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu1.data 475697 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu2.data 636200 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu3.data 1104802 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 3755400 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 115753443 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu1.data 36728233 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu2.data 50596682 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu3.data 84537899 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 287616257 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 115917522 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu1.data 36774458 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu2.data 50677759 # number of overall hits
+system.cpu0.dcache.overall_hits::cpu3.data 84649884 # number of overall hits
+system.cpu0.dcache.overall_hits::total 288019623 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 2092041 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu1.data 624638 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu2.data 970441 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu3.data 3415331 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 7102451 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 840568 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu1.data 251537 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu2.data 625226 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu3.data 3495089 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 5212420 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 514907 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu1.data 141320 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu2.data 198621 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu3.data 334446 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 1189294 # number of SoftPFReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu0.data 668357 # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu1.data 105494 # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu2.data 155232 # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::cpu3.data 298331 # number of WriteLineReq misses
+system.cpu0.dcache.WriteLineReq_misses::total 1227414 # number of WriteLineReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 93062 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 37431 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 50097 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 180259 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 360849 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu3.data 4 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 2908613 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu1.data 880676 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu2.data 1601130 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::cpu3.data 6906501 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 12296920 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 3417202 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu1.data 1026972 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu2.data 1813206 # number of overall misses
-system.cpu0.dcache.overall_misses::cpu3.data 7228821 # number of overall misses
-system.cpu0.dcache.overall_misses::total 13486201 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9559498000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 14919986000 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 53204647500 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 77684131500 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6931134000 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17483945500 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 95592660029 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 120007739529 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 2732317500 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 4244347000 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 10498361311 # number of WriteLineReq miss cycles
-system.cpu0.dcache.WriteLineReq_miss_latency::total 17475025811 # number of WriteLineReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 520498500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 650995000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2326488500 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 3497982000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.demand_misses::cpu0.data 2932609 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu1.data 876175 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu2.data 1595667 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu3.data 6910420 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 12314871 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 3447516 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu1.data 1017495 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu2.data 1794288 # number of overall misses
+system.cpu0.dcache.overall_misses::cpu3.data 7244866 # number of overall misses
+system.cpu0.dcache.overall_misses::total 13504165 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 9754171500 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 15346689000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 52027511000 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 77128371500 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 6989966000 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 16964216500 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 96846252035 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 120800434535 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu1.data 2685222500 # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu2.data 4289017000 # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::cpu3.data 10724214307 # number of WriteLineReq miss cycles
+system.cpu0.dcache.WriteLineReq_miss_latency::total 17698453807 # number of WriteLineReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 525769500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 711390500 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 2241356000 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 3478516000 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 142500 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 142500 # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu1.data 16490632000 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu2.data 32403931500 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu3.data 148797307529 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 197691871029 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu1.data 16490632000 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu2.data 32403931500 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu3.data 148797307529 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 197691871029 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 62514752 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu1.data 19702597 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu2.data 27408255 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::cpu3.data 49551020 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 159176624 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 56305472 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu1.data 17890919 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu2.data 24235811 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu3.data 42138004 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 140570206 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 671738 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 192670 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 292964 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 434768 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 1592140 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 799861 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 159723 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 205181 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 392286 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.WriteLineReq_accesses::total 1557051 # number of WriteLineReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1529118 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 469418 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 630006 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1163378 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 3791920 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1528481 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 469205 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 629772 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1126900 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 3754358 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 118820224 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu1.data 37593516 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu2.data 51644066 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::cpu3.data 91689024 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 299746830 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 119491962 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu1.data 37786186 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu2.data 51937030 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu3.data 92123792 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 301338970 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033177 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031605 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.034680 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.071047 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.045030 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014822 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014419 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.026845 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.080357 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.036489 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.757124 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.759309 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.723898 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.741361 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.746970 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.833894 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.718337 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.745376 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.746195 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788281 # miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.061520 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.080223 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.073871 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.161292 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.096498 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_miss_latency::cpu1.data 16744137500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu2.data 32310905500 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu3.data 148873763035 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 197928806035 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu1.data 16744137500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu2.data 32310905500 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu3.data 148873763035 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 197928806035 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 62461400 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu1.data 19765296 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu2.data 27801428 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu3.data 49233565 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 159261689 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 56224652 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu1.data 17839112 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu2.data 24390921 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu3.data 42214754 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 140669439 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 678986 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 187545 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 279698 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu3.data 446431 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 1592660 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu0.data 800705 # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu1.data 149994 # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu2.data 209563 # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::cpu3.data 397104 # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.WriteLineReq_accesses::total 1557366 # number of WriteLineReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1539381 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 475909 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 636438 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu3.data 1142996 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 3794724 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1538701 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 475697 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 636200 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu3.data 1104806 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 3755404 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 118686052 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu1.data 37604408 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu2.data 52192349 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu3.data 91448319 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 299931128 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 119365038 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu1.data 37791953 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu2.data 52472047 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu3.data 91894750 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 301523788 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033493 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.031603 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.034906 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu3.data 0.069370 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.044596 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.014950 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.014100 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.025634 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu3.data 0.082793 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.037054 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.758347 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.753526 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.710127 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.749155 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.746734 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu0.data 0.834711 # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu1.data 0.703321 # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu2.data 0.740741 # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::cpu3.data 0.751267 # miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_miss_rate::total 0.788135 # miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.060454 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078652 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.078715 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.157707 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.095092 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000004 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000001 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024479 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023426 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu2.data 0.031003 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::cpu3.data 0.075325 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.041024 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028598 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu1.data 0.027179 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034912 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::cpu3.data 0.078469 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.044754 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15351.543104 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15696.788678 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15113.084715 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 10838.095652 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 26867.984649 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 26872.827834 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 28231.194625 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 23396.842474 # average WriteReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 23814.158714 # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 27752.257465 # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 35864.613220 # average WriteLineReq miss latency
-system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 14237.514644 # average WriteLineReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13821.724468 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13988.160468 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12398.482757 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9559.626358 # average LoadLockedReq miss latency
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.024709 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu1.data 0.023300 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu2.data 0.030573 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::cpu3.data 0.075566 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.041059 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028882 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026924 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu2.data 0.034195 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::cpu3.data 0.078839 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.044786 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15615.719024 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 15814.139139 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15233.519387 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 10859.402128 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 27789.017123 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 27132.935131 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 27709.237743 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 23175.499007 # average WriteReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu1.data 25453.793581 # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu2.data 27629.721965 # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::cpu3.data 35947.368215 # average WriteLineReq miss latency
+system.cpu0.dcache.WriteLineReq_avg_miss_latency::total 14419.302539 # average WriteLineReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14046.365312 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 14200.261493 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 12434.086509 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9639.810558 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 35625 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 35625 # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 18724.970364 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20238.163984 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21544.528485 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 16076.535509 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16057.528345 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 17871.070082 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20583.897088 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 14658.825790 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 12159694 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 10325 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 863086 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 292 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.088624 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 35.359589 # average number of cycles each access was blocked
+system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19110.494479 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 20249.153175 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 21543.374069 # average overall miss latency
+system.cpu0.dcache.demand_avg_miss_latency::total 16072.340996 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 16456.235657 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 18007.647323 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 20548.863572 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::total 14656.871123 # average overall miss latency
+system.cpu0.dcache.blocked_cycles::no_mshrs 12269651 # number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles::no_targets 11721 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_mshrs 884921 # number of cycles access was blocked
+system.cpu0.dcache.blocked::no_targets 303 # number of cycles access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.865250 # average number of cycles each access was blocked
+system.cpu0.dcache.avg_blocked_cycles::no_targets 38.683168 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 7548701 # number of writebacks
-system.cpu0.dcache.writebacks::total 7548701 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3073 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 106555 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1929145 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 2038773 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2189 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 286613 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2805614 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 3094416 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 22 # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2153 # number of WriteLineReq MSHR hits
-system.cpu0.dcache.WriteLineReq_mshr_hits::total 2175 # number of WriteLineReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8609 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 10642 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 114897 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 134148 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu1.data 5262 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu2.data 393168 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu3.data 4734759 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 5133189 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu1.data 5262 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu2.data 393168 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu3.data 4734759 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 5133189 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 619633 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 843957 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1591291 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 3054881 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 255781 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 364005 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 580451 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 1200237 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 146073 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 211968 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 317579 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 675620 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 114735 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 152915 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 290569 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.WriteLineReq_mshr_misses::total 558219 # number of WriteLineReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 29049 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 35897 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 72746 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137692 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.writebacks::writebacks 7530303 # number of writebacks
+system.cpu0.dcache.writebacks::total 7530303 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 3244 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 107323 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 1868973 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 1979540 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu1.data 2183 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 273456 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 2901507 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 3177146 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu2.data 23 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::cpu3.data 2180 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.WriteLineReq_mshr_hits::total 2203 # number of WriteLineReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 8289 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 11291 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 111071 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 130651 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu1.data 5427 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu2.data 380779 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu3.data 4770480 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 5156686 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu1.data 5427 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu2.data 380779 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu3.data 4770480 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 5156686 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 621394 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 863118 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 1546358 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 3030870 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 249354 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 351770 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 593582 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 1194706 # number of WriteReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 141097 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 198504 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 329326 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.SoftPFReq_mshr_misses::total 668927 # number of SoftPFReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu1.data 105494 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu2.data 155209 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::cpu3.data 296151 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.WriteLineReq_mshr_misses::total 556854 # number of WriteLineReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 29142 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 38806 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 69188 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 137136 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 4 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu1.data 875414 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu2.data 1207962 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu3.data 2171742 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 4255118 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu1.data 1021487 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu2.data 1419930 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu3.data 2489321 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 4930738 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6070 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4638 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 5330 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16038 # number of ReadReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5514 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4225 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 5069 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14808 # number of WriteReq MSHR uncacheable
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 11584 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 8863 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 10399 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30846 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 8870276000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12358412500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 24290690000 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45519378500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6598387000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9284220500 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17173491540 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33056099040 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2440625000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 3114719000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 4962911000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10518255000 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2617582500 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 4091120500 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 10122943811 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 16831646811 # number of WriteLineReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 372258500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 460319500 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 958480000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1791058000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_misses::cpu1.data 870748 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu2.data 1214888 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu3.data 2139940 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 4225576 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu1.data 1011845 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu2.data 1413392 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu3.data 2469266 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 4894503 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 6330 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 4869 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 4820 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.ReadReq_mshr_uncacheable::total 16019 # number of ReadReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 5775 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 4397 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 4483 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14655 # number of WriteReq MSHR uncacheable
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 12105 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 9266 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 9303 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.overall_mshr_uncacheable_misses::total 30674 # number of overall MSHR uncacheable misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 9061716000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 12702209500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 23634658500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 45398584000 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 6664052500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 9037887500 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 17334765406 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 33036705406 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 2466765500 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 2966502500 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 5024621000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 10457889000 # number of SoftPFReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu1.data 2579728500 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu2.data 4133451000 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::cpu3.data 10340882807 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.WriteLineReq_mshr_miss_latency::total 17054062307 # number of WriteLineReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 376111500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 502612000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 917608500 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1796332000 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 138500 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 138500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 15468663000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 21642633000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 41464181540 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 78575477540 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 17909288000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 24757352000 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 46427092540 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 89093732540 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1079003500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 788343500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 908401000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2775748000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 999912000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 723848500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 894544000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2618304500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2078915500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1512192000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1802945000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5394052500 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031449 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.030792 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.032114 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019192 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014297 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.015019 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.013775 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008538 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.758151 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.723529 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.730456 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.424347 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.718337 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.745269 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.740707 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.358510 # mshr miss rate for WriteLineReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061883 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.056979 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.062530 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036312 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 15725768500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 21740097000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 40969423906 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 78435289406 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 18192534000 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 24706599500 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 45994044906 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 88893178406 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1115432000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 821405500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 838200500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2775038000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1040608000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 744829000 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 810242500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2595679500 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 2156040000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 1566234500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 1648443000 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 5370717500 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.031439 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.031046 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.031409 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.019031 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013978 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.014422 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.014061 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008493 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.752337 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.709708 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.737686 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.420006 # mshr miss rate for SoftPFReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu1.data 0.703321 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu2.data 0.740632 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::cpu3.data 0.745777 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.WriteLineReq_mshr_miss_rate::total 0.357561 # mshr miss rate for WriteLineReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.061234 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.060974 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.060532 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.036139 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000004 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000001 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023286 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023390 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023686 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.014196 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.027033 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.027339 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.027021 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.016363 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14315.370550 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14643.414890 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15264.769297 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14900.540643 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25797.017761 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25505.749921 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29586.462148 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27541.309791 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16708.255461 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14694.288761 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15627.327374 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15568.300228 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 22814.158714 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 26754.213125 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34838.347556 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30152.407587 # average WriteLineReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12814.847327 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12823.341783 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13175.707255 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13007.712866 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.023155 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023277 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.023401 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.014088 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026774 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.026936 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.026871 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.016233 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14582.883002 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14716.654617 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 15284.079431 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14978.730200 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26725.268093 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 25692.604543 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 29203.657466 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 27652.581812 # average WriteReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17482.763631 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14944.295833 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15257.286093 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15633.827010 # average SoftPFReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu1.data 24453.793581 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu2.data 26631.516214 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::cpu3.data 34917.602193 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.WriteLineReq_avg_mshr_miss_latency::total 30625.733688 # average WriteLineReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12906.166358 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12951.914652 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 13262.538301 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13098.909112 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 34625 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 34625 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17670.111513 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17916.650524 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 19092.590897 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18466.110115 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17532.565760 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17435.614432 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18650.504511 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18069.046163 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 177760.049423 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 169974.881414 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 170431.707317 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173073.201147 # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 181340.587595 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 171325.088757 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 176473.466167 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 176816.889519 # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 179464.390539 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 170618.526458 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 173376.766997 # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 174870.404591 # average overall mshr uncacheable latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18060.068470 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17894.733506 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 19145.127390 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18562.034952 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17979.566040 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17480.358952 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 18626.606006 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18161.839600 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176213.586098 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 168701.067981 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 173900.518672 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 173234.159436 # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 180191.861472 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 169394.814646 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 180736.671872 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 177119.037871 # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 178111.524164 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 169030.271962 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 177194.775879 # average overall mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 175090.222990 # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.icache.tags.replacements 15782789 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.974752 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 561471069 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 15783301 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 35.573741 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 10320549500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 471.461580 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.134097 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.765697 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu3.inst 11.613377 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.920823 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006121 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu2.inst 0.050324 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu3.inst 0.022682 # Average percentage of cache occupancy
+system.cpu0.icache.tags.replacements 15815402 # number of replacements
+system.cpu0.icache.tags.tagsinuse 511.974774 # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs 560516546 # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs 15815914 # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs 35.440035 # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle 10320548500 # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.occ_blocks::cpu0.inst 470.983323 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu1.inst 3.370310 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu2.inst 25.740928 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_blocks::cpu3.inst 11.880214 # Average occupied blocks per requestor
+system.cpu0.icache.tags.occ_percent::cpu0.inst 0.919889 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu1.inst 0.006583 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu2.inst 0.050275 # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::cpu3.inst 0.023204 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999951 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 55 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 148 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 306 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 58 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 593396461 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 593396461 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 338161196 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 107417239 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu2.inst 66543293 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu3.inst 49349341 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 561471069 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 338161196 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 107417239 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu2.inst 66543293 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu3.inst 49349341 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 561471069 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 338161196 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 107417239 # number of overall hits
-system.cpu0.icache.overall_hits::cpu2.inst 66543293 # number of overall hits
-system.cpu0.icache.overall_hits::cpu3.inst 49349341 # number of overall hits
-system.cpu0.icache.overall_hits::total 561471069 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 5523274 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 1705507 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu2.inst 3878392 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu3.inst 5034836 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 16142009 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 5523274 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 1705507 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu2.inst 3878392 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu3.inst 5034836 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 16142009 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 5523274 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 1705507 # number of overall misses
-system.cpu0.icache.overall_misses::cpu2.inst 3878392 # number of overall misses
-system.cpu0.icache.overall_misses::cpu3.inst 5034836 # number of overall misses
-system.cpu0.icache.overall_misses::total 16142009 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 22950704500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 52180116500 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 65837786856 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 140968607856 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 22950704500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu2.inst 52180116500 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu3.inst 65837786856 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 140968607856 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 22950704500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu2.inst 52180116500 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu3.inst 65837786856 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 140968607856 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 343684470 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 109122746 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu2.inst 70421685 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu3.inst 54384177 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 577613078 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 343684470 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu1.inst 109122746 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu2.inst 70421685 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::cpu3.inst 54384177 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 577613078 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 343684470 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu1.inst 109122746 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu2.inst 70421685 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu3.inst 54384177 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 577613078 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016071 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015629 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.055074 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.092579 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.027946 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016071 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015629 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu2.inst 0.055074 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu3.inst 0.092579 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.027946 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016071 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015629 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu2.inst 0.055074 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu3.inst 0.092579 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.027946 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13456.822224 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13454.059440 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13076.451121 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 8733.027460 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13456.822224 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13454.059440 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13076.451121 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 8733.027460 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13456.822224 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13454.059440 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13076.451121 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 8733.027460 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 36241 # number of cycles access was blocked
+system.cpu0.icache.tags.tag_accesses 592508619 # Number of tag accesses
+system.cpu0.icache.tags.data_accesses 592508619 # Number of data accesses
+system.cpu0.icache.ReadReq_hits::cpu0.inst 338062772 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu1.inst 107390355 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu2.inst 66013680 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::cpu3.inst 49049739 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 560516546 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 338062772 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu1.inst 107390355 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu2.inst 66013680 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu3.inst 49049739 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 560516546 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 338062772 # number of overall hits
+system.cpu0.icache.overall_hits::cpu1.inst 107390355 # number of overall hits
+system.cpu0.icache.overall_hits::cpu2.inst 66013680 # number of overall hits
+system.cpu0.icache.overall_hits::cpu3.inst 49049739 # number of overall hits
+system.cpu0.icache.overall_hits::total 560516546 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 5529192 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu1.inst 1696190 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu2.inst 3915157 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu3.inst 5035545 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 16176084 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 5529192 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu1.inst 1696190 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu2.inst 3915157 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu3.inst 5035545 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 16176084 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 5529192 # number of overall misses
+system.cpu0.icache.overall_misses::cpu1.inst 1696190 # number of overall misses
+system.cpu0.icache.overall_misses::cpu2.inst 3915157 # number of overall misses
+system.cpu0.icache.overall_misses::cpu3.inst 5035545 # number of overall misses
+system.cpu0.icache.overall_misses::total 16176084 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 22827874500 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 52925900000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::cpu3.inst 65832917354 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 141586691854 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu1.inst 22827874500 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu2.inst 52925900000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::cpu3.inst 65832917354 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 141586691854 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu1.inst 22827874500 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu2.inst 52925900000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::cpu3.inst 65832917354 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 141586691854 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 343591964 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu1.inst 109086545 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu2.inst 69928837 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu3.inst 54085284 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 576692630 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 343591964 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu1.inst 109086545 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu2.inst 69928837 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu3.inst 54085284 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 576692630 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 343591964 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu1.inst 109086545 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu2.inst 69928837 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu3.inst 54085284 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 576692630 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.016092 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015549 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.055988 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu3.inst 0.093104 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.028050 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.016092 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015549 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu2.inst 0.055988 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::cpu3.inst 0.093104 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.028050 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.016092 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015549 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu2.inst 0.055988 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu3.inst 0.093104 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.028050 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13458.323950 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13518.206294 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu3.inst 13073.642943 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 8752.841037 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13458.323950 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13518.206294 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu3.inst 13073.642943 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 8752.841037 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13458.323950 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13518.206294 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu3.inst 13073.642943 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 8752.841037 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 40592 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 2942 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 3092 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.318491 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.128072 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 358626 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 358626 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu3.inst 358626 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 358626 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu3.inst 358626 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 358626 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1705507 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3878392 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4676210 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 10260109 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 1705507 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu2.inst 3878392 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu3.inst 4676210 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 10260109 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 1705507 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu2.inst 3878392 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu3.inst 4676210 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 10260109 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21245197500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 48301724500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 58313017880 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 127859939880 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21245197500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 48301724500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 58313017880 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 127859939880 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21245197500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 48301724500 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 58313017880 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 127859939880 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015629 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.055074 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.085985 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017763 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015629 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.055074 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.085985 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.017763 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015629 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.055074 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.085985 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.017763 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12456.822224 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12454.059440 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12470.145242 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12461.850052 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12456.822224 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12454.059440 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12470.145242 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12461.850052 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12456.822224 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12454.059440 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12470.145242 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 12461.850052 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 360095 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 360095 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu3.inst 360095 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 360095 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu3.inst 360095 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 360095 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 1696190 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 3915157 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 4675450 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 10286797 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 1696190 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu2.inst 3915157 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu3.inst 4675450 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 10286797 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 1696190 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu2.inst 3915157 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu3.inst 4675450 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 10286797 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 21131684500 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 49010743000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 58303327383 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 128445754883 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 21131684500 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 49010743000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 58303327383 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 128445754883 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 21131684500 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 49010743000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 58303327383 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 128445754883 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015549 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.055988 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.086446 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017838 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015549 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.055988 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.086446 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.017838 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015549 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.055988 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.086446 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.017838 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12458.323950 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12518.206294 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12470.099645 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12486.467351 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12458.323950 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12518.206294 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12470.099645 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 12486.467351 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12458.323950 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12518.206294 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12470.099645 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 12486.467351 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.dtb.walker.walks 31718 # Table walker walks requested
-system.cpu1.dtb.walker.walksLong 31718 # Table walker walks initiated with long descriptors
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4562 # Level at which table walker walks with long descriptors terminate
-system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 23271 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walks 31331 # Table walker walks requested
+system.cpu1.dtb.walker.walksLong 31331 # Table walker walks initiated with long descriptors
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level2 4585 # Level at which table walker walks with long descriptors terminate
+system.cpu1.dtb.walker.walksLongTerminationLevel::Level3 22783 # Level at which table walker walks with long descriptors terminate
system.cpu1.dtb.walker.walksSquashedBefore 5 # Table walks squashed before starting
-system.cpu1.dtb.walker.walkWaitTime::samples 31713 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::0 31713 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkWaitTime::total 31713 # Table walker wait (enqueue to first request) latency
-system.cpu1.dtb.walker.walkCompletionTime::samples 27838 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::mean 23890.419570 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::gmean 20799.818642 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::stdev 12686.242290 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::0-32767 18271 65.63% 65.63% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9416 33.82% 99.46% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::65536-98303 93 0.33% 99.79% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::98304-131071 40 0.14% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::163840-196607 7 0.03% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::229376-262143 2 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::262144-294911 3 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walkCompletionTime::total 27838 # Table walker service (enqueue to completion) latency
-system.cpu1.dtb.walker.walksPending::samples 1656807784 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::mean 0.386410 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::stdev 0.486926 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::0 1016600500 61.36% 61.36% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::1 640207284 38.64% 100.00% # Table walker pending requests distribution
-system.cpu1.dtb.walker.walksPending::total 1656807784 # Table walker pending requests distribution
-system.cpu1.dtb.walker.walkPageSizes::4K 23271 83.61% 83.61% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::2M 4562 16.39% 100.00% # Table walker page sizes translated
-system.cpu1.dtb.walker.walkPageSizes::total 27833 # Table walker page sizes translated
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31718 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkWaitTime::samples 31326 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::0 31326 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkWaitTime::total 31326 # Table walker wait (enqueue to first request) latency
+system.cpu1.dtb.walker.walkCompletionTime::samples 27373 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::mean 24398.385270 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::gmean 21301.040403 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::stdev 13057.600682 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::0-32767 17904 65.41% 65.41% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::32768-65535 9272 33.87% 99.28% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::65536-98303 108 0.39% 99.67% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::98304-131071 61 0.22% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::131072-163839 4 0.01% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::163840-196607 12 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::196608-229375 1 0.00% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::229376-262143 5 0.02% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::262144-294911 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walkCompletionTime::total 27373 # Table walker service (enqueue to completion) latency
+system.cpu1.dtb.walker.walksPending::samples 2726095120 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::mean 0.627697 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::stdev 0.483419 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::0 1014934000 37.23% 37.23% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::1 1711161120 62.77% 100.00% # Table walker pending requests distribution
+system.cpu1.dtb.walker.walksPending::total 2726095120 # Table walker pending requests distribution
+system.cpu1.dtb.walker.walkPageSizes::4K 22783 83.25% 83.25% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::2M 4585 16.75% 100.00% # Table walker page sizes translated
+system.cpu1.dtb.walker.walkPageSizes::total 27368 # Table walker page sizes translated
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 31331 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31718 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27833 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 31331 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 27368 # Table walker requests started/completed, data/inst
system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27833 # Table walker requests started/completed, data/inst
-system.cpu1.dtb.walker.walkRequestOrigin::total 59551 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 27368 # Table walker requests started/completed, data/inst
+system.cpu1.dtb.walker.walkRequestOrigin::total 58699 # Table walker requests started/completed, data/inst
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 20370755 # DTB read hits
-system.cpu1.dtb.read_misses 24112 # DTB read misses
-system.cpu1.dtb.write_hits 18527997 # DTB write hits
-system.cpu1.dtb.write_misses 7606 # DTB write misses
-system.cpu1.dtb.flush_tlb 1180 # Number of times complete TLB was flushed
+system.cpu1.dtb.read_hits 20435080 # DTB read hits
+system.cpu1.dtb.read_misses 24017 # DTB read misses
+system.cpu1.dtb.write_hits 18473169 # DTB write hits
+system.cpu1.dtb.write_misses 7314 # DTB write misses
+system.cpu1.dtb.flush_tlb 1184 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 5411 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 128 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 17894 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 5397 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 130 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 17737 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 972 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 965 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 2622 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 20394867 # DTB read accesses
-system.cpu1.dtb.write_accesses 18535603 # DTB write accesses
+system.cpu1.dtb.perms_faults 2574 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 20459097 # DTB read accesses
+system.cpu1.dtb.write_accesses 18480483 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 38898752 # DTB hits
-system.cpu1.dtb.misses 31718 # DTB misses
-system.cpu1.dtb.accesses 38930470 # DTB accesses
+system.cpu1.dtb.hits 38908249 # DTB hits
+system.cpu1.dtb.misses 31331 # DTB misses
+system.cpu1.dtb.accesses 38939580 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.walker.walks 20303 # Table walker walks requested
-system.cpu1.itb.walker.walksLong 20303 # Table walker walks initiated with long descriptors
-system.cpu1.itb.walker.walksLongTerminationLevel::Level2 913 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walksLongTerminationLevel::Level3 18082 # Level at which table walker walks with long descriptors terminate
-system.cpu1.itb.walker.walkWaitTime::samples 20303 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::0 20303 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkWaitTime::total 20303 # Table walker wait (enqueue to first request) latency
-system.cpu1.itb.walker.walkCompletionTime::samples 18995 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::mean 26989.076073 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::gmean 24368.047797 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::stdev 13392.289816 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::0-32767 10117 53.26% 53.26% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::32768-65535 8707 45.84% 99.10% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::65536-98303 60 0.32% 99.42% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::98304-131071 90 0.47% 99.89% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::131072-163839 2 0.01% 99.90% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::163840-196607 6 0.03% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::196608-229375 3 0.02% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::229376-262143 6 0.03% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::327680-360447 1 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::360448-393215 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walkCompletionTime::total 18995 # Table walker service (enqueue to completion) latency
-system.cpu1.itb.walker.walksPending::samples 1000001500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::0 1000001500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu1.itb.walker.walksPending::total 1000001500 # Table walker pending requests distribution
-system.cpu1.itb.walker.walkPageSizes::4K 18082 95.19% 95.19% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::2M 913 4.81% 100.00% # Table walker page sizes translated
-system.cpu1.itb.walker.walkPageSizes::total 18995 # Table walker page sizes translated
+system.cpu1.itb.walker.walks 20082 # Table walker walks requested
+system.cpu1.itb.walker.walksLong 20082 # Table walker walks initiated with long descriptors
+system.cpu1.itb.walker.walksLongTerminationLevel::Level2 956 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walksLongTerminationLevel::Level3 17736 # Level at which table walker walks with long descriptors terminate
+system.cpu1.itb.walker.walkWaitTime::samples 20082 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::0 20082 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkWaitTime::total 20082 # Table walker wait (enqueue to first request) latency
+system.cpu1.itb.walker.walkCompletionTime::samples 18692 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::mean 27635.592767 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::gmean 24782.304535 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::stdev 14713.760053 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::0-32767 9635 51.55% 51.55% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::32768-65535 8833 47.26% 98.80% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::65536-98303 80 0.43% 99.23% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::98304-131071 115 0.62% 99.84% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::131072-163839 1 0.01% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::163840-196607 12 0.06% 99.91% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::196608-229375 3 0.02% 99.93% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::229376-262143 3 0.02% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::262144-294911 4 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::294912-327679 2 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::327680-360447 3 0.02% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walkCompletionTime::total 18692 # Table walker service (enqueue to completion) latency
+system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution
+system.cpu1.itb.walker.walkPageSizes::4K 17736 94.89% 94.89% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::2M 956 5.11% 100.00% # Table walker page sizes translated
+system.cpu1.itb.walker.walkPageSizes::total 18692 # Table walker page sizes translated
system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20303 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20303 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 20082 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Requested::total 20082 # Table walker requests started/completed, data/inst
system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18995 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18995 # Table walker requests started/completed, data/inst
-system.cpu1.itb.walker.walkRequestOrigin::total 39298 # Table walker requests started/completed, data/inst
-system.cpu1.itb.inst_hits 109122746 # ITB inst hits
-system.cpu1.itb.inst_misses 20303 # ITB inst misses
+system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 18692 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin_Completed::total 18692 # Table walker requests started/completed, data/inst
+system.cpu1.itb.walker.walkRequestOrigin::total 38774 # Table walker requests started/completed, data/inst
+system.cpu1.itb.inst_hits 109086545 # ITB inst hits
+system.cpu1.itb.inst_misses 20082 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
-system.cpu1.itb.flush_tlb 1180 # Number of times complete TLB was flushed
+system.cpu1.itb.flush_tlb 1184 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 5411 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 128 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 13373 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 5397 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 130 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 13123 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 109143049 # ITB inst accesses
-system.cpu1.itb.hits 109122746 # DTB hits
-system.cpu1.itb.misses 20303 # DTB misses
-system.cpu1.itb.accesses 109143049 # DTB accesses
-system.cpu1.numCycles 1180099858 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 109106627 # ITB inst accesses
+system.cpu1.itb.hits 109086545 # DTB hits
+system.cpu1.itb.misses 20082 # DTB misses
+system.cpu1.itb.accesses 109106627 # DTB accesses
+system.cpu1.numCycles 1184099170 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 109047622 # Number of instructions committed
-system.cpu1.committedOps 127894194 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 117464270 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 113646 # Number of float alu accesses
-system.cpu1.num_func_calls 6418056 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 16543747 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 117464270 # number of integer instructions
-system.cpu1.num_fp_insts 113646 # number of float instructions
-system.cpu1.num_int_register_reads 169880190 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 93121428 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 186254 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 89372 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 28297680 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 28206937 # number of times the CC registers were written
-system.cpu1.num_mem_refs 38895648 # number of memory refs
-system.cpu1.num_load_insts 20369525 # Number of load instructions
-system.cpu1.num_store_insts 18526123 # Number of store instructions
-system.cpu1.num_idle_cycles 1154177022.629432 # Number of idle cycles
-system.cpu1.num_busy_cycles 25922835.370568 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.021967 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.978033 # Percentage of idle cycles
-system.cpu1.Branches 24335155 # Number of branches fetched
+system.cpu1.committedInsts 109009230 # Number of instructions committed
+system.cpu1.committedOps 127862448 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 117464588 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 115738 # Number of float alu accesses
+system.cpu1.num_func_calls 6440342 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 16554986 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 117464588 # number of integer instructions
+system.cpu1.num_fp_insts 115738 # number of float instructions
+system.cpu1.num_int_register_reads 169322185 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 93148708 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 190671 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 89412 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 28259298 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 28158154 # number of times the CC registers were written
+system.cpu1.num_mem_refs 38905190 # number of memory refs
+system.cpu1.num_load_insts 20434165 # Number of load instructions
+system.cpu1.num_store_insts 18471025 # Number of store instructions
+system.cpu1.num_idle_cycles 1158563290.473996 # Number of idle cycles
+system.cpu1.num_busy_cycles 25535879.526004 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.021566 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.978434 # Percentage of idle cycles
+system.cpu1.Branches 24332682 # Number of branches fetched
system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 88791781 69.39% 69.39% # Class of executed instruction
-system.cpu1.op_class::IntMult 259621 0.20% 69.59% # Class of executed instruction
-system.cpu1.op_class::IntDiv 10323 0.01% 69.60% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 20 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.60% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 11904 0.01% 69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.61% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.61% # Class of executed instruction
-system.cpu1.op_class::MemRead 20369525 15.92% 85.52% # Class of executed instruction
-system.cpu1.op_class::MemWrite 18526123 14.48% 100.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 88740475 69.36% 69.36% # Class of executed instruction
+system.cpu1.op_class::IntMult 271069 0.21% 69.57% # Class of executed instruction
+system.cpu1.op_class::IntDiv 11362 0.01% 69.58% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.58% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 11625 0.01% 69.59% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.59% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.59% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.59% # Class of executed instruction
+system.cpu1.op_class::MemRead 20434165 15.97% 85.56% # Class of executed instruction
+system.cpu1.op_class::MemWrite 18471025 14.44% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 127969318 # Class of executed instruction
+system.cpu1.op_class::total 127939763 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 40525945 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 28226804 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 1998617 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 29685490 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 21101641 # Number of BTB hits
+system.cpu2.branchPred.lookups 40521416 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 28118087 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 2031475 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 29676837 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 20868777 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 71.084025 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 4984455 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 337609 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 70.320085 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 4994532 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 335745 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.dtb.walker.walks 94850 # Table walker walks requested
-system.cpu2.dtb.walker.walksLong 94850 # Table walker walks initiated with long descriptors
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7112 # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 30265 # Level at which table walker walks with long descriptors terminate
-system.cpu2.dtb.walker.walkWaitTime::samples 94850 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::0 94850 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkWaitTime::total 94850 # Table walker wait (enqueue to first request) latency
-system.cpu2.dtb.walker.walkCompletionTime::samples 37377 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::mean 24334.778072 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::gmean 21415.303868 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::stdev 12070.350338 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::0-32767 24490 65.52% 65.52% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::32768-65535 12692 33.96% 99.48% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::65536-98303 111 0.30% 99.78% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::98304-131071 62 0.17% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::131072-163839 2 0.01% 99.95% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::163840-196607 6 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::229376-262143 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::262144-294911 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::294912-327679 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walkCompletionTime::total 37377 # Table walker service (enqueue to completion) latency
-system.cpu2.dtb.walker.walksPending::samples 2000229500 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::0 2000229500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu2.dtb.walker.walksPending::total 2000229500 # Table walker pending requests distribution
-system.cpu2.dtb.walker.walkPageSizes::4K 30265 80.97% 80.97% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::2M 7112 19.03% 100.00% # Table walker page sizes translated
-system.cpu2.dtb.walker.walkPageSizes::total 37377 # Table walker page sizes translated
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 94850 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walks 95252 # Table walker walks requested
+system.cpu2.dtb.walker.walksLong 95252 # Table walker walks initiated with long descriptors
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level2 7000 # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walksLongTerminationLevel::Level3 29929 # Level at which table walker walks with long descriptors terminate
+system.cpu2.dtb.walker.walkWaitTime::samples 95252 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::0 95252 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkWaitTime::total 95252 # Table walker wait (enqueue to first request) latency
+system.cpu2.dtb.walker.walkCompletionTime::samples 36929 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::mean 24871.388340 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::gmean 22228.503196 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::stdev 11289.834647 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::0-32767 23698 64.17% 64.17% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::32768-65535 13086 35.44% 99.61% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::65536-98303 84 0.23% 99.83% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::98304-131071 38 0.10% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::131072-163839 4 0.01% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::163840-196607 9 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::196608-229375 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::229376-262143 4 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::262144-294911 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walkCompletionTime::total 36929 # Table walker service (enqueue to completion) latency
+system.cpu2.dtb.walker.walksPending::samples 2000228500 # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::0 2000228500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu2.dtb.walker.walksPending::total 2000228500 # Table walker pending requests distribution
+system.cpu2.dtb.walker.walkPageSizes::4K 29929 81.04% 81.04% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::2M 7000 18.96% 100.00% # Table walker page sizes translated
+system.cpu2.dtb.walker.walkPageSizes::total 36929 # Table walker page sizes translated
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 95252 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 94850 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 37377 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 95252 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 36929 # Table walker requests started/completed, data/inst
system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 37377 # Table walker requests started/completed, data/inst
-system.cpu2.dtb.walker.walkRequestOrigin::total 132227 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 36929 # Table walker requests started/completed, data/inst
+system.cpu2.dtb.walker.walkRequestOrigin::total 132181 # Table walker requests started/completed, data/inst
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 28616458 # DTB read hits
-system.cpu2.dtb.read_misses 79197 # DTB read misses
-system.cpu2.dtb.write_hits 25171351 # DTB write hits
-system.cpu2.dtb.write_misses 15653 # DTB write misses
-system.cpu2.dtb.flush_tlb 1181 # Number of times complete TLB was flushed
+system.cpu2.dtb.read_hits 29009718 # DTB read hits
+system.cpu2.dtb.read_misses 79511 # DTB read misses
+system.cpu2.dtb.write_hits 25340544 # DTB write hits
+system.cpu2.dtb.write_misses 15741 # DTB write misses
+system.cpu2.dtb.flush_tlb 1184 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.dtb.flush_tlb_mva_asid 6998 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.dtb.flush_tlb_asid 187 # Number of times TLB was flushed by ASID
-system.cpu2.dtb.flush_entries 22525 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 82 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 2323 # Number of TLB faults due to prefetch
+system.cpu2.dtb.flush_tlb_mva_asid 6565 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.dtb.flush_tlb_asid 192 # Number of times TLB was flushed by ASID
+system.cpu2.dtb.flush_entries 22319 # Number of entries that have been flushed from TLB
+system.cpu2.dtb.align_faults 74 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 2265 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 3900 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 28695655 # DTB read accesses
-system.cpu2.dtb.write_accesses 25187004 # DTB write accesses
+system.cpu2.dtb.perms_faults 3693 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 29089229 # DTB read accesses
+system.cpu2.dtb.write_accesses 25356285 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 53787809 # DTB hits
-system.cpu2.dtb.misses 94850 # DTB misses
-system.cpu2.dtb.accesses 53882659 # DTB accesses
+system.cpu2.dtb.hits 54350262 # DTB hits
+system.cpu2.dtb.misses 95252 # DTB misses
+system.cpu2.dtb.accesses 54445514 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.walker.walks 27487 # Table walker walks requested
-system.cpu2.itb.walker.walksLong 27487 # Table walker walks initiated with long descriptors
-system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1835 # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22882 # Level at which table walker walks with long descriptors terminate
-system.cpu2.itb.walker.walkWaitTime::samples 27487 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::0 27487 100.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkWaitTime::total 27487 # Table walker wait (enqueue to first request) latency
-system.cpu2.itb.walker.walkCompletionTime::samples 24717 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::mean 27209.107092 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::gmean 24621.462305 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::stdev 12743.919659 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::0-32767 12896 52.17% 52.17% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::32768-65535 11567 46.80% 98.97% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::65536-98303 97 0.39% 99.36% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::98304-131071 138 0.56% 99.92% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::131072-163839 3 0.01% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::163840-196607 7 0.03% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::196608-229375 6 0.02% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::229376-262143 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::294912-327679 2 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walkCompletionTime::total 24717 # Table walker service (enqueue to completion) latency
-system.cpu2.itb.walker.walksPending::samples 2000203500 # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::0 2000203500 100.00% 100.00% # Table walker pending requests distribution
-system.cpu2.itb.walker.walksPending::total 2000203500 # Table walker pending requests distribution
-system.cpu2.itb.walker.walkPageSizes::4K 22882 92.58% 92.58% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::2M 1835 7.42% 100.00% # Table walker page sizes translated
-system.cpu2.itb.walker.walkPageSizes::total 24717 # Table walker page sizes translated
+system.cpu2.itb.walker.walks 27224 # Table walker walks requested
+system.cpu2.itb.walker.walksLong 27224 # Table walker walks initiated with long descriptors
+system.cpu2.itb.walker.walksLongTerminationLevel::Level2 1814 # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walksLongTerminationLevel::Level3 22841 # Level at which table walker walks with long descriptors terminate
+system.cpu2.itb.walker.walkWaitTime::samples 27224 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::0 27224 100.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkWaitTime::total 27224 # Table walker wait (enqueue to first request) latency
+system.cpu2.itb.walker.walkCompletionTime::samples 24655 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::mean 27863.922125 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::gmean 25521.619222 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::stdev 11746.072802 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::0-32767 11779 47.78% 47.78% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::32768-65535 12711 51.56% 99.33% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::65536-98303 67 0.27% 99.60% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::98304-131071 84 0.34% 99.94% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::131072-163839 1 0.00% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::163840-196607 5 0.02% 99.97% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::196608-229375 3 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::229376-262143 1 0.00% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::262144-294911 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::294912-327679 1 0.00% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::327680-360447 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::360448-393215 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walkCompletionTime::total 24655 # Table walker service (enqueue to completion) latency
+system.cpu2.itb.walker.walksPending::samples 2000202500 # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::0 2000202500 100.00% 100.00% # Table walker pending requests distribution
+system.cpu2.itb.walker.walksPending::total 2000202500 # Table walker pending requests distribution
+system.cpu2.itb.walker.walkPageSizes::4K 22841 92.64% 92.64% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::2M 1814 7.36% 100.00% # Table walker page sizes translated
+system.cpu2.itb.walker.walkPageSizes::total 24655 # Table walker page sizes translated
system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27487 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27487 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 27224 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Requested::total 27224 # Table walker requests started/completed, data/inst
system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24717 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24717 # Table walker requests started/completed, data/inst
-system.cpu2.itb.walker.walkRequestOrigin::total 52204 # Table walker requests started/completed, data/inst
-system.cpu2.itb.inst_hits 70482542 # ITB inst hits
-system.cpu2.itb.inst_misses 27487 # ITB inst misses
+system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 24655 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin_Completed::total 24655 # Table walker requests started/completed, data/inst
+system.cpu2.itb.walker.walkRequestOrigin::total 51879 # Table walker requests started/completed, data/inst
+system.cpu2.itb.inst_hits 69987684 # ITB inst hits
+system.cpu2.itb.inst_misses 27224 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
-system.cpu2.itb.flush_tlb 1181 # Number of times complete TLB was flushed
+system.cpu2.itb.flush_tlb 1184 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu2.itb.flush_tlb_mva_asid 6998 # Number of times TLB was flushed by MVA & ASID
-system.cpu2.itb.flush_tlb_asid 187 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 17121 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_tlb_mva_asid 6565 # Number of times TLB was flushed by MVA & ASID
+system.cpu2.itb.flush_tlb_asid 192 # Number of times TLB was flushed by ASID
+system.cpu2.itb.flush_entries 17001 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 57866 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 55845 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 70510029 # ITB inst accesses
-system.cpu2.itb.hits 70482542 # DTB hits
-system.cpu2.itb.misses 27487 # DTB misses
-system.cpu2.itb.accesses 70510029 # DTB accesses
-system.cpu2.numCycles 6664328122 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 70014908 # ITB inst accesses
+system.cpu2.itb.hits 69987684 # DTB hits
+system.cpu2.itb.misses 27224 # DTB misses
+system.cpu2.itb.accesses 70014908 # DTB accesses
+system.cpu2.numCycles 6727315780 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.committedInsts 147830191 # Number of instructions committed
-system.cpu2.committedOps 173473680 # Number of ops (including micro ops) committed
-system.cpu2.discardedOps 14792725 # Number of ops (including micro ops) which were discarded before commit
-system.cpu2.numFetchSuspends 1537 # Number of times Execute suspended instruction fetching
-system.cpu2.quiesceCycles 95888456497 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.cpi 45.080968 # CPI: cycles per instruction
-system.cpu2.ipc 0.022182 # IPC: instructions per cycle
+system.cpu2.committedInsts 148611673 # Number of instructions committed
+system.cpu2.committedOps 174373358 # Number of ops (including micro ops) committed
+system.cpu2.discardedOps 14098587 # Number of ops (including micro ops) which were discarded before commit
+system.cpu2.numFetchSuspends 1631 # Number of times Execute suspended instruction fetching
+system.cpu2.quiesceCycles 95904949193 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu2.cpi 45.267748 # CPI: cycles per instruction
+system.cpu2.ipc 0.022091 # IPC: instructions per cycle
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.tickCycles 277268742 # Number of cycles that the object actually ticked
-system.cpu2.idleCycles 6387059380 # Total number of cycles that the object has spent stopped
-system.cpu3.branchPred.lookups 75157877 # Number of BP lookups
-system.cpu3.branchPred.condPredicted 50856390 # Number of conditional branches predicted
-system.cpu3.branchPred.condIncorrect 3416721 # Number of conditional branches incorrect
-system.cpu3.branchPred.BTBLookups 51465907 # Number of BTB lookups
-system.cpu3.branchPred.BTBHits 36468064 # Number of BTB hits
+system.cpu2.tickCycles 276122031 # Number of cycles that the object actually ticked
+system.cpu2.idleCycles 6451193749 # Total number of cycles that the object has spent stopped
+system.cpu3.branchPred.lookups 75051711 # Number of BP lookups
+system.cpu3.branchPred.condPredicted 50745018 # Number of conditional branches predicted
+system.cpu3.branchPred.condIncorrect 3426540 # Number of conditional branches incorrect
+system.cpu3.branchPred.BTBLookups 51416576 # Number of BTB lookups
+system.cpu3.branchPred.BTBHits 36523401 # Number of BTB hits
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu3.branchPred.BTBHitPct 70.858683 # BTB Hit Percentage
-system.cpu3.branchPred.usedRAS 9896161 # Number of times the RAS was used to get a target.
-system.cpu3.branchPred.RASInCorrect 105828 # Number of incorrect RAS predictions.
+system.cpu3.branchPred.BTBHitPct 71.034293 # BTB Hit Percentage
+system.cpu3.branchPred.usedRAS 9845099 # Number of times the RAS was used to get a target.
+system.cpu3.branchPred.RASInCorrect 104872 # Number of incorrect RAS predictions.
system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.dtb.walker.walks 516175 # Table walker walks requested
-system.cpu3.dtb.walker.walksLong 516175 # Table walker walks initiated with long descriptors
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8289 # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 49802 # Level at which table walker walks with long descriptors terminate
-system.cpu3.dtb.walker.walksSquashedBefore 319657 # Table walks squashed before starting
-system.cpu3.dtb.walker.walkWaitTime::samples 196518 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::mean 2097.090343 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::stdev 12006.037085 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::0-65535 195408 99.44% 99.44% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::65536-131071 810 0.41% 99.85% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::131072-196607 191 0.10% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::196608-262143 57 0.03% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::262144-327679 27 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::327680-393215 12 0.01% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walks 518940 # Table walker walks requested
+system.cpu3.dtb.walker.walksLong 518940 # Table walker walks initiated with long descriptors
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level2 8603 # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksLongTerminationLevel::Level3 51054 # Level at which table walker walks with long descriptors terminate
+system.cpu3.dtb.walker.walksSquashedBefore 322381 # Table walks squashed before starting
+system.cpu3.dtb.walker.walkWaitTime::samples 196559 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::mean 2153.353446 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::stdev 12453.010606 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::0-65535 195431 99.43% 99.43% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::65536-131071 797 0.41% 99.83% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::131072-196607 204 0.10% 99.94% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::196608-262143 65 0.03% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::262144-327679 34 0.02% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::327680-393215 15 0.01% 99.99% # Table walker wait (enqueue to first request) latency
system.cpu3.dtb.walker.walkWaitTime::393216-458751 11 0.01% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::458752-524287 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::524288-589823 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkWaitTime::total 196518 # Table walker wait (enqueue to first request) latency
-system.cpu3.dtb.walker.walkCompletionTime::samples 233052 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::mean 21512.128195 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::gmean 17601.941392 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::stdev 14913.346295 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::0-65535 228911 98.22% 98.22% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::65536-131071 3858 1.66% 99.88% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::131072-196607 119 0.05% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::196608-262143 117 0.05% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::262144-327679 29 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::327680-393215 13 0.01% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::393216-458751 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::458752-524287 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::589824-655359 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walkCompletionTime::total 233052 # Table walker service (enqueue to completion) latency
-system.cpu3.dtb.walker.walksPending::samples -26470108720 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::mean 0.558973 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::0-3 -27011428720 102.05% 102.05% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::4-7 297974000 -1.13% 100.92% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::8-11 102453500 -0.39% 100.53% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::12-15 64308500 -0.24% 100.29% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::16-19 26659500 -0.10% 100.19% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::20-23 13977000 -0.05% 100.14% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::24-27 12432000 -0.05% 100.09% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::28-31 20278500 -0.08% 100.01% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::32-35 3004000 -0.01% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::36-39 171500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::40-43 49500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::44-47 10000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::48-51 2000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.dtb.walker.walksPending::total -26470108720 # Table walker pending requests distribution
-system.cpu3.dtb.walker.walkPageSizes::4K 49802 85.73% 85.73% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::2M 8289 14.27% 100.00% # Table walker page sizes translated
-system.cpu3.dtb.walker.walkPageSizes::total 58091 # Table walker page sizes translated
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 516175 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkWaitTime::589824-655359 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::655360-720895 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkWaitTime::total 196559 # Table walker wait (enqueue to first request) latency
+system.cpu3.dtb.walker.walkCompletionTime::samples 238895 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::mean 21937.397183 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::gmean 18018.053356 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::stdev 15122.644026 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::0-32767 188060 78.72% 78.72% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::32768-65535 46353 19.40% 98.12% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::65536-98303 3667 1.53% 99.66% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::98304-131071 466 0.20% 99.85% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::131072-163839 68 0.03% 99.88% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::163840-196607 89 0.04% 99.92% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::196608-229375 102 0.04% 99.96% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::229376-262143 32 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::262144-294911 22 0.01% 99.98% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::294912-327679 17 0.01% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::327680-360447 10 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::360448-393215 4 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::393216-425983 3 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::491520-524287 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walkCompletionTime::total 238895 # Table walker service (enqueue to completion) latency
+system.cpu3.dtb.walker.walksPending::samples -25404728884 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::mean 1.186676 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::0-3 -25965813384 102.21% 102.21% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::4-7 315763500 -1.24% 100.97% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::8-11 105079500 -0.41% 100.55% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::12-15 65519000 -0.26% 100.29% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::16-19 25638000 -0.10% 100.19% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::20-23 14396000 -0.06% 100.14% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::24-27 12378500 -0.05% 100.09% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::28-31 18510000 -0.07% 100.01% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::32-35 3399500 -0.01% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::36-39 261000 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::40-43 34500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::44-47 99500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::48-51 5500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.dtb.walker.walksPending::total -25404728884 # Table walker pending requests distribution
+system.cpu3.dtb.walker.walkPageSizes::4K 51054 85.58% 85.58% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::2M 8603 14.42% 100.00% # Table walker page sizes translated
+system.cpu3.dtb.walker.walkPageSizes::total 59657 # Table walker page sizes translated
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 518940 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 516175 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 58091 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 518940 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 59657 # Table walker requests started/completed, data/inst
system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 58091 # Table walker requests started/completed, data/inst
-system.cpu3.dtb.walker.walkRequestOrigin::total 574266 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 59657 # Table walker requests started/completed, data/inst
+system.cpu3.dtb.walker.walkRequestOrigin::total 578597 # Table walker requests started/completed, data/inst
system.cpu3.dtb.inst_hits 0 # ITB inst hits
system.cpu3.dtb.inst_misses 0 # ITB inst misses
-system.cpu3.dtb.read_hits 59190068 # DTB read hits
-system.cpu3.dtb.read_misses 354265 # DTB read misses
-system.cpu3.dtb.write_hits 46339519 # DTB write hits
-system.cpu3.dtb.write_misses 161910 # DTB write misses
-system.cpu3.dtb.flush_tlb 1179 # Number of times complete TLB was flushed
+system.cpu3.dtb.read_hits 58887686 # DTB read hits
+system.cpu3.dtb.read_misses 354452 # DTB read misses
+system.cpu3.dtb.write_hits 46401949 # DTB write hits
+system.cpu3.dtb.write_misses 164488 # DTB write misses
+system.cpu3.dtb.flush_tlb 1183 # Number of times complete TLB was flushed
system.cpu3.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu3.dtb.flush_tlb_mva_asid 11674 # Number of times TLB was flushed by MVA & ASID
-system.cpu3.dtb.flush_tlb_asid 299 # Number of times TLB was flushed by ASID
-system.cpu3.dtb.flush_entries 28883 # Number of entries that have been flushed from TLB
-system.cpu3.dtb.align_faults 57 # Number of TLB faults due to alignment restrictions
-system.cpu3.dtb.prefetch_faults 5029 # Number of TLB faults due to prefetch
+system.cpu3.dtb.flush_tlb_mva_asid 11695 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.dtb.flush_tlb_asid 298 # Number of times TLB was flushed by ASID
+system.cpu3.dtb.flush_entries 29305 # Number of entries that have been flushed from TLB
+system.cpu3.dtb.align_faults 75 # Number of TLB faults due to alignment restrictions
+system.cpu3.dtb.prefetch_faults 5086 # Number of TLB faults due to prefetch
system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.dtb.perms_faults 29040 # Number of TLB faults due to permissions restrictions
-system.cpu3.dtb.read_accesses 59544333 # DTB read accesses
-system.cpu3.dtb.write_accesses 46501429 # DTB write accesses
+system.cpu3.dtb.perms_faults 31208 # Number of TLB faults due to permissions restrictions
+system.cpu3.dtb.read_accesses 59242138 # DTB read accesses
+system.cpu3.dtb.write_accesses 46566437 # DTB write accesses
system.cpu3.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu3.dtb.hits 105529587 # DTB hits
-system.cpu3.dtb.misses 516175 # DTB misses
-system.cpu3.dtb.accesses 106045762 # DTB accesses
+system.cpu3.dtb.hits 105289635 # DTB hits
+system.cpu3.dtb.misses 518940 # DTB misses
+system.cpu3.dtb.accesses 105808575 # DTB accesses
system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu3.itb.walker.walks 59515 # Table walker walks requested
-system.cpu3.itb.walker.walksLong 59515 # Table walker walks initiated with long descriptors
-system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1820 # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksLongTerminationLevel::Level3 40428 # Level at which table walker walks with long descriptors terminate
-system.cpu3.itb.walker.walksSquashedBefore 8158 # Table walks squashed before starting
-system.cpu3.itb.walker.walkWaitTime::samples 51357 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::mean 1446.696653 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::stdev 8669.763957 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::0-32767 50895 99.10% 99.10% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::32768-65535 295 0.57% 99.67% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::65536-98303 94 0.18% 99.86% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::98304-131071 42 0.08% 99.94% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::131072-163839 10 0.02% 99.96% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::163840-196607 7 0.01% 99.97% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::196608-229375 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::229376-262143 4 0.01% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::262144-294911 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::294912-327679 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::327680-360447 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::393216-425983 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkWaitTime::total 51357 # Table walker wait (enqueue to first request) latency
-system.cpu3.itb.walker.walkCompletionTime::samples 50406 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::mean 27093.679324 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::gmean 23240.458219 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::stdev 16758.841159 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::0-32767 28504 56.55% 56.55% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::32768-65535 21034 41.73% 98.28% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::65536-98303 420 0.83% 99.11% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::98304-131071 332 0.66% 99.77% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::131072-163839 37 0.07% 99.84% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::163840-196607 32 0.06% 99.91% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::196608-229375 12 0.02% 99.93% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::229376-262143 7 0.01% 99.94% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::262144-294911 9 0.02% 99.96% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::294912-327679 6 0.01% 99.97% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::327680-360447 5 0.01% 99.98% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::360448-393215 5 0.01% 99.99% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::393216-425983 2 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::458752-491519 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walkCompletionTime::total 50406 # Table walker service (enqueue to completion) latency
-system.cpu3.itb.walker.walksPending::samples -26472605720 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::mean 1.148605 # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::0 3969304628 -14.99% -14.99% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::1 -30473405348 115.11% 100.12% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::2 28081500 -0.11% 100.01% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::3 3146000 -0.01% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::4 137000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::5 114000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::6 8000 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::7 8500 -0.00% 100.00% # Table walker pending requests distribution
-system.cpu3.itb.walker.walksPending::total -26472605720 # Table walker pending requests distribution
-system.cpu3.itb.walker.walkPageSizes::4K 40428 95.69% 95.69% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::2M 1820 4.31% 100.00% # Table walker page sizes translated
-system.cpu3.itb.walker.walkPageSizes::total 42248 # Table walker page sizes translated
+system.cpu3.itb.walker.walks 61371 # Table walker walks requested
+system.cpu3.itb.walker.walksLong 61371 # Table walker walks initiated with long descriptors
+system.cpu3.itb.walker.walksLongTerminationLevel::Level2 1880 # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksLongTerminationLevel::Level3 41824 # Level at which table walker walks with long descriptors terminate
+system.cpu3.itb.walker.walksSquashedBefore 8320 # Table walks squashed before starting
+system.cpu3.itb.walker.walkWaitTime::samples 53051 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::mean 1484.693974 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::stdev 7949.697617 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::0-32767 52591 99.13% 99.13% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::32768-65535 303 0.57% 99.70% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::65536-98303 95 0.18% 99.88% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::98304-131071 39 0.07% 99.96% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::131072-163839 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::163840-196607 10 0.02% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::196608-229375 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::229376-262143 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::262144-294911 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkWaitTime::total 53051 # Table walker wait (enqueue to first request) latency
+system.cpu3.itb.walker.walkCompletionTime::samples 52024 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::mean 27951.877979 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::gmean 24094.893737 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::stdev 16939.258391 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::0-65535 51107 98.24% 98.24% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::65536-131071 782 1.50% 99.74% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::131072-196607 83 0.16% 99.90% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::196608-262143 28 0.05% 99.95% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::262144-327679 17 0.03% 99.99% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::327680-393215 6 0.01% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::720896-786431 1 0.00% 100.00% # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walkCompletionTime::total 52024 # Table walker service (enqueue to completion) latency
+system.cpu3.itb.walker.walksPending::samples -25407358384 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::mean 1.082792 # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::0 2146509568 -8.45% -8.45% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::1 -27591517452 108.60% 100.15% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::2 32946500 -0.13% 100.02% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::3 4144000 -0.02% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::4 483500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::5 75500 -0.00% 100.00% # Table walker pending requests distribution
+system.cpu3.itb.walker.walksPending::total -25407358384 # Table walker pending requests distribution
+system.cpu3.itb.walker.walkPageSizes::4K 41824 95.70% 95.70% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::2M 1880 4.30% 100.00% # Table walker page sizes translated
+system.cpu3.itb.walker.walkPageSizes::total 43704 # Table walker page sizes translated
system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 59515 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Requested::total 59515 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 61371 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Requested::total 61371 # Table walker requests started/completed, data/inst
system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 42248 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin_Completed::total 42248 # Table walker requests started/completed, data/inst
-system.cpu3.itb.walker.walkRequestOrigin::total 101763 # Table walker requests started/completed, data/inst
-system.cpu3.itb.inst_hits 54520119 # ITB inst hits
-system.cpu3.itb.inst_misses 59515 # ITB inst misses
+system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 43704 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin_Completed::total 43704 # Table walker requests started/completed, data/inst
+system.cpu3.itb.walker.walkRequestOrigin::total 105075 # Table walker requests started/completed, data/inst
+system.cpu3.itb.inst_hits 54222751 # ITB inst hits
+system.cpu3.itb.inst_misses 61371 # ITB inst misses
system.cpu3.itb.read_hits 0 # DTB read hits
system.cpu3.itb.read_misses 0 # DTB read misses
system.cpu3.itb.write_hits 0 # DTB write hits
system.cpu3.itb.write_misses 0 # DTB write misses
-system.cpu3.itb.flush_tlb 1179 # Number of times complete TLB was flushed
+system.cpu3.itb.flush_tlb 1183 # Number of times complete TLB was flushed
system.cpu3.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu3.itb.flush_tlb_mva_asid 11674 # Number of times TLB was flushed by MVA & ASID
-system.cpu3.itb.flush_tlb_asid 299 # Number of times TLB was flushed by ASID
-system.cpu3.itb.flush_entries 21966 # Number of entries that have been flushed from TLB
+system.cpu3.itb.flush_tlb_mva_asid 11695 # Number of times TLB was flushed by MVA & ASID
+system.cpu3.itb.flush_tlb_asid 298 # Number of times TLB was flushed by ASID
+system.cpu3.itb.flush_entries 22112 # Number of entries that have been flushed from TLB
system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu3.itb.perms_faults 118601 # Number of TLB faults due to permissions restrictions
+system.cpu3.itb.perms_faults 119556 # Number of TLB faults due to permissions restrictions
system.cpu3.itb.read_accesses 0 # DTB read accesses
system.cpu3.itb.write_accesses 0 # DTB write accesses
-system.cpu3.itb.inst_accesses 54579634 # ITB inst accesses
-system.cpu3.itb.hits 54520119 # DTB hits
-system.cpu3.itb.misses 59515 # DTB misses
-system.cpu3.itb.accesses 54579634 # DTB accesses
-system.cpu3.numCycles 361365292 # number of cpu cycles simulated
+system.cpu3.itb.inst_accesses 54284122 # ITB inst accesses
+system.cpu3.itb.hits 54222751 # DTB hits
+system.cpu3.itb.misses 61371 # DTB misses
+system.cpu3.itb.accesses 54284122 # DTB accesses
+system.cpu3.numCycles 362116242 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu3.fetch.icacheStallCycles 141188803 # Number of cycles fetch is stalled on an Icache miss
-system.cpu3.fetch.Insts 334212277 # Number of instructions fetch has processed
-system.cpu3.fetch.Branches 75157877 # Number of branches that fetch encountered
-system.cpu3.fetch.predictedBranches 46364225 # Number of branches that fetch has predicted taken
-system.cpu3.fetch.Cycles 199187397 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu3.fetch.SquashCycles 7734395 # Number of cycles fetch has spent squashing
-system.cpu3.fetch.TlbCycles 1397358 # Number of cycles fetch has spent waiting for tlb
-system.cpu3.fetch.MiscStallCycles 6420 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu3.fetch.PendingDrainCycles 2372 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu3.fetch.PendingTrapStallCycles 3033071 # Number of stall cycles due to pending traps
-system.cpu3.fetch.PendingQuiesceStallCycles 90584 # Number of stall cycles due to pending quiesce instructions
-system.cpu3.fetch.IcacheWaitRetryStallCycles 3440 # Number of stall cycles due to full MSHR
-system.cpu3.fetch.CacheLines 54384224 # Number of cache lines fetched
-system.cpu3.fetch.IcacheSquashes 2106741 # Number of outstanding Icache misses that were squashed
-system.cpu3.fetch.ItlbSquashes 23723 # Number of outstanding ITLB misses that were squashed
-system.cpu3.fetch.rateDist::samples 348776447 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::mean 1.121764 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::stdev 2.363245 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.icacheStallCycles 140692068 # Number of cycles fetch is stalled on an Icache miss
+system.cpu3.fetch.Insts 333606704 # Number of instructions fetch has processed
+system.cpu3.fetch.Branches 75051711 # Number of branches that fetch encountered
+system.cpu3.fetch.predictedBranches 46368500 # Number of branches that fetch has predicted taken
+system.cpu3.fetch.Cycles 200357205 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu3.fetch.SquashCycles 7729147 # Number of cycles fetch has spent squashing
+system.cpu3.fetch.TlbCycles 1466432 # Number of cycles fetch has spent waiting for tlb
+system.cpu3.fetch.MiscStallCycles 5775 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu3.fetch.PendingDrainCycles 2417 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu3.fetch.PendingTrapStallCycles 3039056 # Number of stall cycles due to pending traps
+system.cpu3.fetch.PendingQuiesceStallCycles 93220 # Number of stall cycles due to pending quiesce instructions
+system.cpu3.fetch.IcacheWaitRetryStallCycles 3908 # Number of stall cycles due to full MSHR
+system.cpu3.fetch.CacheLines 54085330 # Number of cache lines fetched
+system.cpu3.fetch.IcacheSquashes 2111003 # Number of outstanding Icache misses that were squashed
+system.cpu3.fetch.ItlbSquashes 24755 # Number of outstanding ITLB misses that were squashed
+system.cpu3.fetch.rateDist::samples 349524457 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::mean 1.117326 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::stdev 2.359483 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::0 266236191 76.33% 76.33% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::1 10517145 3.02% 79.35% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::2 10460372 3.00% 82.35% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::3 7763584 2.23% 84.57% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::4 15658447 4.49% 89.06% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::5 5090746 1.46% 90.52% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::6 5553519 1.59% 92.12% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::7 4863826 1.39% 93.51% # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::8 22632617 6.49% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::0 267214314 76.45% 76.45% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::1 10401691 2.98% 79.43% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::2 10376538 2.97% 82.40% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::3 7732436 2.21% 84.61% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::4 15785532 4.52% 89.12% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::5 5057577 1.45% 90.57% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::6 5498876 1.57% 92.14% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::7 4902371 1.40% 93.55% # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.rateDist::8 22555122 6.45% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.rateDist::total 348776447 # Number of instructions fetched each cycle (Total)
-system.cpu3.fetch.branchRate 0.207983 # Number of branch fetches per cycle
-system.cpu3.fetch.rate 0.924860 # Number of inst fetches per cycle
-system.cpu3.decode.IdleCycles 115165884 # Number of cycles decode is idle
-system.cpu3.decode.BlockedCycles 162148875 # Number of cycles decode is blocked
-system.cpu3.decode.RunCycles 61184358 # Number of cycles decode is running
-system.cpu3.decode.UnblockCycles 7206821 # Number of cycles decode is unblocking
-system.cpu3.decode.SquashCycles 3068716 # Number of cycles decode is squashing
-system.cpu3.decode.BranchResolved 11212761 # Number of times decode resolved a branch
-system.cpu3.decode.BranchMispred 810030 # Number of times decode detected a branch misprediction
-system.cpu3.decode.DecodedInsts 365054891 # Number of instructions handled by decode
-system.cpu3.decode.SquashedInsts 2491895 # Number of squashed instructions handled by decode
-system.cpu3.rename.SquashCycles 3068716 # Number of cycles rename is squashing
-system.cpu3.rename.IdleCycles 119377384 # Number of cycles rename is idle
-system.cpu3.rename.BlockCycles 12649358 # Number of cycles rename is blocking
-system.cpu3.rename.serializeStallCycles 130577518 # count of cycles rename stalled for serializing inst
-system.cpu3.rename.RunCycles 64081160 # Number of cycles rename is running
-system.cpu3.rename.UnblockCycles 19020412 # Number of cycles rename is unblocking
-system.cpu3.rename.RenamedInsts 356185546 # Number of instructions processed by rename
-system.cpu3.rename.ROBFullEvents 41963 # Number of times rename has blocked due to ROB full
-system.cpu3.rename.IQFullEvents 1038308 # Number of times rename has blocked due to IQ full
-system.cpu3.rename.LQFullEvents 801382 # Number of times rename has blocked due to LQ full
-system.cpu3.rename.SQFullEvents 8908900 # Number of times rename has blocked due to SQ full
-system.cpu3.rename.FullRegisterEvents 2068 # Number of times there has been no free registers
-system.cpu3.rename.RenamedOperands 339701413 # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups 543048215 # Number of register rename lookups that rename has made
-system.cpu3.rename.int_rename_lookups 420838737 # Number of integer rename lookups
-system.cpu3.rename.fp_rename_lookups 489590 # Number of floating rename lookups
-system.cpu3.rename.CommittedMaps 283499579 # Number of HB maps that are committed
-system.cpu3.rename.UndoneMaps 56201829 # Number of HB maps that are undone due to squashing
-system.cpu3.rename.serializingInsts 7935014 # count of serializing insts renamed
-system.cpu3.rename.tempSerializingInsts 6800551 # count of temporary serializing insts renamed
-system.cpu3.rename.skidInsts 39752644 # count of insts added to the skid buffer
-system.cpu3.memDep0.insertedLoads 57621684 # Number of loads inserted to the mem dependence unit.
-system.cpu3.memDep0.insertedStores 48771091 # Number of stores inserted to the mem dependence unit.
-system.cpu3.memDep0.conflictingLoads 7646320 # Number of conflicting loads.
-system.cpu3.memDep0.conflictingStores 8098105 # Number of conflicting stores.
-system.cpu3.iq.iqInstsAdded 338209447 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu3.iq.iqNonSpecInstsAdded 7991300 # Number of non-speculative instructions added to the IQ
-system.cpu3.iq.iqInstsIssued 336799958 # Number of instructions issued
-system.cpu3.iq.iqSquashedInstsIssued 493625 # Number of squashed instructions issued
-system.cpu3.iq.iqSquashedInstsExamined 46981873 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined 30279381 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu3.iq.iqSquashedNonSpecRemoved 194982 # Number of squashed non-spec instructions that were removed
-system.cpu3.iq.issued_per_cycle::samples 348776447 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::mean 0.965661 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::stdev 1.679402 # Number of insts issued each cycle
+system.cpu3.fetch.rateDist::total 349524457 # Number of instructions fetched each cycle (Total)
+system.cpu3.fetch.branchRate 0.207259 # Number of branch fetches per cycle
+system.cpu3.fetch.rate 0.921270 # Number of inst fetches per cycle
+system.cpu3.decode.IdleCycles 115102148 # Number of cycles decode is idle
+system.cpu3.decode.BlockedCycles 163151118 # Number of cycles decode is blocked
+system.cpu3.decode.RunCycles 60941298 # Number of cycles decode is running
+system.cpu3.decode.UnblockCycles 7267408 # Number of cycles decode is unblocking
+system.cpu3.decode.SquashCycles 3060603 # Number of cycles decode is squashing
+system.cpu3.decode.BranchResolved 11237446 # Number of times decode resolved a branch
+system.cpu3.decode.BranchMispred 815602 # Number of times decode detected a branch misprediction
+system.cpu3.decode.DecodedInsts 364546839 # Number of instructions handled by decode
+system.cpu3.decode.SquashedInsts 2510722 # Number of squashed instructions handled by decode
+system.cpu3.rename.SquashCycles 3060603 # Number of cycles rename is squashing
+system.cpu3.rename.IdleCycles 119327697 # Number of cycles rename is idle
+system.cpu3.rename.BlockCycles 12479500 # Number of cycles rename is blocking
+system.cpu3.rename.serializeStallCycles 131448496 # count of cycles rename stalled for serializing inst
+system.cpu3.rename.RunCycles 63890938 # Number of cycles rename is running
+system.cpu3.rename.UnblockCycles 19315280 # Number of cycles rename is unblocking
+system.cpu3.rename.RenamedInsts 355739076 # Number of instructions processed by rename
+system.cpu3.rename.ROBFullEvents 49184 # Number of times rename has blocked due to ROB full
+system.cpu3.rename.IQFullEvents 1032074 # Number of times rename has blocked due to IQ full
+system.cpu3.rename.LQFullEvents 774475 # Number of times rename has blocked due to LQ full
+system.cpu3.rename.SQFullEvents 9071524 # Number of times rename has blocked due to SQ full
+system.cpu3.rename.FullRegisterEvents 2005 # Number of times there has been no free registers
+system.cpu3.rename.RenamedOperands 339501197 # Number of destination operands rename has renamed
+system.cpu3.rename.RenameLookups 543916726 # Number of register rename lookups that rename has made
+system.cpu3.rename.int_rename_lookups 420235861 # Number of integer rename lookups
+system.cpu3.rename.fp_rename_lookups 502563 # Number of floating rename lookups
+system.cpu3.rename.CommittedMaps 283815673 # Number of HB maps that are committed
+system.cpu3.rename.UndoneMaps 55685519 # Number of HB maps that are undone due to squashing
+system.cpu3.rename.serializingInsts 8092119 # count of serializing insts renamed
+system.cpu3.rename.tempSerializingInsts 6958081 # count of temporary serializing insts renamed
+system.cpu3.rename.skidInsts 40275448 # count of insts added to the skid buffer
+system.cpu3.memDep0.insertedLoads 57221877 # Number of loads inserted to the mem dependence unit.
+system.cpu3.memDep0.insertedStores 48841814 # Number of stores inserted to the mem dependence unit.
+system.cpu3.memDep0.conflictingLoads 7500676 # Number of conflicting loads.
+system.cpu3.memDep0.conflictingStores 8056084 # Number of conflicting stores.
+system.cpu3.iq.iqInstsAdded 337690712 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu3.iq.iqNonSpecInstsAdded 8109511 # Number of non-speculative instructions added to the IQ
+system.cpu3.iq.iqInstsIssued 336678168 # Number of instructions issued
+system.cpu3.iq.iqSquashedInstsIssued 492039 # Number of squashed instructions issued
+system.cpu3.iq.iqSquashedInstsExamined 46643392 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu3.iq.iqSquashedOperandsExamined 29867606 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedNonSpecRemoved 195066 # Number of squashed non-spec instructions that were removed
+system.cpu3.iq.issued_per_cycle::samples 349524457 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::mean 0.963246 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::stdev 1.677033 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::0 218198931 62.56% 62.56% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::1 53432546 15.32% 77.88% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::2 24862182 7.13% 85.01% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::3 17747115 5.09% 90.10% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::4 13068769 3.75% 93.85% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::5 9162782 2.63% 96.47% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::6 6242831 1.79% 98.26% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::7 3634597 1.04% 99.30% # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::8 2426694 0.70% 100.00% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::0 218668838 62.56% 62.56% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::1 53919118 15.43% 77.99% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::2 24783168 7.09% 85.08% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::3 17648409 5.05% 90.13% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::4 13036700 3.73% 93.86% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::5 9178789 2.63% 96.48% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::6 6241479 1.79% 98.27% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::7 3625780 1.04% 99.31% # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::8 2422176 0.69% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu3.iq.issued_per_cycle::total 348776447 # Number of insts issued each cycle
+system.cpu3.iq.issued_per_cycle::total 349524457 # Number of insts issued each cycle
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntAlu 1722255 26.20% 26.20% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntMult 16072 0.24% 26.44% # attempts to use FU when none available
-system.cpu3.iq.fu_full::IntDiv 1128 0.02% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMisc 1 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.46% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemRead 2609788 39.70% 66.16% # attempts to use FU when none available
-system.cpu3.iq.fu_full::MemWrite 2224178 33.84% 100.00% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntAlu 1699142 25.95% 25.95% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntMult 17812 0.27% 26.22% # attempts to use FU when none available
+system.cpu3.iq.fu_full::IntDiv 1053 0.02% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatAdd 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCmp 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatCvt 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatMult 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatDiv 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAdd 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdAlu 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCmp 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdCvt 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMisc 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMult 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShift 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 26.24% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemRead 2601719 39.74% 65.97% # attempts to use FU when none available
+system.cpu3.iq.fu_full::MemWrite 2227949 34.03% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu3.iq.FU_type_0::No_OpClass 1 0.00% 0.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntAlu 228441301 67.83% 67.83% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntMult 866625 0.26% 68.08% # Type of FU issued
-system.cpu3.iq.FU_type_0::IntDiv 39602 0.01% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.10% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMisc 39134 0.01% 68.11% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.11% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.11% # Type of FU issued
-system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.11% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemRead 60438362 17.94% 86.05% # Type of FU issued
-system.cpu3.iq.FU_type_0::MemWrite 46974933 13.95% 100.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::No_OpClass 12 0.00% 0.00% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntAlu 228602725 67.90% 67.90% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntMult 820222 0.24% 68.14% # Type of FU issued
+system.cpu3.iq.FU_type_0::IntDiv 38384 0.01% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCmp 5 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.15% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMisc 43257 0.01% 68.17% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 68.17% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.17% # Type of FU issued
+system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.17% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemRead 60130906 17.86% 86.03% # Type of FU issued
+system.cpu3.iq.FU_type_0::MemWrite 47042657 13.97% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu3.iq.FU_type_0::total 336799958 # Type of FU issued
-system.cpu3.iq.rate 0.932021 # Inst issue rate
-system.cpu3.iq.fu_busy_cnt 6573422 # FU busy when requested
-system.cpu3.iq.fu_busy_rate 0.019517 # FU busy rate (busy events/executed inst)
-system.cpu3.iq.int_inst_queue_reads 1028800637 # Number of integer instruction queue reads
-system.cpu3.iq.int_inst_queue_writes 393256983 # Number of integer instruction queue writes
-system.cpu3.iq.int_inst_queue_wakeup_accesses 324790914 # Number of integer instruction queue wakeup accesses
-system.cpu3.iq.fp_inst_queue_reads 642773 # Number of floating instruction queue reads
-system.cpu3.iq.fp_inst_queue_writes 320221 # Number of floating instruction queue writes
-system.cpu3.iq.fp_inst_queue_wakeup_accesses 286838 # Number of floating instruction queue wakeup accesses
-system.cpu3.iq.int_alu_accesses 343029301 # Number of integer alu accesses
-system.cpu3.iq.fp_alu_accesses 344078 # Number of floating point alu accesses
-system.cpu3.iew.lsq.thread0.forwLoads 2684495 # Number of loads that had data forwarded from stores
+system.cpu3.iq.FU_type_0::total 336678168 # Type of FU issued
+system.cpu3.iq.rate 0.929752 # Inst issue rate
+system.cpu3.iq.fu_busy_cnt 6547675 # FU busy when requested
+system.cpu3.iq.fu_busy_rate 0.019448 # FU busy rate (busy events/executed inst)
+system.cpu3.iq.int_inst_queue_reads 1029252740 # Number of integer instruction queue reads
+system.cpu3.iq.int_inst_queue_writes 392488113 # Number of integer instruction queue writes
+system.cpu3.iq.int_inst_queue_wakeup_accesses 324616709 # Number of integer instruction queue wakeup accesses
+system.cpu3.iq.fp_inst_queue_reads 667767 # Number of floating instruction queue reads
+system.cpu3.iq.fp_inst_queue_writes 333618 # Number of floating instruction queue writes
+system.cpu3.iq.fp_inst_queue_wakeup_accesses 297362 # Number of floating instruction queue wakeup accesses
+system.cpu3.iq.int_alu_accesses 342868261 # Number of integer alu accesses
+system.cpu3.iq.fp_alu_accesses 357570 # Number of floating point alu accesses
+system.cpu3.iew.lsq.thread0.forwLoads 2662931 # Number of loads that had data forwarded from stores
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu3.iew.lsq.thread0.squashedLoads 9539540 # Number of loads squashed
-system.cpu3.iew.lsq.thread0.ignoredResponses 13050 # Number of memory responses ignored because the instruction is squashed
-system.cpu3.iew.lsq.thread0.memOrderViolation 400702 # Number of memory ordering violations
-system.cpu3.iew.lsq.thread0.squashedStores 5115949 # Number of stores squashed
+system.cpu3.iew.lsq.thread0.squashedLoads 9411324 # Number of loads squashed
+system.cpu3.iew.lsq.thread0.ignoredResponses 12714 # Number of memory responses ignored because the instruction is squashed
+system.cpu3.iew.lsq.thread0.memOrderViolation 384094 # Number of memory ordering violations
+system.cpu3.iew.lsq.thread0.squashedStores 5127738 # Number of stores squashed
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu3.iew.lsq.thread0.rescheduledLoads 2114056 # Number of loads that were rescheduled
-system.cpu3.iew.lsq.thread0.cacheBlocked 3866933 # Number of times an access to memory failed due to the cache being blocked
+system.cpu3.iew.lsq.thread0.rescheduledLoads 2090075 # Number of loads that were rescheduled
+system.cpu3.iew.lsq.thread0.cacheBlocked 3953629 # Number of times an access to memory failed due to the cache being blocked
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu3.iew.iewSquashCycles 3068716 # Number of cycles IEW is squashing
-system.cpu3.iew.iewBlockCycles 8569768 # Number of cycles IEW is blocking
-system.cpu3.iew.iewUnblockCycles 3216654 # Number of cycles IEW is unblocking
-system.cpu3.iew.iewDispatchedInsts 346278716 # Number of instructions dispatched to IQ
-system.cpu3.iew.iewDispSquashedInsts 1046515 # Number of squashed instructions skipped by dispatch
-system.cpu3.iew.iewDispLoadInsts 57621684 # Number of dispatched load instructions
-system.cpu3.iew.iewDispStoreInsts 48771091 # Number of dispatched store instructions
-system.cpu3.iew.iewDispNonSpecInsts 6645619 # Number of dispatched non-speculative instructions
-system.cpu3.iew.iewIQFullEvents 129030 # Number of times the IQ has become full, causing a stall
-system.cpu3.iew.iewLSQFullEvents 3038668 # Number of times the LSQ has become full, causing a stall
-system.cpu3.iew.memOrderViolationEvents 400702 # Number of memory order violations
-system.cpu3.iew.predictedTakenIncorrect 1583590 # Number of branches that were predicted taken incorrectly
-system.cpu3.iew.predictedNotTakenIncorrect 1353598 # Number of branches that were predicted not taken incorrectly
-system.cpu3.iew.branchMispredicts 2937188 # Number of branch mispredicts detected at execute
-system.cpu3.iew.iewExecutedInsts 332817802 # Number of executed instructions
-system.cpu3.iew.iewExecLoadInsts 59181929 # Number of load instructions executed
-system.cpu3.iew.iewExecSquashedInsts 3473252 # Number of squashed instructions skipped in execute
+system.cpu3.iew.iewSquashCycles 3060603 # Number of cycles IEW is squashing
+system.cpu3.iew.iewBlockCycles 8381523 # Number of cycles IEW is blocking
+system.cpu3.iew.iewUnblockCycles 3212246 # Number of cycles IEW is unblocking
+system.cpu3.iew.iewDispatchedInsts 345878827 # Number of instructions dispatched to IQ
+system.cpu3.iew.iewDispSquashedInsts 1059491 # Number of squashed instructions skipped by dispatch
+system.cpu3.iew.iewDispLoadInsts 57221877 # Number of dispatched load instructions
+system.cpu3.iew.iewDispStoreInsts 48841814 # Number of dispatched store instructions
+system.cpu3.iew.iewDispNonSpecInsts 6807675 # Number of dispatched non-speculative instructions
+system.cpu3.iew.iewIQFullEvents 123383 # Number of times the IQ has become full, causing a stall
+system.cpu3.iew.iewLSQFullEvents 3041851 # Number of times the LSQ has become full, causing a stall
+system.cpu3.iew.memOrderViolationEvents 384094 # Number of memory order violations
+system.cpu3.iew.predictedTakenIncorrect 1583894 # Number of branches that were predicted taken incorrectly
+system.cpu3.iew.predictedNotTakenIncorrect 1359451 # Number of branches that were predicted not taken incorrectly
+system.cpu3.iew.branchMispredicts 2943345 # Number of branch mispredicts detected at execute
+system.cpu3.iew.iewExecutedInsts 332673161 # Number of executed instructions
+system.cpu3.iew.iewExecLoadInsts 58878878 # Number of load instructions executed
+system.cpu3.iew.iewExecSquashedInsts 3493066 # Number of squashed instructions skipped in execute
system.cpu3.iew.exec_swp 0 # number of swp insts executed
-system.cpu3.iew.exec_nop 77969 # number of nop insts executed
-system.cpu3.iew.exec_refs 105520536 # number of memory reference insts executed
-system.cpu3.iew.exec_branches 61786884 # Number of branches executed
-system.cpu3.iew.exec_stores 46338607 # Number of stores executed
-system.cpu3.iew.exec_rate 0.921001 # Inst execution rate
-system.cpu3.iew.wb_sent 325791778 # cumulative count of insts sent to commit
-system.cpu3.iew.wb_count 325077752 # cumulative count of insts written-back
-system.cpu3.iew.wb_producers 160558315 # num instructions producing a value
-system.cpu3.iew.wb_consumers 278246243 # num instructions consuming a value
+system.cpu3.iew.exec_nop 78604 # number of nop insts executed
+system.cpu3.iew.exec_refs 105279838 # number of memory reference insts executed
+system.cpu3.iew.exec_branches 61795726 # Number of branches executed
+system.cpu3.iew.exec_stores 46400960 # Number of stores executed
+system.cpu3.iew.exec_rate 0.918692 # Inst execution rate
+system.cpu3.iew.wb_sent 325632326 # cumulative count of insts sent to commit
+system.cpu3.iew.wb_count 324914071 # cumulative count of insts written-back
+system.cpu3.iew.wb_producers 160314385 # num instructions producing a value
+system.cpu3.iew.wb_consumers 278113551 # num instructions consuming a value
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu3.iew.wb_rate 0.899582 # insts written-back per cycle
-system.cpu3.iew.wb_fanout 0.577037 # average fanout of values written-back
+system.cpu3.iew.wb_rate 0.897265 # insts written-back per cycle
+system.cpu3.iew.wb_fanout 0.576435 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu3.commit.commitSquashedInsts 47005398 # The number of squashed insts skipped by commit
-system.cpu3.commit.commitNonSpecStalls 7796318 # The number of times commit has been forced to stall to communicate backwards
-system.cpu3.commit.branchMispredicts 2618044 # The number of times a branch was mispredicted
-system.cpu3.commit.committed_per_cycle::samples 340807461 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::mean 0.877970 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::stdev 1.872285 # Number of insts commited each cycle
+system.cpu3.commit.commitSquashedInsts 46667653 # The number of squashed insts skipped by commit
+system.cpu3.commit.commitNonSpecStalls 7914445 # The number of times commit has been forced to stall to communicate backwards
+system.cpu3.commit.branchMispredicts 2622372 # The number of times a branch was mispredicted
+system.cpu3.commit.committed_per_cycle::samples 341617018 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::mean 0.875708 # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::stdev 1.868271 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::0 232401746 68.19% 68.19% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::1 52180181 15.31% 83.50% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::2 19062195 5.59% 89.10% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::3 8578726 2.52% 91.61% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::4 6304961 1.85% 93.46% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::5 3698650 1.09% 94.55% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::6 3483571 1.02% 95.57% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::7 2215848 0.65% 96.22% # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::8 12881583 3.78% 100.00% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::0 232826047 68.15% 68.15% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::1 52669534 15.42% 83.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::2 19043564 5.57% 89.15% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::3 8581535 2.51% 91.66% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::4 6262304 1.83% 93.49% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::5 3681580 1.08% 94.57% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::6 3506851 1.03% 95.60% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::7 2207487 0.65% 96.24% # Number of insts commited each cycle
+system.cpu3.commit.committed_per_cycle::8 12838116 3.76% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu3.commit.committed_per_cycle::total 340807461 # Number of insts commited each cycle
-system.cpu3.commit.committedInsts 254571933 # Number of instructions committed
-system.cpu3.commit.committedOps 299218869 # Number of ops (including micro ops) committed
+system.cpu3.commit.committed_per_cycle::total 341617018 # Number of insts commited each cycle
+system.cpu3.commit.committedInsts 254540187 # Number of instructions committed
+system.cpu3.commit.committedOps 299156826 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu3.commit.refs 91737285 # Number of memory references committed
-system.cpu3.commit.loads 48082143 # Number of loads committed
-system.cpu3.commit.membars 2101761 # Number of memory barriers committed
-system.cpu3.commit.branches 56830426 # Number of branches committed
-system.cpu3.commit.fp_insts 274837 # Number of committed floating point instructions.
-system.cpu3.commit.int_insts 275203911 # Number of committed integer instructions.
-system.cpu3.commit.function_calls 7606631 # Number of function calls committed.
+system.cpu3.commit.refs 91524628 # Number of memory references committed
+system.cpu3.commit.loads 47810552 # Number of loads committed
+system.cpu3.commit.membars 2044329 # Number of memory barriers committed
+system.cpu3.commit.branches 56838517 # Number of branches committed
+system.cpu3.commit.fp_insts 284474 # Number of committed floating point instructions.
+system.cpu3.commit.int_insts 274963169 # Number of committed integer instructions.
+system.cpu3.commit.function_calls 7559690 # Number of function calls committed.
system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntAlu 206755279 69.10% 69.10% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntMult 663617 0.22% 69.32% # Class of committed instruction
-system.cpu3.commit.op_class_0::IntDiv 29152 0.01% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.33% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMisc 33536 0.01% 69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.34% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemRead 48082143 16.07% 85.41% # Class of committed instruction
-system.cpu3.commit.op_class_0::MemWrite 43655142 14.59% 100.00% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntAlu 206931641 69.17% 69.17% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntMult 635252 0.21% 69.38% # Class of committed instruction
+system.cpu3.commit.op_class_0::IntDiv 28375 0.01% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatMult 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMult 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShift 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 69.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMisc 36930 0.01% 69.41% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 69.41% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 69.41% # Class of committed instruction
+system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 69.41% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemRead 47810552 15.98% 85.39% # Class of committed instruction
+system.cpu3.commit.op_class_0::MemWrite 43714076 14.61% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu3.commit.op_class_0::total 299218869 # Class of committed instruction
-system.cpu3.commit.bw_lim_events 12881583 # number cycles where commit BW limit reached
-system.cpu3.rob.rob_reads 672002413 # The number of ROB reads
-system.cpu3.rob.rob_writes 700430084 # The number of ROB writes
-system.cpu3.timesIdled 2364277 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu3.idleCycles 12588845 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu3.quiesceCycles 98652153144 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu3.committedInsts 254571933 # Number of Instructions Simulated
-system.cpu3.committedOps 299218869 # Number of Ops (including micro ops) Simulated
-system.cpu3.cpi 1.419502 # CPI: Cycles Per Instruction
-system.cpu3.cpi_total 1.419502 # CPI: Total CPI of All Threads
-system.cpu3.ipc 0.704473 # IPC: Instructions Per Cycle
-system.cpu3.ipc_total 0.704473 # IPC: Total IPC of All Threads
-system.cpu3.int_regfile_reads 392353216 # number of integer regfile reads
-system.cpu3.int_regfile_writes 232744708 # number of integer regfile writes
-system.cpu3.fp_regfile_reads 564242 # number of floating regfile reads
-system.cpu3.fp_regfile_writes 330472 # number of floating regfile writes
-system.cpu3.cc_regfile_reads 70058550 # number of cc regfile reads
-system.cpu3.cc_regfile_writes 70773135 # number of cc regfile writes
-system.cpu3.misc_regfile_reads 654632577 # number of misc regfile reads
-system.cpu3.misc_regfile_writes 7821457 # number of misc regfile writes
-system.iobus.trans_dist::ReadReq 40271 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40271 # Transaction distribution
+system.cpu3.commit.op_class_0::total 299156826 # Class of committed instruction
+system.cpu3.commit.bw_lim_events 12838116 # number cycles where commit BW limit reached
+system.cpu3.rob.rob_reads 672513030 # The number of ROB reads
+system.cpu3.rob.rob_writes 699568614 # The number of ROB writes
+system.cpu3.timesIdled 2366771 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu3.idleCycles 12591785 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu3.quiesceCycles 98718850803 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu3.committedInsts 254540187 # Number of Instructions Simulated
+system.cpu3.committedOps 299156826 # Number of Ops (including micro ops) Simulated
+system.cpu3.cpi 1.422629 # CPI: Cycles Per Instruction
+system.cpu3.cpi_total 1.422629 # CPI: Total CPI of All Threads
+system.cpu3.ipc 0.702924 # IPC: Instructions Per Cycle
+system.cpu3.ipc_total 0.702924 # IPC: Total IPC of All Threads
+system.cpu3.int_regfile_reads 392099204 # number of integer regfile reads
+system.cpu3.int_regfile_writes 232294349 # number of integer regfile writes
+system.cpu3.fp_regfile_reads 578128 # number of floating regfile reads
+system.cpu3.fp_regfile_writes 349384 # number of floating regfile writes
+system.cpu3.cc_regfile_reads 70503993 # number of cc regfile reads
+system.cpu3.cc_regfile_writes 71192448 # number of cc regfile writes
+system.cpu3.misc_regfile_reads 655577760 # number of misc regfile reads
+system.cpu3.misc_regfile_writes 7960975 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 40269 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40269 # Transaction distribution
system.iobus.trans_dist::WriteReq 136539 # Transaction distribution
system.iobus.trans_dist::WriteResp 136539 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 47694 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 122576 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230964 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 230964 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 230960 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 230960 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 353620 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 353616 # Packet count per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 47714 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.bridge.master::total 155706 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334288 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7334288 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7334272 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 7334272 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7492080 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 7492064 # Cumulative packet size per connected master and slave (bytes)
system.iobus.reqLayer0.occupancy 14862000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 10428000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.occupancy 10142000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer24.occupancy 45000 # Layer occupancy (ticks)
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer26.occupancy 30000 # Layer occupancy (ticks)
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 246351678 # Layer occupancy (ticks)
+system.iobus.reqLayer27.occupancy 244315631 # Layer occupancy (ticks)
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 45146000 # Layer occupancy (ticks)
+system.iobus.respLayer0.occupancy 45003000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 48770000 # Layer occupancy (ticks)
+system.iobus.respLayer3.occupancy 69196000 # Layer occupancy (ticks)
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115464 # number of replacements
-system.iocache.tags.tagsinuse 10.421022 # Cycle average of tags in use
+system.iocache.tags.replacements 115462 # number of replacements
+system.iocache.tags.tagsinuse 10.425339 # Cycle average of tags in use
system.iocache.tags.total_refs 3 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 115480 # Sample count of references to valid blocks.
+system.iocache.tags.sampled_refs 115478 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000026 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 13087689851509 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ethernet 3.547375 # Average occupied blocks per requestor
-system.iocache.tags.occ_blocks::realview.ide 6.873647 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ethernet 0.221711 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::realview.ide 0.429603 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.651314 # Average percentage of cache occupancy
+system.iocache.tags.warmup_cycle 13087689855509 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ethernet 3.544644 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 6.880695 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ethernet 0.221540 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::realview.ide 0.430043 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.651584 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 1039695 # Number of tag accesses
-system.iocache.tags.data_accesses 1039695 # Number of data accesses
+system.iocache.tags.tag_accesses 1039677 # Number of tag accesses
+system.iocache.tags.data_accesses 1039677 # Number of data accesses
system.iocache.ReadReq_misses::realview.ethernet 37 # number of ReadReq misses
-system.iocache.ReadReq_misses::realview.ide 8818 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 8855 # number of ReadReq misses
+system.iocache.ReadReq_misses::realview.ide 8816 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 8853 # number of ReadReq misses
system.iocache.WriteReq_misses::realview.ethernet 3 # number of WriteReq misses
system.iocache.WriteReq_misses::total 3 # number of WriteReq misses
system.iocache.WriteLineReq_misses::realview.ide 106664 # number of WriteLineReq misses
system.iocache.WriteLineReq_misses::total 106664 # number of WriteLineReq misses
system.iocache.demand_misses::realview.ethernet 40 # number of demand (read+write) misses
-system.iocache.demand_misses::realview.ide 8818 # number of demand (read+write) misses
-system.iocache.demand_misses::total 8858 # number of demand (read+write) misses
+system.iocache.demand_misses::realview.ide 8816 # number of demand (read+write) misses
+system.iocache.demand_misses::total 8856 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ethernet 40 # number of overall misses
-system.iocache.overall_misses::realview.ide 8818 # number of overall misses
-system.iocache.overall_misses::total 8858 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 66023672 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 66023672 # number of ReadReq miss cycles
-system.iocache.WriteLineReq_miss_latency::realview.ide 5601261006 # number of WriteLineReq miss cycles
-system.iocache.WriteLineReq_miss_latency::total 5601261006 # number of WriteLineReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 66023672 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 66023672 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 66023672 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 66023672 # number of overall miss cycles
+system.iocache.overall_misses::realview.ide 8816 # number of overall misses
+system.iocache.overall_misses::total 8856 # number of overall misses
+system.iocache.ReadReq_miss_latency::realview.ide 902834218 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 902834218 # number of ReadReq miss cycles
+system.iocache.WriteLineReq_miss_latency::realview.ide 5365256413 # number of WriteLineReq miss cycles
+system.iocache.WriteLineReq_miss_latency::total 5365256413 # number of WriteLineReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 902834218 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 902834218 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 902834218 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 902834218 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ethernet 37 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::realview.ide 8818 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 8855 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::realview.ide 8816 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 8853 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::realview.ethernet 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 3 # number of WriteReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::realview.ide 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.WriteLineReq_accesses::total 106664 # number of WriteLineReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ethernet 40 # number of demand (read+write) accesses
-system.iocache.demand_accesses::realview.ide 8818 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 8858 # number of demand (read+write) accesses
+system.iocache.demand_accesses::realview.ide 8816 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 8856 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ethernet 40 # number of overall (read+write) accesses
-system.iocache.overall_accesses::realview.ide 8818 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 8858 # number of overall (read+write) accesses
+system.iocache.overall_accesses::realview.ide 8816 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 8856 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ethernet 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.overall_miss_rate::realview.ethernet 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 7487.374915 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 7456.089441 # average ReadReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::realview.ide 52513.134760 # average WriteLineReq miss latency
-system.iocache.WriteLineReq_avg_miss_latency::total 52513.134760 # average WriteLineReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 7487.374915 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 7453.564236 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 7487.374915 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 7453.564236 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 432 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::realview.ide 102408.600045 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 101980.596182 # average ReadReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::realview.ide 50300.536385 # average WriteLineReq miss latency
+system.iocache.WriteLineReq_avg_miss_latency::total 50300.536385 # average WriteLineReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 102408.600045 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 101946.049910 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 102408.600045 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 101946.049910 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 17834 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 47 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 1976 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 9.191489 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 9.025304 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 106631 # number of writebacks
system.iocache.writebacks::total 106631 # number of writebacks
-system.iocache.ReadReq_mshr_misses::realview.ide 493 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 493 # number of ReadReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::realview.ide 47400 # number of WriteLineReq MSHR misses
-system.iocache.WriteLineReq_mshr_misses::total 47400 # number of WriteLineReq MSHR misses
-system.iocache.demand_mshr_misses::realview.ide 493 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 493 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::realview.ide 493 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 493 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 41373672 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 41373672 # number of ReadReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3231261006 # number of WriteLineReq MSHR miss cycles
-system.iocache.WriteLineReq_mshr_miss_latency::total 3231261006 # number of WriteLineReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 41373672 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 41373672 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 41373672 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 41373672 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.055908 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 0.055675 # mshr miss rate for ReadReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.444386 # mshr miss rate for WriteLineReq accesses
-system.iocache.WriteLineReq_mshr_miss_rate::total 0.444386 # mshr miss rate for WriteLineReq accesses
-system.iocache.demand_mshr_miss_rate::realview.ide 0.055908 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 0.055656 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::realview.ide 0.055908 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 0.055656 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83922.255578 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 83922.255578 # average ReadReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68170.063418 # average WriteLineReq mshr miss latency
-system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68170.063418 # average WriteLineReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 83922.255578 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 83922.255578 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 83922.255578 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 83922.255578 # average overall mshr miss latency
+system.iocache.ReadReq_mshr_misses::realview.ide 4982 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 4982 # number of ReadReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::realview.ide 45408 # number of WriteLineReq MSHR misses
+system.iocache.WriteLineReq_mshr_misses::total 45408 # number of WriteLineReq MSHR misses
+system.iocache.demand_mshr_misses::realview.ide 4982 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 4982 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::realview.ide 4982 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 4982 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 653734218 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 653734218 # number of ReadReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 3094856413 # number of WriteLineReq MSHR miss cycles
+system.iocache.WriteLineReq_mshr_miss_latency::total 3094856413 # number of WriteLineReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 653734218 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 653734218 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 653734218 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 653734218 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.565109 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 0.562747 # mshr miss rate for ReadReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 0.425711 # mshr miss rate for WriteLineReq accesses
+system.iocache.WriteLineReq_mshr_miss_rate::total 0.425711 # mshr miss rate for WriteLineReq accesses
+system.iocache.demand_mshr_miss_rate::realview.ide 0.565109 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 0.562556 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::realview.ide 0.565109 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 0.562556 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 131219.232838 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 131219.232838 # average ReadReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68156.633479 # average WriteLineReq mshr miss latency
+system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68156.633479 # average WriteLineReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 131219.232838 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 131219.232838 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 131219.232838 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 131219.232838 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.l2c.tags.replacements 1178201 # number of replacements
-system.l2c.tags.tagsinuse 65342.536635 # Cycle average of tags in use
-system.l2c.tags.total_refs 47533778 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1240935 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 38.304809 # Average number of references to valid blocks.
+system.l2c.tags.replacements 1197494 # number of replacements
+system.l2c.tags.tagsinuse 65334.177646 # Cycle average of tags in use
+system.l2c.tags.total_refs 47583797 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 1260356 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 37.754251 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 395986000 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 36457.259516 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 134.391742 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 206.626869 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 3141.459987 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 10234.454405 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 42.556098 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 61.614862 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 851.307108 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 2279.755035 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 36.540857 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.itb.walker 56.575168 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 1930.782572 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 2582.079000 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.dtb.walker 98.957647 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.itb.walker 152.820118 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst 2413.377960 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data 4661.977691 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.556294 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.002051 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.003153 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.047935 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.156165 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000649 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.000940 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.012990 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.034786 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000558 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.itb.walker 0.000863 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst 0.029461 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data 0.039399 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001510 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.itb.walker 0.002332 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst 0.036825 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data 0.071136 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.997048 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 348 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 62386 # Occupied blocks per task id
+system.l2c.tags.occ_blocks::writebacks 36625.887647 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 129.652823 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 192.600178 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 3297.722493 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 10271.458508 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.360816 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.itb.walker 62.862423 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 734.403230 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 2295.121948 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.dtb.walker 38.166542 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.itb.walker 55.564036 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst 2274.574548 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data 3138.217003 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.dtb.walker 98.389522 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.itb.walker 140.202266 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst 1940.354614 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data 3994.639050 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.558867 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001978 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker 0.002939 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.050319 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data 0.156730 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000677 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.itb.walker 0.000959 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.011206 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data 0.035021 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000582 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.itb.walker 0.000848 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst 0.034707 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data 0.047885 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.dtb.walker 0.001501 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.itb.walker 0.002139 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst 0.029607 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data 0.060953 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.996920 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1023 305 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_blocks::1024 62557 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 346 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 117 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 559 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 2832 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 5180 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 53698 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.005310 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.951935 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 421030068 # Number of tag accesses
-system.l2c.tags.data_accesses 421030068 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 160105 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 111071 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 55142 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 41666 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.dtb.walker 153356 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.itb.walker 57206 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.dtb.walker 292962 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.itb.walker 104864 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 976372 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 7548701 # number of Writeback hits
-system.l2c.Writeback_hits::total 7548701 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 3766 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 1252 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu2.data 1641 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu3.data 2803 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 9462 # number of UpgradeReq hits
+system.l2c.tags.age_task_id_blocks_1023::4 304 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 569 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 2827 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 5128 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::4 53917 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1023 0.004654 # Percentage of cache occupancy per task id
+system.l2c.tags.occ_task_id_percent::1024 0.954544 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 421629401 # Number of tag accesses
+system.l2c.tags.data_accesses 421629401 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0.dtb.walker 162534 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker 110569 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker 55382 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker 41930 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.dtb.walker 157494 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.itb.walker 59360 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.dtb.walker 299154 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.itb.walker 112124 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 998547 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 7530303 # number of Writeback hits
+system.l2c.Writeback_hits::total 7530303 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 3865 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 1247 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2.data 1535 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3.data 2775 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 9422 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu3.data 2 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 634186 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 200968 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu2.data 288741 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu3.data 458130 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 1582025 # number of ReadExReq hits
-system.l2c.ReadCleanReq_hits::cpu0.inst 5488344 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu1.inst 1694582 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu2.inst 3854361 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::cpu3.inst 4648089 # number of ReadCleanReq hits
-system.l2c.ReadCleanReq_hits::total 15685376 # number of ReadCleanReq hits
-system.l2c.ReadSharedReq_hits::cpu0.data 2558848 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu1.data 765070 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu2.data 1053468 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::cpu3.data 1902951 # number of ReadSharedReq hits
-system.l2c.ReadSharedReq_hits::total 6280337 # number of ReadSharedReq hits
-system.l2c.InvalidateReq_hits::cpu0.data 284863 # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu1.data 96754 # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu2.data 124346 # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::cpu3.data 225674 # number of InvalidateReq hits
-system.l2c.InvalidateReq_hits::total 731637 # number of InvalidateReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 160105 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 111071 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 5488344 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 3193034 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 55142 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 41666 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 1694582 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 966038 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.dtb.walker 153356 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.itb.walker 57206 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst 3854361 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data 1342209 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.dtb.walker 292962 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.itb.walker 104864 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst 4648089 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data 2361081 # number of demand (read+write) hits
-system.l2c.demand_hits::total 24524110 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 160105 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 111071 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 5488344 # number of overall hits
-system.l2c.overall_hits::cpu0.data 3193034 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 55142 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 41666 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 1694582 # number of overall hits
-system.l2c.overall_hits::cpu1.data 966038 # number of overall hits
-system.l2c.overall_hits::cpu2.dtb.walker 153356 # number of overall hits
-system.l2c.overall_hits::cpu2.itb.walker 57206 # number of overall hits
-system.l2c.overall_hits::cpu2.inst 3854361 # number of overall hits
-system.l2c.overall_hits::cpu2.data 1342209 # number of overall hits
-system.l2c.overall_hits::cpu3.dtb.walker 292962 # number of overall hits
-system.l2c.overall_hits::cpu3.itb.walker 104864 # number of overall hits
-system.l2c.overall_hits::cpu3.inst 4648089 # number of overall hits
-system.l2c.overall_hits::cpu3.data 2361081 # number of overall hits
-system.l2c.overall_hits::total 24524110 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 1302 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker 1407 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 317 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker 303 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.dtb.walker 507 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.itb.walker 452 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.dtb.walker 1016 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.itb.walker 958 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 6262 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 13735 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 4483 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data 5785 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data 10296 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 34299 # number of UpgradeReq misses
+system.l2c.ReadExReq_hits::cpu0.data 634082 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 192446 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2.data 277703 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3.data 471607 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 1575838 # number of ReadExReq hits
+system.l2c.ReadCleanReq_hits::cpu0.inst 5493197 # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu1.inst 1685224 # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu2.inst 3887506 # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::cpu3.inst 4647283 # number of ReadCleanReq hits
+system.l2c.ReadCleanReq_hits::total 15713210 # number of ReadCleanReq hits
+system.l2c.ReadSharedReq_hits::cpu0.data 2580953 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu1.data 758591 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu2.data 1060227 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::cpu3.data 1868057 # number of ReadSharedReq hits
+system.l2c.ReadSharedReq_hits::total 6267828 # number of ReadSharedReq hits
+system.l2c.InvalidateReq_hits::cpu0.data 284671 # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu1.data 86494 # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu2.data 126322 # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::cpu3.data 229482 # number of InvalidateReq hits
+system.l2c.InvalidateReq_hits::total 726969 # number of InvalidateReq hits
+system.l2c.demand_hits::cpu0.dtb.walker 162534 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker 110569 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 5493197 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 3215035 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker 55382 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker 41930 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 1685224 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 951037 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.dtb.walker 157494 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.itb.walker 59360 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst 3887506 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 1337930 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.dtb.walker 299154 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.itb.walker 112124 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst 4647283 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data 2339664 # number of demand (read+write) hits
+system.l2c.demand_hits::total 24555423 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.dtb.walker 162534 # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker 110569 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 5493197 # number of overall hits
+system.l2c.overall_hits::cpu0.data 3215035 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 55382 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 41930 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 1685224 # number of overall hits
+system.l2c.overall_hits::cpu1.data 951037 # number of overall hits
+system.l2c.overall_hits::cpu2.dtb.walker 157494 # number of overall hits
+system.l2c.overall_hits::cpu2.itb.walker 59360 # number of overall hits
+system.l2c.overall_hits::cpu2.inst 3887506 # number of overall hits
+system.l2c.overall_hits::cpu2.data 1337930 # number of overall hits
+system.l2c.overall_hits::cpu3.dtb.walker 299154 # number of overall hits
+system.l2c.overall_hits::cpu3.itb.walker 112124 # number of overall hits
+system.l2c.overall_hits::cpu3.inst 4647283 # number of overall hits
+system.l2c.overall_hits::cpu3.data 2339664 # number of overall hits
+system.l2c.overall_hits::total 24555423 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 1348 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker 1360 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 417 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker 408 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.dtb.walker 426 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.itb.walker 363 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.dtb.walker 1018 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.itb.walker 932 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 6272 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 14062 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 4585 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data 5739 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data 9908 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 34294 # number of UpgradeReq misses
system.l2c.SCUpgradeReq_misses::cpu3.data 2 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 182889 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 49078 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data 67882 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data 112079 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 411928 # number of ReadExReq misses
-system.l2c.ReadCleanReq_misses::cpu0.inst 34930 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu1.inst 10925 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu2.inst 24031 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::cpu3.inst 28031 # number of ReadCleanReq misses
-system.l2c.ReadCleanReq_misses::total 97917 # number of ReadCleanReq misses
-system.l2c.ReadSharedReq_misses::cpu0.data 117851 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu1.data 29685 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu2.data 38310 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::cpu3.data 75808 # number of ReadSharedReq misses
-system.l2c.ReadSharedReq_misses::total 261654 # number of ReadSharedReq misses
-system.l2c.InvalidateReq_misses::cpu0.data 382135 # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu1.data 17981 # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu2.data 28569 # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::cpu3.data 64895 # number of InvalidateReq misses
-system.l2c.InvalidateReq_misses::total 493580 # number of InvalidateReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 1302 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 1407 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 34930 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 300740 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.dtb.walker 317 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.itb.walker 303 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst 10925 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 78763 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.dtb.walker 507 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.itb.walker 452 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst 24031 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data 106192 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.dtb.walker 1016 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.itb.walker 958 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst 28031 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data 187887 # number of demand (read+write) misses
-system.l2c.demand_misses::total 777761 # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.dtb.walker 1302 # number of overall misses
-system.l2c.overall_misses::cpu0.itb.walker 1407 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 34930 # number of overall misses
-system.l2c.overall_misses::cpu0.data 300740 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 317 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 303 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 10925 # number of overall misses
-system.l2c.overall_misses::cpu1.data 78763 # number of overall misses
-system.l2c.overall_misses::cpu2.dtb.walker 507 # number of overall misses
-system.l2c.overall_misses::cpu2.itb.walker 452 # number of overall misses
-system.l2c.overall_misses::cpu2.inst 24031 # number of overall misses
-system.l2c.overall_misses::cpu2.data 106192 # number of overall misses
-system.l2c.overall_misses::cpu3.dtb.walker 1016 # number of overall misses
-system.l2c.overall_misses::cpu3.itb.walker 958 # number of overall misses
-system.l2c.overall_misses::cpu3.inst 28031 # number of overall misses
-system.l2c.overall_misses::cpu3.data 187887 # number of overall misses
-system.l2c.overall_misses::total 777761 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 27522500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker 26481000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 43212000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu2.itb.walker 38388000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 88884500 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu3.itb.walker 86213000 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::total 310701000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu1.data 68441500 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu2.data 90805000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::cpu3.data 164582000 # number of UpgradeReq miss cycles
-system.l2c.UpgradeReq_miss_latency::total 323828500 # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_misses::cpu0.data 188559 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 51076 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data 66860 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data 112125 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 418620 # number of ReadExReq misses
+system.l2c.ReadCleanReq_misses::cpu0.inst 35995 # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu1.inst 10966 # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu2.inst 27651 # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::cpu3.inst 28085 # number of ReadCleanReq misses
+system.l2c.ReadCleanReq_misses::total 102697 # number of ReadCleanReq misses
+system.l2c.ReadSharedReq_misses::cpu0.data 119057 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu1.data 33042 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu2.data 40134 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::cpu3.data 73982 # number of ReadSharedReq misses
+system.l2c.ReadSharedReq_misses::total 266215 # number of ReadSharedReq misses
+system.l2c.InvalidateReq_misses::cpu0.data 383686 # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu1.data 19000 # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu2.data 28887 # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::cpu3.data 66669 # number of InvalidateReq misses
+system.l2c.InvalidateReq_misses::total 498242 # number of InvalidateReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 1348 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker 1360 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 35995 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 307616 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 417 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker 408 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 10966 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 84118 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.dtb.walker 426 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.itb.walker 363 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst 27651 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data 106994 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.dtb.walker 1018 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.itb.walker 932 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst 28085 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data 186107 # number of demand (read+write) misses
+system.l2c.demand_misses::total 793804 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 1348 # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker 1360 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 35995 # number of overall misses
+system.l2c.overall_misses::cpu0.data 307616 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 417 # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker 408 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 10966 # number of overall misses
+system.l2c.overall_misses::cpu1.data 84118 # number of overall misses
+system.l2c.overall_misses::cpu2.dtb.walker 426 # number of overall misses
+system.l2c.overall_misses::cpu2.itb.walker 363 # number of overall misses
+system.l2c.overall_misses::cpu2.inst 27651 # number of overall misses
+system.l2c.overall_misses::cpu2.data 106994 # number of overall misses
+system.l2c.overall_misses::cpu3.dtb.walker 1018 # number of overall misses
+system.l2c.overall_misses::cpu3.itb.walker 932 # number of overall misses
+system.l2c.overall_misses::cpu3.inst 28085 # number of overall misses
+system.l2c.overall_misses::cpu3.data 186107 # number of overall misses
+system.l2c.overall_misses::total 793804 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 35190000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker 35160000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 36174500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.itb.walker 31569500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.dtb.walker 89352000 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.itb.walker 82579500 # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total 310025500 # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data 68776500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data 92773000 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3.data 156127500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 317677000 # number of UpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::cpu3.data 81000 # number of SCUpgradeReq miss cycles
system.l2c.SCUpgradeReq_miss_latency::total 81000 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu1.data 3953928500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu2.data 5507688000 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::cpu3.data 10998115500 # number of ReadExReq miss cycles
-system.l2c.ReadExReq_miss_latency::total 20459732000 # number of ReadExReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu1.inst 888341500 # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu2.inst 1996189000 # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2389519000 # number of ReadCleanReq miss cycles
-system.l2c.ReadCleanReq_miss_latency::total 5274049500 # number of ReadCleanReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu1.data 2457700500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu2.data 3192549500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::cpu3.data 6788552500 # number of ReadSharedReq miss cycles
-system.l2c.ReadSharedReq_miss_latency::total 12438802500 # number of ReadSharedReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu1.data 1429563000 # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu2.data 2523386500 # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::cpu3.data 6994477500 # number of InvalidateReq miss cycles
-system.l2c.InvalidateReq_miss_latency::total 10947427000 # number of InvalidateReq miss cycles
-system.l2c.demand_miss_latency::cpu1.dtb.walker 27522500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.itb.walker 26481000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.inst 888341500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu1.data 6411629000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.dtb.walker 43212000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.itb.walker 38388000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.inst 1996189000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu2.data 8700237500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.dtb.walker 88884500 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.itb.walker 86213000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.inst 2389519000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::cpu3.data 17786668000 # number of demand (read+write) miss cycles
-system.l2c.demand_miss_latency::total 38483285000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency::cpu1.dtb.walker 27522500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.itb.walker 26481000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.inst 888341500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu1.data 6411629000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.dtb.walker 43212000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.itb.walker 38388000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.inst 1996189000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu2.data 8700237500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.dtb.walker 88884500 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.itb.walker 86213000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.inst 2389519000 # number of overall miss cycles
-system.l2c.overall_miss_latency::cpu3.data 17786668000 # number of overall miss cycles
-system.l2c.overall_miss_latency::total 38483285000 # number of overall miss cycles
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 161407 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.itb.walker 112478 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 55459 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 41969 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.dtb.walker 153863 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.itb.walker 57658 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.dtb.walker 293978 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.itb.walker 105822 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 982634 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 7548701 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 7548701 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 17501 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 5735 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data 7426 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data 13099 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 43761 # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_miss_latency::cpu1.data 4115650000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data 5398260500 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data 10994713000 # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total 20508623500 # number of ReadExReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu1.inst 887226500 # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu2.inst 2301476500 # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2388363000 # number of ReadCleanReq miss cycles
+system.l2c.ReadCleanReq_miss_latency::total 5577066000 # number of ReadCleanReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu1.data 2751846000 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu2.data 3344905000 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::cpu3.data 6580498500 # number of ReadSharedReq miss cycles
+system.l2c.ReadSharedReq_miss_latency::total 12677249500 # number of ReadSharedReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu1.data 1513300000 # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu2.data 2542083000 # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::cpu3.data 7155981000 # number of InvalidateReq miss cycles
+system.l2c.InvalidateReq_miss_latency::total 11211364000 # number of InvalidateReq miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker 35190000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker 35160000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst 887226500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data 6867496000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.dtb.walker 36174500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.itb.walker 31569500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst 2301476500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data 8743165500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.dtb.walker 89352000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.itb.walker 82579500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst 2388363000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data 17575211500 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 39072964500 # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker 35190000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker 35160000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst 887226500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data 6867496000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.dtb.walker 36174500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.itb.walker 31569500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst 2301476500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data 8743165500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.dtb.walker 89352000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.itb.walker 82579500 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst 2388363000 # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data 17575211500 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 39072964500 # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 163882 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 111929 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 55799 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 42338 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.dtb.walker 157920 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.itb.walker 59723 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.dtb.walker 300172 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.itb.walker 113056 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 1004819 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 7530303 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 7530303 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 17927 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 5832 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data 7274 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data 12683 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 43716 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu3.data 4 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 817075 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 250046 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data 356623 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data 570209 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 1993953 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu0.inst 5523274 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu1.inst 1705507 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu2.inst 3878392 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::cpu3.inst 4676120 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadCleanReq_accesses::total 15783293 # number of ReadCleanReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu0.data 2676699 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu1.data 794755 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu2.data 1091778 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::cpu3.data 1978759 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.ReadSharedReq_accesses::total 6541991 # number of ReadSharedReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu0.data 666998 # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu1.data 114735 # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu2.data 152915 # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::cpu3.data 290569 # number of InvalidateReq accesses(hits+misses)
-system.l2c.InvalidateReq_accesses::total 1225217 # number of InvalidateReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 161407 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 112478 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 5523274 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 3493774 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 55459 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 41969 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 1705507 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 1044801 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.dtb.walker 153863 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.itb.walker 57658 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst 3878392 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data 1448401 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.dtb.walker 293978 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.itb.walker 105822 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst 4676120 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data 2548968 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 25301871 # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.dtb.walker 161407 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.itb.walker 112478 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst 5523274 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 3493774 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.dtb.walker 55459 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.itb.walker 41969 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 1705507 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 1044801 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.dtb.walker 153863 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.itb.walker 57658 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst 3878392 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data 1448401 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.dtb.walker 293978 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.itb.walker 105822 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst 4676120 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data 2548968 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 25301871 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.008067 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012509 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.005716 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.007220 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003295 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.007839 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003456 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.009053 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.006373 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784812 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.781691 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data 0.779020 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data 0.786014 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.783780 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_accesses::cpu0.data 822641 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 243522 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data 344563 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data 583732 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 1994458 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu0.inst 5529192 # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu1.inst 1696190 # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu2.inst 3915157 # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::cpu3.inst 4675368 # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadCleanReq_accesses::total 15815907 # number of ReadCleanReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu0.data 2700010 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu1.data 791633 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu2.data 1100361 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::cpu3.data 1942039 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.ReadSharedReq_accesses::total 6534043 # number of ReadSharedReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu0.data 668357 # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu1.data 105494 # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu2.data 155209 # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::cpu3.data 296151 # number of InvalidateReq accesses(hits+misses)
+system.l2c.InvalidateReq_accesses::total 1225211 # number of InvalidateReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 163882 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 111929 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 5529192 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 3522651 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 55799 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 42338 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 1696190 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 1035155 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.dtb.walker 157920 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.itb.walker 59723 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst 3915157 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data 1444924 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.dtb.walker 300172 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.itb.walker 113056 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst 4675368 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data 2525771 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 25349227 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 163882 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 111929 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 5529192 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 3522651 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 55799 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 42338 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 1696190 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 1035155 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.dtb.walker 157920 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.itb.walker 59723 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst 3915157 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data 1444924 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.dtb.walker 300172 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.itb.walker 113056 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst 4675368 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data 2525771 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 25349227 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.008225 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.012151 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.007473 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.009637 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.002698 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.006078 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.dtb.walker 0.003391 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.itb.walker 0.008244 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.006242 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.784403 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.786180 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data 0.788974 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data 0.781203 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.784473 # miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::cpu3.data 0.500000 # miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_miss_rate::total 0.500000 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.223834 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.196276 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data 0.190347 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data 0.196558 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.206589 # miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006324 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.006406 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.006196 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.005994 # miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_miss_rate::total 0.006204 # miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.044028 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.037351 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.035090 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.038311 # miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_miss_rate::total 0.039996 # miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu0.data 0.572918 # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu1.data 0.156718 # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu2.data 0.186829 # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::cpu3.data 0.223338 # miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_miss_rate::total 0.402851 # miss rate for InvalidateReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.008067 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.012509 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.006324 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.086079 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.005716 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.itb.walker 0.007220 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.006406 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.075386 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003295 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.itb.walker 0.007839 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst 0.006196 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data 0.073317 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003456 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.itb.walker 0.009053 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst 0.005994 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data 0.073711 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.030739 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.008067 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.012509 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.006324 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.086079 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.005716 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.itb.walker 0.007220 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.006406 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.075386 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003295 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.itb.walker 0.007839 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst 0.006196 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data 0.073317 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003456 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.itb.walker 0.009053 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst 0.005994 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data 0.073711 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.030739 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 86821.766562 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 87396.039604 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 85230.769231 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 84929.203540 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 87484.744094 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 89992.693111 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 49616.895561 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15266.897167 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 15696.629213 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 15985.042735 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 9441.339398 # average UpgradeReq miss latency
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.229212 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.209739 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data 0.194043 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data 0.192083 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.209892 # miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.006510 # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.006465 # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.007063 # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.006007 # miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_miss_rate::total 0.006493 # miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.044095 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.041739 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.036473 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.038095 # miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_miss_rate::total 0.040743 # miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu0.data 0.574073 # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu1.data 0.180105 # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu2.data 0.186117 # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::cpu3.data 0.225118 # miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_miss_rate::total 0.406658 # miss rate for InvalidateReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.008225 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.012151 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.006510 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.087325 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.007473 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker 0.009637 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.006465 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.081261 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.dtb.walker 0.002698 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.itb.walker 0.006078 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst 0.007063 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data 0.074048 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.dtb.walker 0.003391 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.itb.walker 0.008244 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst 0.006007 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data 0.073683 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.031315 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.008225 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.012151 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.006510 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.087325 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.007473 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker 0.009637 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.006465 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.081261 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.dtb.walker 0.002698 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.itb.walker 0.006078 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst 0.007063 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data 0.074048 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.dtb.walker 0.003391 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.itb.walker 0.008244 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst 0.006007 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data 0.073683 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.031315 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 84388.489209 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 86176.470588 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 84916.666667 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 86968.319559 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.dtb.walker 87772.102161 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.itb.walker 88604.613734 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::total 49430.086097 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 15000.327154 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 16165.359819 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data 15757.721034 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::total 9263.340526 # average UpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::cpu3.data 40500 # average SCUpgradeReq miss latency
system.l2c.SCUpgradeReq_avg_miss_latency::total 40500 # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80564.173357 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu2.data 81136.206947 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::cpu3.data 98128.244363 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 49668.223573 # average ReadExReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 81312.723112 # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83067.246473 # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 85245.585245 # average ReadCleanReq miss latency
-system.l2c.ReadCleanReq_avg_miss_latency::total 53862.449830 # average ReadCleanReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 82792.673067 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83334.625424 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 89549.288993 # average ReadSharedReq miss latency
-system.l2c.ReadSharedReq_avg_miss_latency::total 47539.126098 # average ReadSharedReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79504.087648 # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 88326.035213 # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 107781.454658 # average InvalidateReq miss latency
-system.l2c.InvalidateReq_avg_miss_latency::total 22179.640585 # average InvalidateReq miss latency
-system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 86821.766562 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.itb.walker 87396.039604 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.inst 81312.723112 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu1.data 81404.072978 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 85230.769231 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.itb.walker 84929.203540 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.inst 83067.246473 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu2.data 81929.312001 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 87484.744094 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.itb.walker 89992.693111 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.inst 85245.585245 # average overall miss latency
-system.l2c.demand_avg_miss_latency::cpu3.data 94666.836982 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 49479.576631 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 86821.766562 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.itb.walker 87396.039604 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 81312.723112 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.data 81404.072978 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 85230.769231 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.itb.walker 84929.203540 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.inst 83067.246473 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu2.data 81929.312001 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 87484.744094 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.itb.walker 89992.693111 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.inst 85245.585245 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu3.data 94666.836982 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 49479.576631 # average overall miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 80578.941186 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 80739.762190 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 98057.641026 # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::total 48991.026468 # average ReadExReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 80907.030823 # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 83233.029547 # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 85040.519850 # average ReadCleanReq miss latency
+system.l2c.ReadCleanReq_avg_miss_latency::total 54306.026466 # average ReadCleanReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 83283.275831 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 83343.424528 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 88947.291233 # average ReadSharedReq miss latency
+system.l2c.ReadSharedReq_avg_miss_latency::total 47620.342580 # average ReadSharedReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu1.data 79647.368421 # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu2.data 88000.934676 # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::cpu3.data 107335.958241 # average InvalidateReq miss latency
+system.l2c.InvalidateReq_avg_miss_latency::total 22501.844485 # average InvalidateReq miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 84388.489209 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 86176.470588 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 80907.030823 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 81641.218289 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 84916.666667 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.itb.walker 86968.319559 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 83233.029547 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data 81716.409331 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.dtb.walker 87772.102161 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.itb.walker 88604.613734 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 85040.519850 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 94436.058289 # average overall miss latency
+system.l2c.demand_avg_miss_latency::total 49222.433371 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 84388.489209 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 86176.470588 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 80907.030823 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 81641.218289 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 84916.666667 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.itb.walker 86968.319559 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 83233.029547 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data 81716.409331 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.dtb.walker 87772.102161 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.itb.walker 88604.613734 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 85040.519850 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 94436.058289 # average overall miss latency
+system.l2c.overall_avg_miss_latency::total 49222.433371 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 982136 # number of writebacks
-system.l2c.writebacks::total 982136 # number of writebacks
-system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker 4 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::cpu3.itb.walker 15 # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_hits::total 19 # number of ReadReq MSHR hits
+system.l2c.writebacks::writebacks 991802 # number of writebacks
+system.l2c.writebacks::total 991802 # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu3.dtb.walker 9 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3.itb.walker 11 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
system.l2c.ReadSharedReq_mshr_hits::cpu2.data 3 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::cpu3.data 2 # number of ReadSharedReq MSHR hits
-system.l2c.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::cpu3.data 3 # number of ReadSharedReq MSHR hits
+system.l2c.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.data 3 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.dtb.walker 4 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.itb.walker 15 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.dtb.walker 9 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.itb.walker 11 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu3.inst 1 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::cpu3.data 2 # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.data 3 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.data 3 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.dtb.walker 4 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.itb.walker 15 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.dtb.walker 9 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.itb.walker 11 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu3.inst 1 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::cpu3.data 2 # number of overall MSHR hits
-system.l2c.overall_mshr_hits::total 25 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 317 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 303 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 507 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 452 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 1012 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::cpu3.itb.walker 943 # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_misses::total 3534 # number of ReadReq MSHR misses
-system.l2c.CleanEvict_mshr_misses::writebacks 457 # number of CleanEvict MSHR misses
-system.l2c.CleanEvict_mshr_misses::total 457 # number of CleanEvict MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu1.data 4483 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu2.data 5785 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::cpu3.data 10296 # number of UpgradeReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses::total 20564 # number of UpgradeReq MSHR misses
+system.l2c.overall_mshr_hits::cpu3.data 3 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 27 # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 417 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 408 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 426 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 363 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.dtb.walker 1009 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.itb.walker 921 # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total 3544 # number of ReadReq MSHR misses
+system.l2c.CleanEvict_mshr_misses::writebacks 456 # number of CleanEvict MSHR misses
+system.l2c.CleanEvict_mshr_misses::total 456 # number of CleanEvict MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data 4585 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data 5739 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data 9908 # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total 20232 # number of UpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::cpu3.data 2 # number of SCUpgradeReq MSHR misses
system.l2c.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu1.data 49078 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu2.data 67882 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::cpu3.data 112079 # number of ReadExReq MSHR misses
-system.l2c.ReadExReq_mshr_misses::total 229039 # number of ReadExReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10925 # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 24031 # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 28030 # number of ReadCleanReq MSHR misses
-system.l2c.ReadCleanReq_mshr_misses::total 62986 # number of ReadCleanReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu1.data 29685 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu2.data 38307 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::cpu3.data 75806 # number of ReadSharedReq MSHR misses
-system.l2c.ReadSharedReq_mshr_misses::total 143798 # number of ReadSharedReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu1.data 17981 # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu2.data 28569 # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::cpu3.data 64895 # number of InvalidateReq MSHR misses
-system.l2c.InvalidateReq_mshr_misses::total 111445 # number of InvalidateReq MSHR misses
-system.l2c.demand_mshr_misses::cpu1.dtb.walker 317 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.itb.walker 303 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.inst 10925 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu1.data 78763 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.dtb.walker 507 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.itb.walker 452 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.inst 24031 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu2.data 106189 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.dtb.walker 1012 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.itb.walker 943 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.inst 28030 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::cpu3.data 187885 # number of demand (read+write) MSHR misses
-system.l2c.demand_mshr_misses::total 439357 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses::cpu1.dtb.walker 317 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.itb.walker 303 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.inst 10925 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 78763 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.dtb.walker 507 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.itb.walker 452 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.inst 24031 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu2.data 106189 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.dtb.walker 1012 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.itb.walker 943 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.inst 28030 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu3.data 187885 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 439357 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6070 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu2.data 4638 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::cpu3.data 5330 # number of ReadReq MSHR uncacheable
-system.l2c.ReadReq_mshr_uncacheable::total 16038 # number of ReadReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5514 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu2.data 4225 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::cpu3.data 5069 # number of WriteReq MSHR uncacheable
-system.l2c.WriteReq_mshr_uncacheable::total 14808 # number of WriteReq MSHR uncacheable
-system.l2c.overall_mshr_uncacheable_misses::cpu1.data 11584 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu2.data 8863 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::cpu3.data 10399 # number of overall MSHR uncacheable misses
-system.l2c.overall_mshr_uncacheable_misses::total 30846 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 24352500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 23451000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 38142000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 33868000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 78456500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 75654000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 273924000 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 92604000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 120054000 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 213635500 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 426293500 # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_misses::cpu1.data 51076 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data 66860 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3.data 112125 # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total 230061 # number of ReadExReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 10966 # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 27651 # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 28084 # number of ReadCleanReq MSHR misses
+system.l2c.ReadCleanReq_mshr_misses::total 66701 # number of ReadCleanReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu1.data 33042 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu2.data 40131 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::cpu3.data 73979 # number of ReadSharedReq MSHR misses
+system.l2c.ReadSharedReq_mshr_misses::total 147152 # number of ReadSharedReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu1.data 19000 # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu2.data 28887 # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::cpu3.data 66669 # number of InvalidateReq MSHR misses
+system.l2c.InvalidateReq_mshr_misses::total 114556 # number of InvalidateReq MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker 417 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker 408 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst 10966 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data 84118 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.dtb.walker 426 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.itb.walker 363 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst 27651 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data 106991 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.dtb.walker 1009 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.itb.walker 921 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst 28084 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data 186104 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total 447458 # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker 417 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker 408 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst 10966 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data 84118 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.dtb.walker 426 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.itb.walker 363 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst 27651 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data 106991 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.dtb.walker 1009 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.itb.walker 921 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst 28084 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data 186104 # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total 447458 # number of overall MSHR misses
+system.l2c.ReadReq_mshr_uncacheable::cpu1.data 6330 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu2.data 4869 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::cpu3.data 4820 # number of ReadReq MSHR uncacheable
+system.l2c.ReadReq_mshr_uncacheable::total 16019 # number of ReadReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu1.data 5775 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu2.data 4397 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::cpu3.data 4483 # number of WriteReq MSHR uncacheable
+system.l2c.WriteReq_mshr_uncacheable::total 14655 # number of WriteReq MSHR uncacheable
+system.l2c.overall_mshr_uncacheable_misses::cpu1.data 12105 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu2.data 9266 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::cpu3.data 9303 # number of overall MSHR uncacheable misses
+system.l2c.overall_mshr_uncacheable_misses::total 30674 # number of overall MSHR uncacheable misses
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 31020000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 31080000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 31914500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 27939500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.dtb.walker 78750500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.itb.walker 72708500 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total 273413000 # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 94704500 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 119085000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 205591000 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 419380500 # number of UpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu3.data 91500 # number of SCUpgradeReq MSHR miss cycles
system.l2c.SCUpgradeReq_mshr_miss_latency::total 91500 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3463148500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4828868000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 9877325500 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 18169342000 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 779091500 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1755879000 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 2109208500 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadCleanReq_mshr_miss_latency::total 4644179000 # number of ReadCleanReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 2160850500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 2809328500 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 6030368000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.ReadSharedReq_mshr_miss_latency::total 11000547000 # number of ReadSharedReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1249753000 # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data 2237696500 # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data 6345527500 # number of InvalidateReq MSHR miss cycles
-system.l2c.InvalidateReq_mshr_miss_latency::total 9832977000 # number of InvalidateReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 24352500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 23451000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.inst 779091500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 5623999000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 38142000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 33868000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.inst 1755879000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu2.data 7638196500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 78456500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 75654000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.inst 2109208500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu3.data 15907693500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 34087992000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 24352500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 23451000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 779091500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 5623999000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 38142000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 33868000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.inst 1755879000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu2.data 7638196500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 78456500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 75654000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.inst 2109208500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu3.data 15907693500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 34087992000 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1003128500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 730361500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 841776000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 2575266000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 936501000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 675184500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 836243500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 2447929000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1939629500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1405546000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu3.data 1678019500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 5023195000 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.005716 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.007220 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003295 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.007839 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003442 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.008911 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.003596 # mshr miss rate for ReadReq accesses
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3604890000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 4729660500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 9873463000 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 18208013500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 777566500 # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 2024966500 # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 2107511500 # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadCleanReq_mshr_miss_latency::total 4910044500 # number of ReadCleanReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 2421426000 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 2943444000 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 5840517500 # number of ReadSharedReq MSHR miss cycles
+system.l2c.ReadSharedReq_mshr_miss_latency::total 11205387500 # number of ReadSharedReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu1.data 1323300000 # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu2.data 2253213000 # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::cpu3.data 6489291000 # number of InvalidateReq MSHR miss cycles
+system.l2c.InvalidateReq_mshr_miss_latency::total 10065804000 # number of InvalidateReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 31020000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 31080000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst 777566500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data 6026316000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 31914500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 27939500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst 2024966500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data 7673104500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.dtb.walker 78750500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.itb.walker 72708500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst 2107511500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data 15713980500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 34596858500 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 31020000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 31080000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst 777566500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data 6026316000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 31914500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 27939500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst 2024966500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data 7673104500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.dtb.walker 78750500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.itb.walker 72708500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst 2107511500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data 15713980500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 34596858500 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1036307000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 760536500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 777950000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 2574793500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 974195500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 694163000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 758681500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 2427040000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 2010502500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 1454699500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3.data 1536631500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 5001833500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.007473 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.009637 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.002698 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.006078 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003361 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.itb.walker 0.008146 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.003527 # mshr miss rate for ReadReq accesses
system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.781691 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.779020 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.786014 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.469916 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.786180 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.788974 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.781203 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.462805 # mshr miss rate for UpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.500000 # mshr miss rate for SCUpgradeReq accesses
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.196276 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.190347 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.196558 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.114867 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006406 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.006196 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.005994 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadCleanReq_mshr_miss_rate::total 0.003991 # mshr miss rate for ReadCleanReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.037351 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.035087 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.038310 # mshr miss rate for ReadSharedReq accesses
-system.l2c.ReadSharedReq_mshr_miss_rate::total 0.021981 # mshr miss rate for ReadSharedReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.156718 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.186829 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.223338 # mshr miss rate for InvalidateReq accesses
-system.l2c.InvalidateReq_mshr_miss_rate::total 0.090959 # mshr miss rate for InvalidateReq accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.005716 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.007220 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006406 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.075386 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003295 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.007839 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.006196 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.073315 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003442 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008911 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.inst 0.005994 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu3.data 0.073710 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.017365 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.005716 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.007220 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006406 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.075386 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003295 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.007839 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.006196 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.073315 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003442 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008911 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.inst 0.005994 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu3.data 0.073710 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.017365 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76821.766562 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 77396.039604 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75230.769231 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 74929.203540 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 77526.185771 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 80226.935313 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 77511.035654 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20656.703101 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20752.636128 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20749.368687 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20730.086559 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.209739 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.194043 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.192083 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.115350 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.006465 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.007063 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.006007 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadCleanReq_mshr_miss_rate::total 0.004217 # mshr miss rate for ReadCleanReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.041739 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.036471 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.038093 # mshr miss rate for ReadSharedReq accesses
+system.l2c.ReadSharedReq_mshr_miss_rate::total 0.022521 # mshr miss rate for ReadSharedReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu1.data 0.180105 # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu2.data 0.186117 # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::cpu3.data 0.225118 # mshr miss rate for InvalidateReq accesses
+system.l2c.InvalidateReq_mshr_miss_rate::total 0.093499 # mshr miss rate for InvalidateReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.007473 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.009637 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.006465 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.081261 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.002698 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.006078 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.007063 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.074046 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003361 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.itb.walker 0.008146 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006007 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data 0.073682 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.017652 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.007473 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.009637 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.006465 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.081261 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.002698 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.006078 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.007063 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.074046 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003361 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.itb.walker 0.008146 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006007 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data 0.073682 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.017652 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 74388.489209 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76176.470588 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 74916.666667 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 76968.319559 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 78048.067393 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.itb.walker 78945.168295 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 77148.137698 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20655.288986 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20750.130685 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20750 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20728.573547 # average UpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 45750 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 45750 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70564.173357 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 71136.206947 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 88128.244363 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 79328.594693 # average ReadExReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71312.723112 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73067.246473 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 75248.251873 # average ReadCleanReq mshr miss latency
-system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73733.512209 # average ReadCleanReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 72792.673067 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73337.209909 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 79550.009234 # average ReadSharedReq mshr miss latency
-system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76500 # average ReadSharedReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69504.087648 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 78326.035213 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 97781.454658 # average InvalidateReq mshr miss latency
-system.l2c.InvalidateReq_avg_mshr_miss_latency::total 88231.656871 # average InvalidateReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76821.766562 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 77396.039604 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71312.723112 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71404.072978 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75230.769231 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 74929.203540 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73067.246473 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71930.204635 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 77526.185771 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 80226.935313 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 75248.251873 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu3.data 84667.182053 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 77586.090582 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76821.766562 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 77396.039604 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71312.723112 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71404.072978 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75230.769231 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 74929.203540 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73067.246473 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71930.204635 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 77526.185771 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 80226.935313 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75248.251873 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84667.182053 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 77586.090582 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 165260.049423 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 157473.372143 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 157931.707317 # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160572.764684 # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169840.587595 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 159806.982249 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 164972.085224 # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 165311.250675 # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 167440.391920 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 158585.806160 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 161363.544572 # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total 162847.532905 # average overall mshr uncacheable latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70578.941186 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 70739.762190 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 88057.641026 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 79144.285646 # average ReadExReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 70907.030823 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 73233.029547 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 75043.138442 # average ReadCleanReq mshr miss latency
+system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 73612.756930 # average ReadCleanReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 73283.275831 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 73345.892203 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 78948.316414 # average ReadSharedReq mshr miss latency
+system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 76148.387382 # average ReadSharedReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu1.data 69647.368421 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu2.data 78000.934676 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::cpu3.data 97335.958241 # average InvalidateReq mshr miss latency
+system.l2c.InvalidateReq_avg_mshr_miss_latency::total 87867.977234 # average InvalidateReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74388.489209 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76176.470588 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70907.030823 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71641.218289 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 74916.666667 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 76968.319559 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 73233.029547 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 71717.289305 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 78048.067393 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.itb.walker 78945.168295 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 75043.138442 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 84436.554292 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 77318.672367 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74388.489209 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76176.470588 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70907.030823 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71641.218289 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 74916.666667 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 76968.319559 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 73233.029547 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 71717.289305 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 78048.067393 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.itb.walker 78945.168295 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 75043.138442 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 84436.554292 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 77318.672367 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163713.586098 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 156199.733005 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 161400.414938 # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 160733.722455 # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168691.861472 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 157871.958153 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 169235.221950 # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 165611.736609 # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 166088.599752 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 156993.254910 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 165175.910996 # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total 163064.272674 # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.membus.trans_dist::ReadReq 76737 # Transaction distribution
-system.membus.trans_dist::ReadResp 451400 # Transaction distribution
-system.membus.trans_dist::WriteReq 33647 # Transaction distribution
-system.membus.trans_dist::WriteResp 33647 # Transaction distribution
-system.membus.trans_dist::Writeback 1088767 # Transaction distribution
-system.membus.trans_dist::CleanEvict 205338 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 34966 # Transaction distribution
+system.membus.trans_dist::ReadReq 76739 # Transaction distribution
+system.membus.trans_dist::ReadResp 460749 # Transaction distribution
+system.membus.trans_dist::WriteReq 33648 # Transaction distribution
+system.membus.trans_dist::WriteResp 33648 # Transaction distribution
+system.membus.trans_dist::Writeback 1098433 # Transaction distribution
+system.membus.trans_dist::CleanEvict 213962 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 34949 # Transaction distribution
system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 34968 # Transaction distribution
-system.membus.trans_dist::ReadExReq 904844 # Transaction distribution
-system.membus.trans_dist::ReadExResp 904844 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 374663 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 34951 # Transaction distribution
+system.membus.trans_dist::ReadExReq 916210 # Transaction distribution
+system.membus.trans_dist::ReadExResp 916210 # Transaction distribution
+system.membus.trans_dist::ReadSharedReq 384010 # Transaction distribution
system.membus.trans_dist::InvalidateReq 106664 # Transaction distribution
system.membus.trans_dist::InvalidateResp 106664 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 122576 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 62 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6756 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3881435 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 4010829 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 345611 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 345611 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 4356440 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 6762 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 3942227 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 4071627 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 343658 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 343658 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 4415285 # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 155706 # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 196 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13512 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 144353760 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 144523174 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7363392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7363392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 151886566 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 711 # Total snoops (count)
-system.membus.snoop_fanout::samples 2826104 # Request fanout histogram
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 13524 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 146305120 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 146474546 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7302336 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7302336 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 153776882 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 1554 # Total snoops (count)
+system.membus.snoop_fanout::samples 2866082 # Request fanout histogram
system.membus.snoop_fanout::mean 1 # Request fanout histogram
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 2826104 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 2866082 100.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 2826104 # Request fanout histogram
-system.membus.reqLayer0.occupancy 51928000 # Layer occupancy (ticks)
+system.membus.snoop_fanout::total 2866082 # Request fanout histogram
+system.membus.reqLayer0.occupancy 51617000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 2000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1759000 # Layer occupancy (ticks)
+system.membus.reqLayer2.occupancy 1694500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 3236688724 # Layer occupancy (ticks)
+system.membus.reqLayer5.occupancy 3281296074 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2999492092 # Layer occupancy (ticks)
+system.membus.respLayer2.occupancy 3058096264 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 84543932 # Layer occupancy (ticks)
+system.membus.respLayer3.occupancy 103726218 # Layer occupancy (ticks)
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
system.realview.ethernet.txBytes 966 # Bytes Transmitted
system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
system.realview.ethernet.postedInterrupts 18 # number of posts to CPU
system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.toL2Bus.trans_dist::ReadReq 1501925 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 23827607 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 33647 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 33647 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 8029950 # Transaction distribution
-system.toL2Bus.trans_dist::CleanEvict 18099474 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 43761 # Transaction distribution
+system.toL2Bus.trans_dist::ReadReq 1507075 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 23857599 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 33648 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 33648 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 8015609 # Transaction distribution
+system.toL2Bus.trans_dist::CleanEvict 18152591 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 43716 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 43765 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 1993953 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 1993953 # Transaction distribution
-system.toL2Bus.trans_dist::ReadCleanReq 15783383 # Transaction distribution
-system.toL2Bus.trans_dist::ReadSharedReq 6542484 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateReq 1272617 # Transaction distribution
-system.toL2Bus.trans_dist::InvalidateResp 1225217 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47433804 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29504905 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 816519 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1737039 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 79492267 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1010303252 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1029626962 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2926248 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6100712 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 2048957174 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1001590 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 53371149 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.039891 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.195703 # Request fanout histogram
+system.toL2Bus.trans_dist::UpgradeResp 43720 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 1994458 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 1994458 # Transaction distribution
+system.toL2Bus.trans_dist::ReadCleanReq 15815989 # Transaction distribution
+system.toL2Bus.trans_dist::ReadSharedReq 6539025 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateReq 1270619 # Transaction distribution
+system.toL2Bus.trans_dist::InvalidateResp 1225211 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 47531663 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 29482635 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 826355 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 1753245 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 79593898 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 1012390548 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1027984926 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 2989368 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 6204744 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 2049569586 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 999459 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 53440188 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.040190 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.196406 # Request fanout histogram
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 51242120 96.01% 96.01% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 2129029 3.99% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 51292404 95.98% 95.98% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 2147784 4.02% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 53371149 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 20695529987 # Layer occupancy (ticks)
+system.toL2Bus.snoop_fanout::total 53440188 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 20656393480 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 462000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks)
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 15394171442 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.occupancy 15434172491 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 7879772837 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.occupancy 7824329236 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 290523250 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.occupancy 294252739 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 715846054 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.occupancy 716654510 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu3.kern.inst.arm 0 # number of arm instructions executed
system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed
[ 3.133982] msgmni has been set to 469\r
[ 3.135967] io scheduler noop registered\r
[ 3.136002] io scheduler cfq registered (default)\r
-[ 3.136279] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
+[ 3.136280] pci-host-generic 30000000.pci: PCI host bridge to bus 0000:00\r
[ 3.136281] pci_bus 0000:00: root bus resource [io 0x0000-0xffff]\r
[ 3.136283] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff]\r
[ 3.136284] pci_bus 0000:00: root bus resource [bus 00-ff]\r
[ 3.136285] pci_bus 0000:00: scanning bus\r
[ 3.136288] pci 0000:00:00.0: [8086:1075] type 00 class 0x020000\r
[ 3.136290] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x0001ffff]\r
-[ 3.136292] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
+[ 3.136293] pci 0000:00:00.0: reg 0x30: [mem 0x00000000-0x000007ff pref]\r
[ 3.136309] pci 0000:00:01.0: [8086:7111] type 00 class 0x010185\r
[ 3.136311] pci 0000:00:01.0: reg 0x10: [io 0x0000-0x0007]\r
[ 3.136313] pci 0000:00:01.0: reg 0x14: [io 0x0000-0x0003]\r
[ 3.136352] pci 0000:00:00.0: BAR 0: assigned [mem 0x40000000-0x4001ffff]\r
[ 3.136354] pci 0000:00:00.0: BAR 6: assigned [mem 0x40020000-0x400207ff pref]\r
[ 3.136356] pci 0000:00:01.0: BAR 6: assigned [mem 0x40020800-0x40020fff pref]\r
-[ 3.136357] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
+[ 3.136358] pci 0000:00:01.0: BAR 4: assigned [io 0x1000-0x100f]\r
[ 3.136359] pci 0000:00:01.0: BAR 0: assigned [io 0x1010-0x1017]\r
[ 3.136361] pci 0000:00:01.0: BAR 2: assigned [io 0x1018-0x101f]\r
[ 3.136363] pci 0000:00:01.0: BAR 1: assigned [io 0x1020-0x1023]\r
[ 3.136364] pci 0000:00:01.0: BAR 3: assigned [io 0x1024-0x1027]\r
-[ 3.136957] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
+[ 3.136956] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled\r
[ 3.137115] ata_piix 0000:00:01.0: version 2.13\r
[ 3.137124] ata_piix 0000:00:01.0: enabling device (0000 -> 0001)\r
[ 3.137143] ata_piix 0000:00:01.0: enabling bus mastering\r
[ 3.137321] scsi0 : ata_piix\r
[ 3.137376] scsi1 : ata_piix\r
[ 3.137393] ata1: PATA max UDMA/33 cmd 0x1010 ctl 0x1020 bmdma 0x1000 irq 34\r
-[ 3.137395] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
-[ 3.137475] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
-[ 3.137488] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
-[ 3.137509] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
-[ 3.137522] e1000 0000:00:00.0: enabling bus mastering\r
+[ 3.137394] ata2: PATA max UDMA/33 cmd 0x1018 ctl 0x1024 bmdma 0x1008 irq 34\r
+[ 3.137474] e1000: Intel(R) PRO/1000 Network Driver - version 7.3.21-k8-NAPI\r
+[ 3.137487] e1000: Copyright (c) 1999-2006 Intel Corporation.\r
+[ 3.137508] e1000 0000:00:00.0: enabling device (0000 -> 0002)\r
+[ 3.137521] e1000 0000:00:00.0: enabling bus mastering\r
[ 3.290865] ata1.00: ATA-7: M5 IDE Disk, , max UDMA/66\r
[ 3.290866] ata1.00: 2096640 sectors, multi 0: LBA \r
[ 3.290873] ata1.00: configured for UDMA/33\r
[ 3.411208] e1000e: Copyright(c) 1999 - 2014 Intel Corporation.\r
[ 3.411238] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.0.5-k\r
[ 3.411251] igb: Copyright (c) 2007-2014 Intel Corporation.\r
-[ 3.411375] usbcore: registered new interface driver usb-storage\r
+[ 3.411374] usbcore: registered new interface driver usb-storage\r
[ 3.411444] mousedev: PS/2 mouse device common for all mice\r
[ 3.411624] usbcore: registered new interface driver usbhid\r
[ 3.411633] usbhid: USB HID core driver\r
[ 3.411895] Freeing unused kernel memory: 208K (ffffffc000692000 - ffffffc0006c6000)\r
\0\0\rINIT: \0version 2.88 booting\0\r\r
\0Starting udev\r
-[ 3.450115] udevd[607]: starting version 182\r
+[ 3.450119] udevd[607]: starting version 182\r
Starting Bootlog daemon: bootlogd.\r\r
-[ 3.533154] random: dd urandom read with 19 bits of entropy available\r
+[ 3.543151] random: dd urandom read with 19 bits of entropy available\r
Populating dev cache\r\r
net.ipv4.conf.default.rp_filter = 1\r\r
net.ipv4.conf.all.rp_filter = 1\r\r
hwclock: can't open '/dev/misc/rtc': No such file or directory\r\r
\rINIT: Entering runlevel: 5\r\r\r
Configuring network interfaces... udhcpc (v1.21.1) started\r\r
-[ 3.671081] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
+[ 3.681081] e1000: eth0 NIC Link is Up 1000 Mbps Full Duplex, Flow Control: None\r
Sending discover...\r\r
Sending discover...\r\r
Sending discover...\r\r
projects / gem5.git / commitdiff