Update commented out
authorEddie Hung <eddie@fpgeh.com>
Fri, 30 Aug 2019 22:01:38 +0000 (15:01 -0700)
committerEddie Hung <eddie@fpgeh.com>
Fri, 30 Aug 2019 22:01:38 +0000 (15:01 -0700)
passes/pmgen/xilinx_dsp.cc

index 105ad1fa16714b90c4193c8dbeacb2dab5800282..b03fff8ecb28ddfde909be7940ba24a28e5529b1 100644 (file)
@@ -104,7 +104,7 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                        if (st.ffP->type == "$dff")
                                cell->setPort("\\CEM", State::S1);
                        //else if (st.ffP->type == "$dffe")
-                       //      cell->setPort("\\CEP", st.ffP->getPort("\\EN"));
+                       //      cell->setPort("\\CEM", st.ffM->getPort("\\EN"));
                        else log_abort();
                }
                if (st.ffP) {