ac: add has_dcc_constant_encode to ac_gpu_info

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index a3f1afe1f0455965ec3186eaee950a6d3f9b3e57..b6b37564c9f7fb2076b892c5ee1d6cedf42cf841 100644 (file)
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -450,6 +450,10 @@ bool ac_query_gpu_info(int fd, void *dev_p,
        info->has_distributed_tess = info->chip_class >= GFX8 &&
                                     info->max_se >= 2;
 
+       info->has_dcc_constant_encode = info->family == CHIP_RAVEN2 ||
+                                       info->family == CHIP_RENOIR ||
+                                       info->chip_class >= GFX10;
+
        /* Get the number of good compute units. */
        info->num_good_compute_units = 0;
        for (i = 0; i < info->max_se; i++)

diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 9ce1650c03c25376d1dbad11231d7b1a01993fd0..10b578a1ef991db7c2baf7f4a02babf1011dd54b 100644 (file)
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -60,6 +60,7 @@ struct radeon_info {
        uint32_t                    tcc_cache_line_size;
        bool                        has_clear_state;
        bool                        has_distributed_tess;
+       bool                        has_dcc_constant_encode;
 
        /* There are 2 display DCC codepaths, because display expects unaligned DCC. */
        /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 83c6eb04e1e0885b31eafd9a40990397504629ab..ac9ec2e9b0d7df9f45f219b2079127548e3e910b 100644 (file)
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2005,7 +2005,7 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
 
        if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {
                bool disable_constant_encode =
-                       cmd_buffer->device->physical_device->has_dcc_constant_encode;
+                       cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;
                enum chip_class chip_class =
                        cmd_buffer->device->physical_device->rad_info.chip_class;
                uint8_t watermark = chip_class >= GFX10 ? 6 : 4;

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index ad5c104f44fa9e74802c23439903f9b0f65edb8f..a1927b9506c28d28c4a37692a7daad38d7f06d56 100644 (file)
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -386,10 +386,6 @@ radv_physical_device_init(struct radv_physical_device *device,
                                       (device->rad_info.chip_class >= GFX8 &&
                                        device->rad_info.me_fw_feature >= 41);
 
-       device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
-                                         device->rad_info.family == CHIP_RENOIR ||
-                                         device->rad_info.chip_class >= GFX10;
-
        device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
                                    device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
 

diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 287c2abfa3fa27cd637fb822ef8174947dbff00e..6c8d4b9c0a0048e205ecfefdc631ed552d1770bf 100644 (file)
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -298,9 +298,6 @@ struct radv_physical_device {
        /* Whether to enable the AMD_shader_ballot extension */
        bool use_shader_ballot;
 
-       /* Whether DISABLE_CONSTANT_ENCODE_REG is supported. */
-       bool has_dcc_constant_encode;
-
        /* Number of threads per wave. */
        uint8_t ps_wave_size;
        uint8_t cs_wave_size;

diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index a83f65c6f1be5cb5cbcca9e834816b82413f7c1c..34a39a0edae7f8e0df086a72d571d4482c9ea4c5 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -559,7 +559,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
                /* Chips with DCC constant encoding don't need to set the clear
                 * color registers for DCC clear values 0 and 1.
                 */
-               if (sctx->screen->has_dcc_constant_encode && !eliminate_needed)
+               if (sctx->screen->info.has_dcc_constant_encode && !eliminate_needed)
                        continue;
 
                if (si_set_clear_color(tex, fb->cbufs[i]->format, color)) {

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index b6fce0640f4038d28890bf6dabee4cbfd7dbbae5..2d5298edd8cff8986c58cbf85476bdeb972f8e15 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1144,9 +1144,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
                                           sscreen->info.family == CHIP_RAVEN;
        sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
                                        sscreen->info.family == CHIP_RAVEN;
-       sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2 ||
-                                          sscreen->info.family == CHIP_RENOIR ||
-                                          sscreen->info.chip_class >= GFX10;
        sscreen->use_ngg = sscreen->info.chip_class >= GFX10;
        sscreen->use_ngg_streamout = sscreen->info.chip_class >= GFX10;
 

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 6b0b5d3e20d66f6100f264c71974d41b3dd836bf..7ad700f526539a521e0f0a324e813dea4569e4a6 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -498,7 +498,6 @@ struct si_screen {
        bool                            has_gfx9_scissor_bug;
        bool                            has_msaa_sample_loc_bug;
        bool                            has_ls_vgpr_init_bug;
-       bool                            has_dcc_constant_encode;
        bool                            dpbb_allowed;
        bool                            dfsm_allowed;
        bool                            llvm_has_working_vgpr_indexing;

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index d5cdc6603509adf339f61004e0cbac7ee94641cf..cd26f5af9d2e98996b09134f0afdaa5a7cb8d3f5 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -127,7 +127,7 @@ static void si_emit_cb_render_state(struct si_context *sctx)
                                S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
                                S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
                                S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
-                               S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
+                               S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->info.has_dcc_constant_encode));
        }
 
        /* RB+ register settings. */