muldiv.md (mulhisi3_c): Limit the mode of the 2nd operand to HI mode.

* config/m32c/muldiv.md (mulhisi3_c): Limit the mode of the 2nd
operand to HI mode.
(mulsi3): New.
(divsi3): New.
(udivsi3): New.

From-SVN: r124524

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9452c04552462f5f90794844ad2b28d1885609ac..a7df7b0eecb009ed9305f7782819511a0f0ce460 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,11 @@
+2007-05-07   Naveen.H.S  <naveen.hs@kpitcummins.com>
+
+       * config/m32c/muldiv.md (mulhisi3_c): Limit the mode of the 2nd
+       operand to HI mode.
+       (mulsi3): New.
+       (divsi3): New.
+       (udivsi3): New.
+
 2007-05-07  Jayant Sonar  <jayants@kpitcummins.com>
 
        * config/m32c/m32c.c (SYMBOL_FLAG_FUNCVEC_FUNCTION): Define.

diff --git a/gcc/config/m32c/muldiv.md b/gcc/config/m32c/muldiv.md
index 6913ea9a7293ffcfacd20347e93968ff845f25e4..b6c6565baa51c899532c0a9618be696853275eb0 100644 (file)
--- a/gcc/config/m32c/muldiv.md
+++ b/gcc/config/m32c/muldiv.md
@@ -82,7 +82,7 @@
 (define_insn "mulhisi3_c"
   [(set (match_operand:SI 0 "ra_operand" "=Rsi")
         (mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand" "%0"))
-                 (match_operand 2 "immediate_operand" "i")))]
+                 (match_operand:HI 2 "immediate_operand" "i")))]
   ""
   "mul.w\t%2,%1"
   [(set_attr "flags" "o")]
@@ -159,7 +159,14 @@
      }"
   )
 
-
+(define_insn "mulsi3"
+  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
+        (mult:SI (match_operand:SI 1 "r0123_operand" "%0,0")
+                 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
+  "TARGET_M32C"
+  "mul.l\t%2,%1"
+  [(set_attr "flags" "o")]
+)
 
 (define_expand "divmodqi4"
   [(set (match_dup 4)
@@ -260,3 +267,23 @@
   "divu.w\t%2"
   [(set_attr "flags" "o")]
   )
+
+(define_insn "divsi3"
+  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
+        (div:SI (match_operand:SI 1 "r0123_operand" "0,0")
+                (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
+  "TARGET_M32C"
+  "div.l\t%2"
+  [(set_attr "flags" "o")]
+)
+
+(define_insn "udivsi3"
+  [(set (match_operand:SI 0 "r0123_operand" "=R02,R02")
+        (udiv:SI (match_operand:SI 1 "r0123_operand" "0,0")
+                 (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
+  "TARGET_M32C"
+  "divu.l\t%2"
+  [(set_attr "flags" "o")]
+)
+
+