Re-arrange FD order

diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v
index 4ab8e15640accd4193af8d490b928ded74b029df..6d93e508f38e5ed5ef81ff924e422a579f5c9214 100644 (file)
--- a/techlibs/xilinx/abc9_map.v
+++ b/techlibs/xilinx/abc9_map.v
@@ -163,6 +163,89 @@ module FDRE_1 (output Q, input C, CE, D, R);
 `endif
 endmodule
 
+module FDSE (output Q, input C, CE, D, S);
+  parameter [0:0] INIT = 1'b1;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_S_INVERTED = 1'b0;
+`ifdef DFF_MODE
+  wire QQ, $Q;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDRE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_R_INVERTED(IS_S_INVERTED)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDSE #(
+      .INIT(1'b0),
+      .IS_C_INVERTED(IS_C_INVERTED),
+      .IS_D_INVERTED(IS_D_INVERTED),
+      .IS_S_INVERTED(IS_S_INVERTED)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
+    );
+  end endgenerate
+  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+
+  // Special signals
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+`else
+  (* abc9_keep *)
+  FDSE #(
+    .INIT(INIT),
+    .IS_C_INVERTED(IS_C_INVERTED),
+    .IS_D_INVERTED(IS_D_INVERTED),
+    .IS_S_INVERTED(IS_S_INVERTED)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
+  );
+`endif
+endmodule
+module FDSE_1 (output Q, input C, CE, D, S);
+  parameter [0:0] INIT = 1'b1;
+`ifdef DFF_MODE
+  wire QQ, $Q;
+  generate if (INIT == 1'b1) begin
+    assign Q = ~QQ;
+    FDRE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
+    );
+  end
+  else begin
+    assign Q = QQ;
+    FDSE_1 #(
+      .INIT(1'b0)
+    ) _TECHMAP_REPLACE_ (
+      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
+    );
+  end endgenerate
+  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
+
+  // Special signals
+  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
+  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
+`else
+  (* abc9_keep *)
+  FDSE_1 #(
+    .INIT(INIT)
+  ) _TECHMAP_REPLACE_ (
+    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
+  );
+`endif
+endmodule
+
 module FDCE (output Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
@@ -379,89 +462,6 @@ module FDPE_1 (output Q, input C, CE, D, PRE);
 `endif
 endmodule
 
-module FDSE (output Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b1;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_S_INVERTED = 1'b0;
-`ifdef DFF_MODE
-  wire QQ, $Q;
-  generate if (INIT == 1'b1) begin
-    assign Q = ~QQ;
-    FDRE #(
-      .INIT(1'b0),
-      .IS_C_INVERTED(IS_C_INVERTED),
-      .IS_D_INVERTED(IS_D_INVERTED),
-      .IS_R_INVERTED(IS_S_INVERTED)
-    ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
-    );
-  end
-  else begin
-    assign Q = QQ;
-    FDSE #(
-      .INIT(1'b0),
-      .IS_C_INVERTED(IS_C_INVERTED),
-      .IS_D_INVERTED(IS_D_INVERTED),
-      .IS_S_INVERTED(IS_S_INVERTED)
-    ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
-    );
-  end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
-
-  // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, IS_C_INVERTED};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDSE #(
-    .INIT(INIT),
-    .IS_C_INVERTED(IS_C_INVERTED),
-    .IS_D_INVERTED(IS_D_INVERTED),
-    .IS_S_INVERTED(IS_S_INVERTED)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
-  );
-`endif
-endmodule
-module FDSE_1 (output Q, input C, CE, D, S);
-  parameter [0:0] INIT = 1'b1;
-`ifdef DFF_MODE
-  wire QQ, $Q;
-  generate if (INIT == 1'b1) begin
-    assign Q = ~QQ;
-    FDRE_1 #(
-      .INIT(1'b0)
-    ) _TECHMAP_REPLACE_ (
-      .D(~D), .Q($Q), .C(C), .CE(CE), .R(S)
-    );
-  end
-  else begin
-    assign Q = QQ;
-    FDSE_1 #(
-      .INIT(1'b0)
-    ) _TECHMAP_REPLACE_ (
-      .D(D), .Q($Q), .C(C), .CE(CE), .S(S)
-    );
-  end endgenerate
-  $__ABC9_FF_ abc_dff (.D($Q), .Q(QQ));
-
-  // Special signals
-  wire [1:0] _TECHMAP_REPLACE_.$abc9_clock = {C, 1'b1 /* IS_C_INVERTED */};
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_init = 1'b0;
-  wire [0:0] _TECHMAP_REPLACE_.$abc9_currQ = QQ;
-`else
-  (* abc9_keep *)
-  FDSE_1 #(
-    .INIT(INIT)
-  ) _TECHMAP_REPLACE_ (
-    .D(D), .Q(Q), .C(C), .CE(CE), .S(S)
-  );
-`endif
-endmodule
-
 // Attach a (combinatorial) black-box onto the output
 //   of thes LUTRAM primitives to capture their
 //   asynchronous read behaviour

diff --git a/techlibs/xilinx/abc9_xc7.box b/techlibs/xilinx/abc9_xc7.box
index 3024870416e9d348ca39293ba4a107a6118b5dc1..43c39544e0c4d534ffad530f7a5af58904095716 100644 (file)
--- a/techlibs/xilinx/abc9_xc7.box
+++ b/techlibs/xilinx/abc9_xc7.box
@@ -81,48 +81,48 @@ FDRE_1 1101 1   5   1
 #0 109 -46 404 0
 0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
 
-# Box 1102 : FDCE
+# Box 1102 : FDSE
 # name ID   w/b ins outs
-FDCE   1102 1   5   1
+FDSE   1102 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1103 : FDSE_1
+# name ID   w/b ins outs
+FDSE_1 1103 1   5   1
+#C CE  D   R   $abc9_currQ
+#0 109 -46 404 0
+0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
+
+# Box 1104 : FDCE
+# name ID   w/b ins outs
+FDCE   1104 1   5   1
 #C CE  CLR D   $abc9_currQ
 #0 109 764 -46 0
 0 109 764 0   0 # Q (-46ps Tsu clamped to 0)
 
-# Box 1103 : FDCE_1
+# Box 1105 : FDCE_1
 # name ID   w/b ins outs
-FDCE_1 1103 1   5   1
+FDCE_1 1105 1   5   1
 #C CE  CLR D   $abc9_currQ
 #0 109 764 -46 0
 0 109 764 0   0 # Q (-46ps Tsu clamped to 0)
 
-# Box 1104 : FDPE
+# Box 1106 : FDPE
 # name ID   w/b ins outs
-FDPE   1104 1   5   1
+FDPE   1106 1   5   1
 #C CE  D   PRE $abc9_currQ
 #0 109 -46 764 0
 0 109 -46 764 0 # Q (-46ps Tsu clamped to 0)
 
-# Box 1105 : FDPE_1
+# Box 1107 : FDPE_1
 # name ID   w/b ins outs
-FDPE_1 1105 1   5   1
+FDPE_1 1107 1   5   1
 #C CE  D   PRE $abc9_currQ
 #0 109 -46 764 0
 0 109 -46 764 0 # Q (-46ps Tsu clamped to 0)
 
-# Box 1106 : FDSE
-# name ID   w/b ins outs
-FDSE   1106 1   5   1
-#C CE  D   R   $abc9_currQ
-#0 109 -46 404 0
-0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
-
-# Box 1107 : FDSE_1
-# name ID   w/b ins outs
-FDSE_1 1107 1   5   1
-#C CE  D   R   $abc9_currQ
-#0 109 -46 404 0
-0 109 0   404 0 # Q (-46ps Tsu clamped to 0)
-
 # Box 2000 : $__ABC9_LUT6
 #            (private cell to emulate async behaviour of LUTRAMs)
 # SLICEM/A6LUT

diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 982ccad72ad2f9ebf35685680b4e7064d79dbdcc..c22bcdc27972c9f1a161206ef72c67a96e364b70 100644 (file)
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -362,6 +362,43 @@ module FDRE_1 (
   always @(negedge C) if (R) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
+(* abc9_box_id=1102, lib_whitebox, abc9_flop *)
+module FDSE (
+  (* abc9_arrival=303 *)
+  output reg Q,
+  (* clkbuf_sink *)
+  (* invertible_pin = "IS_C_INVERTED" *)
+  input C,
+  input CE,
+  (* invertible_pin = "IS_D_INVERTED" *)
+  input D,
+  (* invertible_pin = "IS_S_INVERTED" *)
+  input S
+);
+  parameter [0:0] INIT = 1'b1;
+  parameter [0:0] IS_C_INVERTED = 1'b0;
+  parameter [0:0] IS_D_INVERTED = 1'b0;
+  parameter [0:0] IS_S_INVERTED = 1'b0;
+  initial Q <= INIT;
+  generate case (|IS_C_INVERTED)
+    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
+  endcase endgenerate
+endmodule
+
+(* abc9_box_id=1103, lib_whitebox, abc9_flop *)
+module FDSE_1 (
+  (* abc9_arrival=303 *)
+  output reg Q,
+  (* clkbuf_sink *)
+  input C,
+  input CE, D, S
+);
+  parameter [0:0] INIT = 1'b1;
+  initial Q <= INIT;
+  always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
+endmodule
+
 module FDRSE (
   output reg Q,
   (* clkbuf_sink *)
@@ -397,7 +434,7 @@ module FDRSE (
       Q <= d;
 endmodule
 
-(* abc9_box_id=1102, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
 module FDCE (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -423,7 +460,7 @@ module FDCE (
   endcase endgenerate
 endmodule
 
-(* abc9_box_id=1103, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1105, lib_whitebox, abc9_flop *)
 module FDCE_1 (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -436,52 +473,7 @@ module FDCE_1 (
   always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else if (CE) Q <= D;
 endmodule
 
-module FDCPE (
-  output wire Q,
-  (* clkbuf_sink *)
-  (* invertible_pin = "IS_C_INVERTED" *)
-  input C,
-  input CE,
-  (* invertible_pin = "IS_CLR_INVERTED" *)
-  input CLR,
-  input D,
-  (* invertible_pin = "IS_PRE_INVERTED" *)
-  input PRE
-);
-  parameter [0:0] INIT = 1'b0;
-  parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_CLR_INVERTED = 1'b0;
-  parameter [0:0] IS_PRE_INVERTED = 1'b0;
-  wire c = C ^ IS_C_INVERTED;
-  wire clr = CLR ^ IS_CLR_INVERTED;
-  wire pre = PRE ^ IS_PRE_INVERTED;
-  // Hacky model to avoid simulation-synthesis mismatches.
-  reg qc, qp, qs;
-  initial qc = INIT;
-  initial qp = INIT;
-  initial qs = 0;
-  always @(posedge c, posedge clr) begin
-    if (clr)
-      qc <= 0;
-    else if (CE)
-      qc <= D;
-  end
-  always @(posedge c, posedge pre) begin
-    if (pre)
-      qp <= 1;
-    else if (CE)
-      qp <= D;
-  end
-  always @* begin
-    if (clr)
-      qs <= 0;
-    else if (pre)
-      qs <= 1;
-  end
-  assign Q = qs ? qp : qc;
-endmodule
-
-(* abc9_box_id=1104, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1106, lib_whitebox, abc9_flop *)
 module FDPE (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -507,7 +499,7 @@ module FDPE (
   endcase endgenerate
 endmodule
 
-(* abc9_box_id=1105, lib_whitebox, abc9_flop *)
+(* abc9_box_id=1107, lib_whitebox, abc9_flop *)
 module FDPE_1 (
   (* abc9_arrival=303 *)
   output reg Q,
@@ -520,41 +512,49 @@ module FDPE_1 (
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
-(* abc9_box_id=1106, lib_whitebox, abc9_flop *)
-module FDSE (
-  (* abc9_arrival=303 *)
-  output reg Q,
+module FDCPE (
+  output wire Q,
   (* clkbuf_sink *)
   (* invertible_pin = "IS_C_INVERTED" *)
   input C,
   input CE,
-  (* invertible_pin = "IS_D_INVERTED" *)
+  (* invertible_pin = "IS_CLR_INVERTED" *)
+  input CLR,
   input D,
-  (* invertible_pin = "IS_S_INVERTED" *)
-  input S
+  (* invertible_pin = "IS_PRE_INVERTED" *)
+  input PRE
 );
-  parameter [0:0] INIT = 1'b1;
+  parameter [0:0] INIT = 1'b0;
   parameter [0:0] IS_C_INVERTED = 1'b0;
-  parameter [0:0] IS_D_INVERTED = 1'b0;
-  parameter [0:0] IS_S_INVERTED = 1'b0;
-  initial Q <= INIT;
-  generate case (|IS_C_INVERTED)
-    1'b0: always @(posedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-    1'b1: always @(negedge C) if (S == !IS_S_INVERTED) Q <= 1'b1; else if (CE) Q <= D ^ IS_D_INVERTED;
-  endcase endgenerate
-endmodule
-
-(* abc9_box_id=1107, lib_whitebox, abc9_flop *)
-module FDSE_1 (
-  (* abc9_arrival=303 *)
-  output reg Q,
-  (* clkbuf_sink *)
-  input C,
-  input CE, D, S
-);
-  parameter [0:0] INIT = 1'b1;
-  initial Q <= INIT;
-  always @(negedge C) if (S) Q <= 1'b1; else if (CE) Q <= D;
+  parameter [0:0] IS_CLR_INVERTED = 1'b0;
+  parameter [0:0] IS_PRE_INVERTED = 1'b0;
+  wire c = C ^ IS_C_INVERTED;
+  wire clr = CLR ^ IS_CLR_INVERTED;
+  wire pre = PRE ^ IS_PRE_INVERTED;
+  // Hacky model to avoid simulation-synthesis mismatches.
+  reg qc, qp, qs;
+  initial qc = INIT;
+  initial qp = INIT;
+  initial qs = 0;
+  always @(posedge c, posedge clr) begin
+    if (clr)
+      qc <= 0;
+    else if (CE)
+      qc <= D;
+  end
+  always @(posedge c, posedge pre) begin
+    if (pre)
+      qp <= 1;
+    else if (CE)
+      qp <= D;
+  end
+  always @* begin
+    if (clr)
+      qs <= 0;
+    else if (pre)
+      qs <= 1;
+  end
+  assign Q = qs ? qp : qc;
 endmodule
 
 module LDCE (