2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>

	* micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index ae22ba9a20b58eb15be3405f105d5e4b75eb1db0..901e59086aed0062cf0f5e018ff453573a4da7f6 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,7 @@
+2013-10-07  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
+
+       * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
+
 2013-09-30  H.J. Lu  <hongjiu.lu@intel.com>
 
        * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.

diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index fa6efb51486f6c57f23b1a2d2d14bfd60cd5ccfc..c5733d43acffc2669b86c39694e0d38ef398840f 100644 (file)
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -586,12 +586,12 @@ const struct mips_opcode micromips_opcodes[] =
 {"dli",                        "t,I",          0,    (int) M_DLI,      INSN_MACRO,             0,              I3,             0,      0 },
 {"dmfc0",              "t,G",          0x580000fc, 0xfc00ffff, WR_1|RD_C0,             0,              I3,             0,      0 },
 {"dmfc0",              "t,G,H",        0x580000fc, 0xfc00c7ff, WR_1|RD_C0,             0,              I3,             0,      0 },
-{"dmfgc0",             "t,G",          0x580000e7, 0xfc00ffff, WR_1|RD_C0,             0,              0,              IVIRT64, 0 },
-{"dmfgc0",             "t,G,H",        0x580000e7, 0xfc00c7ff, WR_1|RD_C0,             0,              0,              IVIRT64, 0 },
+{"dmfgc0",             "t,G",          0x580004fc, 0xfc00ffff, WR_1|RD_C0,             0,              0,              IVIRT64, 0 },
+{"dmfgc0",             "t,G,H",        0x580004fc, 0xfc00c7ff, WR_1|RD_C0,             0,              0,              IVIRT64, 0 },
 {"dmtc0",              "t,G",          0x580002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              I3,             0,      0 },
 {"dmtc0",              "t,G,H",        0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              I3,             0,      0 },
-{"dmtgc0",             "t,G",          0x580002e7, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
-{"dmtgc0",             "t,G,H",        0x580002e7, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
+{"dmtgc0",             "t,G",          0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
+{"dmtgc0",             "t,G,H",        0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC,       0,              0,              IVIRT64, 0 },
 {"dmfc1",              "t,S",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S,         0,              I3,             0,      0 },
 {"dmfc1",              "t,G",          0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S,         0,              I3,             0,      0 },
 {"dmtc1",              "t,G",          0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S,         0,              I3,             0,      0 },