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Add to CHANGELOG
author
Eddie Hung
<eddie@fpgeh.com>
Fri, 22 Nov 2019 23:35:08 +0000
(15:35 -0800)
committer
Eddie Hung
<eddie@fpgeh.com>
Fri, 22 Nov 2019 23:35:51 +0000
(15:35 -0800)
CHANGELOG
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diff --git
a/CHANGELOG
b/CHANGELOG
index a49c27b05c76df46a02cc7a44e94c66ea077030a..d9d261fbcbe47c876c3c13741cf216eb45741520 100644
(file)
--- a/
CHANGELOG
+++ b/
CHANGELOG
@@
-53,6
+53,7
@@
Yosys 0.9 .. Yosys 0.9-dev
- Added "check -mapped"
- Added checking of SystemVerilog always block types (always_comb,
always_latch and always_ff)
+ - Added "clkpart" pass
Yosys 0.8 .. Yosys 0.9
----------------------