bug 676: nearly there. just <= vs < to deal with

diff --git a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
index 831472cf7e66bbf7efdfc0a4ff5088da02b6fb2f..151984de03c52a370141d578160675fb2c94952e 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_maxloc.py
@@ -55,7 +55,7 @@ class DDFFirstTestCase(FHDLTestCase):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
     def test_sv_maxloc_1(self):
-        self.sv_maxloc([2,3,0,7])
+        self.sv_maxloc([9,10,11,10])
 
     def tst_sv_maxloc_2(self):
         self.sv_maxloc([3,4,1,5])
@@ -92,13 +92,10 @@ class DDFFirstTestCase(FHDLTestCase):
                 #"sv.addi/mr/sm=ge/dm=ns 4, *4, 0", # r4 = last non-masked value
                 "mtcrf 128, 0",       # clear CR0 (in case VL=0?)
                 "sv.minmax./ff=lt/m=ge 4, *10, 4, 1", # uses r4 as accumulator
+                "sv.svstep/mr/m=ge 3, 0, 6, 1",  # svstep: get vector dststep
                 "sv.creqv *16,*16,*16", # set mask on already-tested
-                "sv.crand *19,*16,0", # set mask on less-than
-                "sv.cror *19,*19,2", # and equal 
-                "sv.svstep/mr/m=so 3, 0, 6, 1",  # svstep: get vector dststep
-                "add 1,1,3",  # accumulate dststep
                 #"sv.addi/dm=1<<r3 *5, 4, 0", # put r4 into vector at r5
-                "bc 12,0, -0x48"            # CR0 lt bit clear, branch back
+                "bc 12,0, -0x34"            # CR0 lt bit clear, branch back
                 #"setvl 3,0,4,0,1,1",        # set MVL=4, VL=MIN(MVL,CTR)
                 #"sv.bc/m=ge 16, 19, -0x3c", # until r10[i]>r4 (and dec CTR)
                         ])