---------- Begin Simulation Statistics ----------
-sim_seconds 5.136797 # Number of seconds simulated
-sim_ticks 5136797077000 # Number of ticks simulated
-final_tick 5136797077000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.136818 # Number of seconds simulated
+sim_ticks 5136817990000 # Number of ticks simulated
+final_tick 5136817990000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 59794 # Simulator instruction rate (inst/s)
-host_op_rate 118197 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 752889080 # Simulator tick rate (ticks/s)
-host_mem_usage 765888 # Number of bytes of host memory used
-host_seconds 6822.78 # Real time elapsed on the host
-sim_insts 407963976 # Number of instructions simulated
-sim_ops 806432115 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2490112 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3136 # Number of bytes read from this memory
+host_inst_rate 178524 # Simulator instruction rate (inst/s)
+host_op_rate 352888 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2247974016 # Simulator tick rate (ticks/s)
+host_mem_usage 798352 # Number of bytes of host memory used
+host_seconds 2285.09 # Real time elapsed on the host
+sim_insts 407944006 # Number of instructions simulated
+sim_ops 806380994 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2472512 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 3008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1077440 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10840448 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14411520 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1077440 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1077440 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9595008 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9595008 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38908 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 49 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 1073088 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10819392 # Number of bytes read from this memory
+system.physmem.bytes_read::total 14368384 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1073088 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1073088 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9566592 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9566592 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38633 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 47 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16835 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 169382 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 225180 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149922 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149922 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 484760 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 610 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 16767 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 169053 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 224506 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 149478 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149478 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 481331 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 586 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 209749 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2110352 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2805546 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 209749 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 209749 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1867897 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1867897 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1867897 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 484760 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 610 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 208901 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2106244 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2797137 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 208901 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 208901 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1862358 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1862358 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1862358 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 481331 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 586 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 209749 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2110352 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4673443 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 225180 # Total number of read requests seen
-system.physmem.writeReqs 149922 # Total number of write requests seen
-system.physmem.cpureqs 389082 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 14411520 # Total number of bytes read from memory
-system.physmem.bytesWritten 9595008 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 14411520 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9595008 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 75 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4150 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 13684 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 14849 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 12992 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::4 13538 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 14702 # Track reads on a per bank basis
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-system.physmem.perBankRdReqs::14 12817 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 15188 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 8767 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 10396 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 8323 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 10488 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 8797 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 10117 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8482 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 9956 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 8780 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 9930 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 9138 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 10179 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 8298 # Track writes on a per bank basis
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+system.physmem.bw_total::cpu.inst 208901 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2106244 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4659495 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 224506 # Total number of read requests seen
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+system.physmem.bytesRead 14368384 # Total number of bytes read from memory
+system.physmem.bytesWritten 9566592 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 14368384 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 9566592 # bytesWritten derated as per pkt->getSize()
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5136797025000 # Total gap between requests
+system.physmem.numWrRetry 164 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5136817938000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
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system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
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+system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 3390959114 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 7646017114 # Sum of mem lat for all requests
-system.physmem.totBusLat 900420000 # Total cycles spent in databus access
-system.physmem.totBankLat 3354638000 # Total cycles spent in bank access
-system.physmem.avgQLat 15063.90 # Average queueing delay per request
-system.physmem.avgBankLat 14902.55 # Average bank access latency per request
+system.physmem.totQLat 3338682949 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 7589868949 # Sum of mem lat for all requests
+system.physmem.totBusLat 897612000 # Total cycles spent in databus access
+system.physmem.totBankLat 3353574000 # Total cycles spent in bank access
+system.physmem.avgQLat 14878.07 # Average queueing delay per request
+system.physmem.avgBankLat 14944.43 # Average bank access latency per request
system.physmem.avgBusLat 4000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 33966.45 # Average memory access latency
-system.physmem.avgRdBW 2.81 # Average achieved read bandwidth in MB/s
-system.physmem.avgWrBW 1.87 # Average achieved write bandwidth in MB/s
-system.physmem.avgConsumedRdBW 2.81 # Average consumed read bandwidth in MB/s
-system.physmem.avgConsumedWrBW 1.87 # Average consumed write bandwidth in MB/s
+system.physmem.avgMemAccLat 33822.49 # Average memory access latency
+system.physmem.avgRdBW 2.80 # Average achieved read bandwidth in MB/s
+system.physmem.avgWrBW 1.86 # Average achieved write bandwidth in MB/s
+system.physmem.avgConsumedRdBW 2.80 # Average consumed read bandwidth in MB/s
+system.physmem.avgConsumedWrBW 1.86 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 11.93 # Average write queue length over time
-system.physmem.readRowHits 198524 # Number of row buffer hits during reads
-system.physmem.writeRowHits 88099 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 88.19 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 58.76 # Row buffer hit rate for writes
-system.physmem.avgGap 13694400.52 # Average gap between requests
-system.iocache.replacements 47577 # number of replacements
-system.iocache.tagsinuse 0.116411 # Cycle average of tags in use
+system.physmem.avgWrQLen 11.19 # Average write queue length over time
+system.physmem.readRowHits 197567 # Number of row buffer hits during reads
+system.physmem.writeRowHits 87961 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 88.04 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 58.85 # Row buffer hit rate for writes
+system.physmem.avgGap 13735394.93 # Average gap between requests
+system.iocache.replacements 47579 # number of replacements
+system.iocache.tagsinuse 0.116428 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47593 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47595 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4991829125000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.116411 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.007276 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.007276 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 912 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 912 # number of ReadReq misses
+system.iocache.warmup_cycle 4991841370000 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.116428 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.007277 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.007277 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 914 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 914 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47632 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47632 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47632 # number of overall misses
-system.iocache.overall_misses::total 47632 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 146446932 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 146446932 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 9011912160 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 9011912160 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 9158359092 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 9158359092 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 9158359092 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 9158359092 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 912 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 912 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47634 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47634 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47634 # number of overall misses
+system.iocache.overall_misses::total 47634 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 143641932 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 143641932 # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 8950549160 # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total 8950549160 # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 9094191092 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 9094191092 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 9094191092 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 9094191092 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 914 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 914 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47632 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47632 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47632 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47632 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47634 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47634 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47634 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47634 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 160577.776316 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 160577.776316 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 192891.955479 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 192891.955479 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 192273.242610 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 192273.242610 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 192273.242610 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 192273.242610 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 57584 # number of cycles access was blocked
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 157157.474836 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 157157.474836 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 191578.535103 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 191578.535103 # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 190918.064660 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 190918.064660 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 190918.064660 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 190918.064660 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 54662 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 7533 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 7510 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 7.644232 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 7.278562 # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 912 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 912 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 914 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 914 # number of ReadReq MSHR misses
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 47632 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 47632 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 47632 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 47632 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 98991992 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 98991992 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6580127962 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 6580127962 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6679119954 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 6679119954 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6679119954 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 6679119954 # number of overall MSHR miss cycles
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 47634 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 47634 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 47634 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 47634 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 96083990 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 96083990 # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 6518807893 # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total 6518807893 # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 6614891883 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 6614891883 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 6614891883 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 6614891883 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 108543.850877 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 108543.850877 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 140841.780009 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 140841.780009 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 140223.378275 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 140223.378275 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 140223.378275 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 140223.378275 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105124.715536 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 105124.715536 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 139529.278532 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 139529.278532 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 138869.124638 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 138869.124638 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 138869.124638 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 138869.124638 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 447871414 # number of cpu cycles simulated
+system.cpu.numCycles 447901761 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.BPredUnit.lookups 86248524 # Number of BP lookups
-system.cpu.BPredUnit.condPredicted 86248524 # Number of conditional branches predicted
-system.cpu.BPredUnit.condIncorrect 1109719 # Number of conditional branches incorrect
-system.cpu.BPredUnit.BTBLookups 81324372 # Number of BTB lookups
-system.cpu.BPredUnit.BTBHits 79248318 # Number of BTB hits
+system.cpu.BPredUnit.lookups 86252881 # Number of BP lookups
+system.cpu.BPredUnit.condPredicted 86252881 # Number of conditional branches predicted
+system.cpu.BPredUnit.condIncorrect 1115345 # Number of conditional branches incorrect
+system.cpu.BPredUnit.BTBLookups 81384938 # Number of BTB lookups
+system.cpu.BPredUnit.BTBHits 79240101 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.fetch.icacheStallCycles 27555812 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 426098303 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86248524 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79248318 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 163629889 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4731856 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 116400 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 62921622 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 35870 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 52533 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 368 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9034264 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 488269 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 3183 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 257896503 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.261731 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.418044 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27570299 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 426189548 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86252881 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79240101 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 163642808 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4755358 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 112288 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 62866127 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 37152 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 52962 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 398 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9042653 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 488997 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 3194 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 257883656 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.262433 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.418145 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 94692515 36.72% 36.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1566812 0.61% 37.32% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71928839 27.89% 65.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 936780 0.36% 65.58% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1600320 0.62% 66.20% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2427387 0.94% 67.14% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1078261 0.42% 67.56% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1378215 0.53% 68.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 82287374 31.91% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 94667319 36.71% 36.71% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1563412 0.61% 37.32% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71921029 27.89% 65.20% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 936098 0.36% 65.57% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1601572 0.62% 66.19% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2435088 0.94% 67.13% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1080780 0.42% 67.55% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1378788 0.53% 68.09% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 82299570 31.91% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 257896503 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192574 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.951385 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31239529 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 60388203 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 159435692 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3249070 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3584009 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 838053376 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 983 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3584009 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 33976924 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37367105 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 10941861 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159620502 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12406102 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834408692 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 19434 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5810292 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4754441 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 7847 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 995994396 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1811420133 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1811419405 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 728 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964426992 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 31567397 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 458567 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 466421 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 28739056 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17094362 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10134243 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1234841 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 965780 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 828292865 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1249354 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 823298492 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 149694 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 22192286 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33736795 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 196434 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 257896503 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.192360 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.384089 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 257883656 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192571 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.951525 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31254353 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 60335803 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 159451505 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3240373 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3601622 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 838158125 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 957 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3601622 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34003643 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37352024 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 10890553 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 159616474 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 12419340 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 834485567 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19816 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5811427 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4758263 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 7797 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 996045264 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1811616758 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1811616222 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964358369 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 31686888 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 460019 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 467360 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 28800044 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17105540 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10151316 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1164746 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 891886 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 828333374 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1249979 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 823307593 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 149787 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 22280168 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 33846252 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 197115 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 257883656 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.192554 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.383898 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 71417814 27.69% 27.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15473003 6.00% 33.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10302554 3.99% 37.69% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7467952 2.90% 40.58% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75909427 29.43% 70.02% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3864522 1.50% 71.52% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72522780 28.12% 99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 788081 0.31% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 150370 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 71395205 27.69% 27.69% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15462696 6.00% 33.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10317630 4.00% 37.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7483312 2.90% 40.58% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75909298 29.44% 70.02% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3861835 1.50% 71.52% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72513968 28.12% 99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 788170 0.31% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 151542 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 257896503 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 257883656 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 363959 34.09% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.09% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 552647 51.76% 85.85% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 151055 14.15% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 365240 34.17% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.17% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 553441 51.78% 85.95% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 150145 14.05% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 310624 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795733525 96.65% 96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 311438 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 795721586 96.65% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 17867181 2.17% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9387162 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 17876340 2.17% 98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9398229 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 823298492 # Type of FU issued
-system.cpu.iq.rate 1.838247 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1067661 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001297 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1905840686 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 851744345 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 818819585 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 303 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 346 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 74 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 824055392 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 137 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1644579 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 823307593 # Type of FU issued
+system.cpu.iq.rate 1.838143 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1068826 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001298 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1905849140 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 851873423 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 818806890 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 220 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 250 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 824064883 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 98 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1642369 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3112367 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 23963 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11499 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1716857 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3123872 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 22910 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11412 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1729878 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1932401 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 11954 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1932382 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 12176 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3584009 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26166561 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2112396 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 829542219 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 307602 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17094362 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10134243 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 718774 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1614614 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11947 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11499 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 653687 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 591965 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1245652 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 821416518 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17449825 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1881973 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3601622 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 26144135 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2117005 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 829583353 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 307079 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 17105540 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 10151316 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 719112 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 1614713 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 12810 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11412 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 656230 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 596856 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1253086 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 821409782 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 17457108 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1897810 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26604955 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83223788 # Number of branches executed
-system.cpu.iew.exec_stores 9155130 # Number of stores executed
-system.cpu.iew.exec_rate 1.834045 # Inst execution rate
-system.cpu.iew.wb_sent 820955265 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 818819659 # cumulative count of insts written-back
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-system.cpu.iew.wb_consumers 1045837145 # num instructions consuming a value
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+system.cpu.iew.exec_branches 83220659 # Number of branches executed
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.828247 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611929 # average fanout of values written-back
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+system.cpu.iew.wb_fanout 0.611910 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 23003299 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1052918 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1114308 # The number of times a branch was mispredicted
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-system.cpu.commit.committed_per_cycle::stdev 2.854625 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 23092364 # The number of squashed insts skipped by commit
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 82565112 32.47% 32.47% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11801317 4.64% 37.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3875007 1.52% 38.63% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74957575 29.47% 68.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2434316 0.96% 69.06% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1480794 0.58% 69.64% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 899910 0.35% 70.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70920339 27.89% 97.89% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5378124 2.11% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 82542979 32.46% 32.46% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11813450 4.65% 37.11% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3859102 1.52% 38.62% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74953678 29.48% 68.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2443754 0.96% 69.06% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1483333 0.58% 69.65% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 886403 0.35% 69.99% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70916473 27.89% 97.88% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5382862 2.12% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 254312494 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407963976 # Number of instructions committed
-system.cpu.commit.committedOps 806432115 # Number of ops (including micro ops) committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
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-system.cpu.commit.membars 473513 # Number of memory barriers committed
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system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
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system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5378124 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5382862 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1078291467 # The number of ROB reads
-system.cpu.rob.rob_writes 1662473587 # The number of ROB writes
-system.cpu.timesIdled 1221266 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 189974911 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9825720160 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407963976 # Number of Instructions Simulated
-system.cpu.committedOps 806432115 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 407963976 # Number of Instructions Simulated
-system.cpu.cpi 1.097821 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.097821 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.910895 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.910895 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1507038080 # number of integer regfile reads
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-system.cpu.misc_regfile_writes 402502 # number of misc regfile writes
-system.cpu.icache.replacements 1052817 # number of replacements
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-system.cpu.icache.total_refs 7916649 # Total number of references to valid blocks.
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-system.cpu.icache.warmup_cycle 55992087000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.984184 # Average occupied blocks per requestor
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-system.cpu.icache.occ_percent::total 0.998016 # Average percentage of cache occupancy
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-system.cpu.icache.ReadReq_misses::total 1117614 # number of ReadReq misses
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-system.cpu.icache.overall_misses::total 1117614 # number of overall misses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13532.322866 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13532.322866 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13532.322866 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13532.322866 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13532.322866 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13532.322866 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 6872 # number of cycles access was blocked
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+system.cpu.idleCycles 190018105 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9825731637 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407944006 # Number of Instructions Simulated
+system.cpu.committedOps 806380994 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 407944006 # Number of Instructions Simulated
+system.cpu.cpi 1.097949 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.097949 # CPI: Total CPI of All Threads
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+system.cpu.ipc_total 0.910789 # IPC: Total IPC of All Threads
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+system.cpu.icache.total_refs 7923866 # Total number of references to valid blocks.
+system.cpu.icache.sampled_refs 1054768 # Sample count of references to valid blocks.
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+system.cpu.icache.warmup_cycle 56004276000 # Cycle when the warmup percentage was hit.
+system.cpu.icache.occ_blocks::cpu.inst 510.988943 # Average occupied blocks per requestor
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+system.cpu.icache.overall_misses::total 1118784 # number of overall misses
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13556.952447 # average overall miss latency
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+system.cpu.icache.blocked_cycles::no_mshrs 9830 # number of cycles access was blocked
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-system.cpu.icache.blocked::no_mshrs 267 # number of cycles access was blocked
+system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked
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-system.cpu.icache.avg_blocked_cycles::no_mshrs 25.737828 # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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-system.cpu.icache.demand_mshr_hits::total 61803 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 61803 # number of overall MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 1055811 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1055811 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1055811 # number of demand (read+write) MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 12467027488 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12467027488 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12467027488 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12467027488 # number of overall MSHR miss cycles
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-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116867 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.010608 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.010608 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.010608 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.010608 # average overall mshr miss latency
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+system.cpu.icache.demand_mshr_hits::total 61527 # number of demand (read+write) MSHR hits
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+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_miss_rate::total 0.116919 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.116919 # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_miss_rate::total 0.116919 # mshr miss rate for demand accesses
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+system.cpu.icache.overall_mshr_miss_rate::total 0.116919 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11821.446902 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11821.446902 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11821.446902 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11821.446902 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11821.446902 # average overall mshr miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11065.435908 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11065.435908 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11065.435908 # average overall miss latency
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+system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10934.423814 # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10934.423814 # average overall miss latency
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system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
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-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9065.435908 # average overall mshr miss latency
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+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8934.423814 # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average overall mshr miss latency
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+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8934.423814 # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8934.423814 # average overall mshr miss latency
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dtb_walker_cache.ReadReq_misses::total 112651 # number of ReadReq misses
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-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12430.528801 # average overall miss latency
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-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12430.528801 # average overall miss latency
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+system.cpu.dtb_walker_cache.overall_accesses::total 246666 # number of overall (read+write) accesses
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+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12465.194189 # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12465.194189 # average overall miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12465.194189 # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12465.194189 # average overall miss latency
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system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 35078 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 35078 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 112651 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 112651 # number of ReadReq MSHR misses
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-system.cpu.dtb_walker_cache.demand_mshr_misses::total 112651 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 112651 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 112651 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 1175009500 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 1175009500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1175009500 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1175009500 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.464157 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for demand accesses
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-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.464157 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.464157 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10430.528801 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average overall mshr miss latency
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-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10430.528801 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10430.528801 # average overall mshr miss latency
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+system.cpu.dtb_walker_cache.writebacks::total 34685 # number of writebacks
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+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 1143312000 # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1143312000 # number of overall MSHR miss cycles
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+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average overall mshr miss latency
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+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10465.194189 # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10465.194189 # average overall mshr miss latency
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.replacements 1661569 # number of replacements
-system.cpu.dcache.tagsinuse 511.994847 # Cycle average of tags in use
-system.cpu.dcache.total_refs 19098471 # Total number of references to valid blocks.
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-system.cpu.dcache.avg_refs 11.490698 # Average number of references to valid blocks.
+system.cpu.dcache.replacements 1662857 # number of replacements
+system.cpu.dcache.tagsinuse 511.994597 # Cycle average of tags in use
+system.cpu.dcache.total_refs 19099158 # Total number of references to valid blocks.
+system.cpu.dcache.sampled_refs 1663369 # Sample count of references to valid blocks.
+system.cpu.dcache.avg_refs 11.482214 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 27804000 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.ReadReq_avg_miss_latency::total 14279.889246 # average ReadReq miss latency
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-system.cpu.dcache.WriteReq_avg_miss_latency::total 30187.982617 # average WriteReq miss latency
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-system.cpu.dcache.demand_avg_miss_latency::total 16262.755301 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 16262.755301 # average overall miss latency
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-system.cpu.dcache.blocked_cycles::no_mshrs 404649 # number of cycles access was blocked
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+system.cpu.dcache.WriteReq_avg_miss_latency::total 30195.887989 # average WriteReq miss latency
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system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 42429 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 1562908 # number of writebacks
-system.cpu.dcache.writebacks::total 1562908 # number of writebacks
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.015897 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026761 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.021116 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.921494 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.921494 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.459120 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.459120 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000465 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000789 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.015897 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102241 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.066103 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000465 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000789 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015897 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102241 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.066103 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 105752 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47411.764478 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52710.068613 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 51060.040674 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10273.896844 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10273.896844 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38410.144154 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38410.144154 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 105752 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47411.764478 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41499.691644 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42036.066370 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56172.148936 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 105752 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47411.764478 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41499.691644 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42036.066370 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-Real time: Jan/14/2013 10:13:32
+Real time: Jan/14/2013 22:52:15
Profiler Stats
--------------
-Elapsed_time_in_seconds: 413
-Elapsed_time_in_minutes: 6.88333
-Elapsed_time_in_hours: 0.114722
-Elapsed_time_in_days: 0.00478009
+Elapsed_time_in_seconds: 462
+Elapsed_time_in_minutes: 7.7
+Elapsed_time_in_hours: 0.128333
+Elapsed_time_in_days: 0.00534722
-Virtual_time_in_seconds: 413.38
-Virtual_time_in_minutes: 6.88967
-Virtual_time_in_hours: 0.114828
-Virtual_time_in_days: 0.00478449
+Virtual_time_in_seconds: 461.58
+Virtual_time_in_minutes: 7.693
+Virtual_time_in_hours: 0.128217
+Virtual_time_in_days: 0.00534236
-Ruby_current_time: 10410012988
+Ruby_current_time: 10409964586
Ruby_start_time: 0
-Ruby_cycles: 10410012988
+Ruby_cycles: 10409964586
-mbytes_resident: 588.977
-mbytes_total: 828.605
-resident_ratio: 0.710814
+mbytes_resident: 590.25
+mbytes_total: 829.625
+resident_ratio: 0.711475
-ruby_cycles_executed: [ 10410012989 10410012989 ]
+ruby_cycles_executed: [ 10409964587 10409964587 ]
Busy Controller Counts:
L1Cache-0:0 L1Cache-1:0
Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154767676 average: 1.00012 | standard deviation: 0.0109603 | 0 154749082 18594 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154388062 average: 1.00012 | standard deviation: 0.0108509 | 0 154369882 18180 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 236 count: 154767675 average: 3.45133 | standard deviation: 5.08508 | 0 152082948 0 0 0 0 0 0 0 926780 2045 1452598 1543 98967 1815 27128 360 207 3 49 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3362 5780 7262 9598 51179 184 505 82 107 136 4 29 2 7 6 6 11 4 5 23 4 17 8 9 15 11 471 4264 10010 17502 13223 43114 813 894 2364 288 781 16 18 42 15 24 13 21 50 10 30 9 26 49 14 23 11 21 20 81 147 128 144 237 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 216 count: 15353007 average: 5.08842 | standard deviation: 8.50498 | 0 13922473 0 0 0 0 0 0 0 116145 265 1232650 928 35561 1127 12313 285 170 3 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 887 725 2463 2782 1967 61 77 31 29 29 1 1 0 0 0 2 3 2 2 2 1 2 4 2 0 3 0 1320 2750 4751 6080 5745 316 282 232 119 113 8 7 4 7 5 6 6 7 1 3 2 8 3 7 3 5 7 6 22 13 57 47 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 236 count: 9752758 average: 5.12122 | standard deviation: 15.1327 | 0 9401253 0 0 0 0 0 0 0 27237 27 167380 295 28892 378 2214 46 13 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 3337 3550 6358 49095 86 397 40 70 107 2 26 2 2 6 3 7 2 2 21 3 13 3 3 13 5 469 953 2931 8561 6761 36978 325 523 2027 157 663 8 10 37 5 16 3 11 42 4 25 4 15 44 4 20 5 11 11 20 101 56 96 215 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 212 count: 128448361 average: 3.11278 | standard deviation: 1.97284 | 0 127661323 0 0 0 0 0 0 0 767930 1689 1597 184 154 39 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1612 1614 805 34 43 19 27 6 1 0 1 2 0 5 0 1 1 0 1 0 0 2 0 4 1 2 2 1978 4253 4132 218 194 166 78 102 6 2 0 1 1 3 3 4 3 1 4 2 3 3 2 3 0 1 3 3 39 33 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_RMW_Read: [binsize: 2 max: 214 count: 526633 average: 6.20648 | standard deviation: 9.4774 | 0 453002 0 0 0 0 0 0 0 10683 54 32916 31 18977 59 9489 9 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 86 385 383 51 15 4 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 9 51 15 121 166 3 9 3 6 2 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 343458 average: 5.69413 | standard deviation: 7.99933 | 0 301439 0 0 0 0 0 0 0 4785 10 18055 105 15383 212 3112 20 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 18 59 41 23 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 25 43 43 31 3 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 343458 average: 3 | standard deviation: 0 | 0 0 0 343458 ]
-miss_latency_NULL: [binsize: 2 max: 236 count: 154767675 average: 3.45133 | standard deviation: 5.08508 | 0 152082948 0 0 0 0 0 0 0 926780 2045 1452598 1543 98967 1815 27128 360 207 3 49 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3362 5780 7262 9598 51179 184 505 82 107 136 4 29 2 7 6 6 11 4 5 23 4 17 8 9 15 11 471 4264 10010 17502 13223 43114 813 894 2364 288 781 16 18 42 15 24 13 21 50 10 30 9 26 49 14 23 11 21 20 81 147 128 144 237 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 2 max: 273 count: 154388061 average: 3.45295 | standard deviation: 5.08106 | 0 151690537 0 0 0 0 0 0 0 932040 1703 1471533 1379 91424 1420 25290 352 173 9 51 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3364 5598 7271 9474 50989 163 513 82 90 127 6 24 4 6 9 8 14 4 5 25 4 18 6 7 12 11 470 4229 10028 17505 13231 42632 784 872 2277 305 815 8 29 37 18 24 23 26 53 8 26 13 20 33 16 22 11 24 27 83 131 126 141 264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 216 count: 15287552 average: 5.10334 | standard deviation: 8.51891 | 0 13850933 0 0 0 0 0 0 0 114268 255 1245097 853 32879 910 11079 294 137 7 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 911 726 2346 2634 1956 44 90 30 21 27 1 2 1 1 2 2 4 3 3 2 2 3 5 1 1 4 0 1351 2838 4647 6042 5788 291 264 240 135 110 0 10 3 8 6 12 9 4 3 5 5 4 3 7 8 2 6 4 27 18 45 48 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 273 count: 9717504 average: 5.12149 | standard deviation: 15.1012 | 0 9364126 0 0 0 0 0 0 0 26595 28 173015 272 26742 292 2182 35 8 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 3242 3694 6375 48918 84 398 40 60 99 3 20 3 1 7 4 9 1 1 23 2 13 0 4 10 4 468 868 2785 8639 6835 36479 336 487 1937 162 695 8 13 32 7 16 4 11 46 3 18 3 12 29 5 11 6 13 18 15 84 59 91 238 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 212 count: 128175950 average: 3.11389 | standard deviation: 1.98122 | 0 127382199 0 0 0 0 0 0 0 775103 1366 1499 157 150 47 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1597 1530 790 33 43 20 20 6 2 0 2 2 0 4 0 1 1 0 1 0 0 2 0 2 0 2 2 1997 4318 4166 202 165 151 106 98 1 6 0 5 1 3 2 7 6 3 1 3 5 4 1 4 3 3 5 5 41 29 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_RMW_Read: [binsize: 2 max: 214 count: 522203 average: 6.16921 | standard deviation: 9.47561 | 0 450065 0 0 0 0 0 0 0 10577 45 32980 16 17715 77 9308 9 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 83 382 379 52 13 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 8 68 17 113 166 3 12 2 7 2 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 342426 average: 5.64732 | standard deviation: 7.89763 | 0 300788 0 0 0 0 0 0 0 5497 9 18942 81 13938 94 2721 14 18 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 17 59 53 20 2 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 5 19 36 39 34 3 3 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 342426 average: 3 | standard deviation: 0 | 0 0 0 342426 ]
+miss_latency_NULL: [binsize: 2 max: 273 count: 154388061 average: 3.45295 | standard deviation: 5.08106 | 0 151690537 0 0 0 0 0 0 0 932040 1703 1471533 1379 91424 1420 25290 352 173 9 51 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3364 5598 7271 9474 50989 163 513 82 90 127 6 24 4 6 9 8 14 4 5 25 4 18 6 7 12 11 470 4229 10028 17505 13231 42632 784 872 2277 305 815 8 29 37 18 24 23 26 53 8 26 13 20 33 16 22 11 24 27 83 131 126 141 264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 0
-miss_latency_LD_NULL: [binsize: 2 max: 216 count: 15353007 average: 5.08842 | standard deviation: 8.50498 | 0 13922473 0 0 0 0 0 0 0 116145 265 1232650 928 35561 1127 12313 285 170 3 48 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 887 725 2463 2782 1967 61 77 31 29 29 1 1 0 0 0 2 3 2 2 2 1 2 4 2 0 3 0 1320 2750 4751 6080 5745 316 282 232 119 113 8 7 4 7 5 6 6 7 1 3 2 8 3 7 3 5 7 6 22 13 57 47 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_NULL: [binsize: 2 max: 236 count: 9752758 average: 5.12122 | standard deviation: 15.1327 | 0 9401253 0 0 0 0 0 0 0 27237 27 167380 295 28892 378 2214 46 13 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 3337 3550 6358 49095 86 397 40 70 107 2 26 2 2 6 3 7 2 2 21 3 13 3 3 13 5 469 953 2931 8561 6761 36978 325 523 2027 157 663 8 10 37 5 16 3 11 42 4 25 4 15 44 4 20 5 11 11 20 101 56 96 215 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH_NULL: [binsize: 2 max: 212 count: 128448361 average: 3.11278 | standard deviation: 1.97284 | 0 127661323 0 0 0 0 0 0 0 767930 1689 1597 184 154 39 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1612 1614 805 34 43 19 27 6 1 0 1 2 0 5 0 1 1 0 1 0 0 2 0 4 1 2 2 1978 4253 4132 218 194 166 78 102 6 2 0 1 1 3 3 4 3 1 4 2 3 3 2 3 0 1 3 3 39 33 15 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 526633 average: 6.20648 | standard deviation: 9.4774 | 0 453002 0 0 0 0 0 0 0 10683 54 32916 31 18977 59 9489 9 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 86 385 383 51 15 4 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 9 51 15 121 166 3 9 3 6 2 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 343458 average: 5.69413 | standard deviation: 7.99933 | 0 301439 0 0 0 0 0 0 0 4785 10 18055 105 15383 212 3112 20 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 18 59 41 23 3 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 25 43 43 31 3 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 343458 average: 3 | standard deviation: 0 | 0 0 0 343458 ]
+miss_latency_LD_NULL: [binsize: 2 max: 216 count: 15287552 average: 5.10334 | standard deviation: 8.51891 | 0 13850933 0 0 0 0 0 0 0 114268 255 1245097 853 32879 910 11079 294 137 7 50 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 911 726 2346 2634 1956 44 90 30 21 27 1 2 1 1 2 2 4 3 3 2 2 3 5 1 1 4 0 1351 2838 4647 6042 5788 291 264 240 135 110 0 10 3 8 6 12 9 4 3 5 5 4 3 7 8 2 6 4 27 18 45 48 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_NULL: [binsize: 2 max: 273 count: 9717504 average: 5.12149 | standard deviation: 15.1012 | 0 9364126 0 0 0 0 0 0 0 26595 28 173015 272 26742 292 2182 35 8 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 756 3242 3694 6375 48918 84 398 40 60 99 3 20 3 1 7 4 9 1 1 23 2 13 0 4 10 4 468 868 2785 8639 6835 36479 336 487 1937 162 695 8 13 32 7 16 4 11 46 3 18 3 12 29 5 11 6 13 18 15 84 59 91 238 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_NULL: [binsize: 2 max: 212 count: 128175950 average: 3.11389 | standard deviation: 1.98122 | 0 127382199 0 0 0 0 0 0 0 775103 1366 1499 157 150 47 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1597 1530 790 33 43 20 20 6 2 0 2 2 0 4 0 1 1 0 1 0 0 2 0 2 0 2 2 1997 4318 4166 202 165 151 106 98 1 6 0 5 1 3 2 7 6 3 1 3 5 4 1 4 3 3 5 5 41 29 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 522203 average: 6.16921 | standard deviation: 9.47561 | 0 450065 0 0 0 0 0 0 0 10577 45 32980 16 17715 77 9308 9 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 83 382 379 52 13 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 8 68 17 113 166 3 12 2 7 2 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 342426 average: 5.64732 | standard deviation: 7.89763 | 0 300788 0 0 0 0 0 0 0 5497 9 18942 81 13938 94 2721 14 18 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 17 59 53 20 2 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 5 19 36 39 34 3 3 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 342426 average: 3 | standard deviation: 0 | 0 0 0 342426 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 37 count: 11102774 average: 0.602872 | standard deviation: 1.4337 | 9428519 3298 1963 3123 1660358 3178 362 299 341 1114 46 54 45 70 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
-Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4899179 average: 0.0429682 | standard deviation: 0.408932 | 4844093 1818 1298 2395 49214 270 22 12 25 32 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 37 count: 6203595 average: 1.04505 | standard deviation: 1.76171 | 4584426 1480 665 728 1611144 2908 340 287 316 1082 46 54 45 70 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4764254 average: 0.043552 | standard deviation: 0.412206 | 4710335 1474 1074 2162 48904 216 21 12 25 31 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 134925 average: 0.0223532 | standard deviation: 0.268086 | 133758 344 224 233 310 54 1 0 0 1 ]
+Total_delay_cycles: [binsize: 1 max: 20 count: 11148135 average: 0.604011 | standard deviation: 1.43412 | 9463752 2800 1716 2621 1672813 2611 326 245 267 831 14 9 33 96 0 0 0 0 0 0 1 ]
+Total_nonPF_delay_cycles: [binsize: 1 max: 9 count: 4908600 average: 0.0392664 | standard deviation: 0.391117 | 4858225 1610 1216 1960 45293 234 18 5 15 24 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 6239535 average: 1.04829 | standard deviation: 1.7624 | 4605527 1190 500 661 1627520 2377 308 240 252 807 14 9 33 96 0 0 0 0 0 0 1 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4783054 average: 0.0397181 | standard deviation: 0.3938 | 4733713 1359 968 1776 44998 181 18 4 15 22 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 125546 average: 0.0220557 | standard deviation: 0.26914 | 124512 251 248 184 295 53 0 1 0 2 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
-user_time: 413
+user_time: 461
system_time: 0
-page_reclaims: 142263
+page_reclaims: 142165
page_faults: 0
swaps: 0
-block_inputs: 16
-block_outputs: 504
+block_inputs: 0
+block_outputs: 544
Network Stats
-------------
-total_msg_count_Control: 8573871 68590968
-total_msg_count_Request_Control: 402900 3223200
-total_msg_count_Response_Data: 8871192 638725824
-total_msg_count_Response_Control: 11214789 89718312
-total_msg_count_Writeback_Data: 4845120 348848640
-total_msg_count_Writeback_Control: 241380 1931040
-total_msgs: 34149252 total_bytes: 1151037984
+total_msg_count_Control: 8609013 68872104
+total_msg_count_Request_Control: 374943 2999544
+total_msg_count_Response_Data: 8904417 641118024
+total_msg_count_Response_Control: 11255862 90046896
+total_msg_count_Writeback_Data: 4892238 352241136
+total_msg_count_Writeback_Control: 242529 1940232
+total_msgs: 34279002 total_bytes: 1157217936
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.0911536
- links_utilized_percent_switch_0_link_0: 0.0987886 bw: 16000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.0835187 bw: 16000 base_latency: 1
-
- outgoing_messages_switch_0_link_0_Request_Control: 70808 566464 [ 70808 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Data: 2104978 151558416 [ 0 2104978 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Control: 1552199 12417592 [ 0 1552199 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Control: 2125604 17004832 [ 2125604 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Response_Data: 64998 4679856 [ 0 64998 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Response_Control: 1603807 12830456 [ 0 30257 1573550 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Data: 1445625 104085000 [ 1445565 60 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Control: 63591 508728 [ 63591 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_0: 0.0914405
+ links_utilized_percent_switch_0_link_0: 0.0993568 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.0835242 bw: 16000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Request_Control: 66162 529296 [ 66162 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 2118929 152562888 [ 0 2118929 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 1549489 12395912 [ 0 1549489 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 2137847 17102776 [ 2137847 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Data: 60658 4367376 [ 0 60658 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Control: 1598104 12784832 [ 0 28048 1570056 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 1449697 104378184 [ 1449587 110 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 60538 484304 [ 60538 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.0193523
- links_utilized_percent_switch_1_link_0: 0.0246033 bw: 16000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.0141014 bw: 16000 base_latency: 1
-
- outgoing_messages_switch_1_link_0_Request_Control: 64117 512936 [ 64117 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Response_Data: 536143 38602296 [ 0 536143 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Response_Control: 233007 1864056 [ 0 233007 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Control: 559123 4472984 [ 559123 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Data: 62234 4480848 [ 0 62234 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Control: 275077 2200616 [ 0 25012 250065 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Data: 169415 12197880 [ 169228 187 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Control: 16869 134952 [ 16869 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 0.0196
+ links_utilized_percent_switch_1_link_0: 0.0247412 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.0144589 bw: 16000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 59384 475072 [ 59384 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 538601 38779272 [ 0 538601 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Control: 244316 1954528 [ 0 244316 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Control: 559677 4477416 [ 559677 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 57457 4136904 [ 0 57457 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 283787 2270296 [ 0 23091 260696 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Data: 181049 13035528 [ 180829 220 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 20305 162440 [ 20305 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.113347
- links_utilized_percent_switch_2_link_0: 0.10197 bw: 16000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.124723 bw: 16000 base_latency: 1
-
- outgoing_messages_switch_2_link_0_Control: 2684727 21477816 [ 2684727 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Response_Data: 221053 15915816 [ 0 221053 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Response_Control: 1940242 15521936 [ 0 116627 1823615 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Writeback_Data: 1615040 116282880 [ 1614793 247 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Writeback_Control: 80460 643680 [ 80460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Control: 173230 1385840 [ 173230 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Request_Control: 133050 1064400 [ 133050 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Response_Data: 2656602 191275344 [ 0 2656602 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Response_Control: 1751674 14013392 [ 0 1751674 0 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_2: 0.11409
+ links_utilized_percent_switch_2_link_0: 0.10253 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.12565 bw: 16000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 2697524 21580192 [ 2697524 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Data: 216185 15565320 [ 0 216185 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Control: 1945956 15567648 [ 0 115204 1830752 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Data: 1630746 117413712 [ 1630416 330 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 80843 646744 [ 80843 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Request_Control: 123851 990808 [ 123851 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 2677877 192807144 [ 0 2677877 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Control: 1763446 14107568 [ 0 1763446 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 2
switch_3_outlinks: 2
-links_utilized_percent_switch_3: 0.00650054
- links_utilized_percent_switch_3_link_0: 0.00499545 bw: 16000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0.00800563 bw: 16000 base_latency: 1
+links_utilized_percent_switch_3: 0.00646039
+ links_utilized_percent_switch_3_link_0: 0.00496714 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.00795363 bw: 16000 base_latency: 1
- outgoing_messages_switch_3_link_0_Control: 173230 1385840 [ 173230 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_Response_Data: 94890 6832080 [ 0 94890 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_Response_Control: 12815 102520 [ 0 12815 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Response_Data: 173230 12472560 [ 0 173230 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Response_Control: 107705 861640 [ 0 107705 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Data: 94424 6798528 [ 0 94424 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 12193 97544 [ 0 12193 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 172147 12394584 [ 0 172147 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Control: 106617 852936 [ 0 106617 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_4_inlinks: 2
switch_4_outlinks: 2
switch_5_inlinks: 5
switch_5_outlinks: 5
-links_utilized_percent_switch_5: 0.0460715
- links_utilized_percent_switch_5_link_0: 0.0987886 bw: 16000 base_latency: 1
- links_utilized_percent_switch_5_link_1: 0.0246033 bw: 16000 base_latency: 1
- links_utilized_percent_switch_5_link_2: 0.10197 bw: 16000 base_latency: 1
- links_utilized_percent_switch_5_link_3: 0.00499545 bw: 16000 base_latency: 1
+links_utilized_percent_switch_5: 0.0463191
+ links_utilized_percent_switch_5_link_0: 0.0993568 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_5_link_1: 0.0247412 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_5_link_2: 0.10253 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_5_link_3: 0.00496714 bw: 16000 base_latency: 1
links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
- outgoing_messages_switch_5_link_0_Request_Control: 70808 566464 [ 70808 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_0_Response_Data: 2104978 151558416 [ 0 2104978 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_0_Response_Control: 1552199 12417592 [ 0 1552199 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_1_Request_Control: 64117 512936 [ 64117 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_1_Response_Data: 536143 38602296 [ 0 536143 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_1_Response_Control: 233007 1864056 [ 0 233007 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_2_Control: 2684727 21477816 [ 2684727 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_2_Response_Data: 221053 15915816 [ 0 221053 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_2_Response_Control: 1940242 15521936 [ 0 116627 1823615 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_2_Writeback_Data: 1615040 116282880 [ 1614793 247 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_2_Writeback_Control: 80460 643680 [ 80460 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_3_Control: 173230 1385840 [ 173230 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_3_Response_Data: 94890 6832080 [ 0 94890 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_3_Response_Control: 12815 102520 [ 0 12815 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Request_Control: 66162 529296 [ 66162 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Data: 2118929 152562888 [ 0 2118929 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Control: 1549489 12395912 [ 0 1549489 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Request_Control: 59384 475072 [ 59384 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Data: 538601 38779272 [ 0 538601 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Control: 244316 1954528 [ 0 244316 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_2_Control: 2697524 21580192 [ 2697524 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_2_Response_Data: 216185 15565320 [ 0 216185 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_2_Response_Control: 1945956 15567648 [ 0 115204 1830752 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_2_Writeback_Data: 1630746 117413712 [ 1630416 330 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_2_Writeback_Control: 80843 646744 [ 80843 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_3_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_3_Response_Data: 94424 6798528 [ 0 94424 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_3_Response_Control: 12193 97544 [ 0 12193 0 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory
- system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 500458
- system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 500458
+ system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 519318
+ system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 519318
system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.ruby.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
- system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 500458 100%
+ system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 519318 100%
Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory
- system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 1625146
- system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 1625146
+ system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 1618529
+ system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 1618529
system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
- system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 80.0217%
- system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 19.9783%
+ system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 80.1036%
+ system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 19.8964%
- system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 1625146 100%
+ system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 1618529 100%
--- L1Cache ---
- Event Counts -
-Load [11657148 3695859 ] 15353007
-Ifetch [108817459 19630908 ] 128448367
-Store [7712341 3253966 ] 10966307
-Inv [30317 25199 ] 55516
-L1_Replacement [2079336 509005 ] 2588341
-Fwd_GETX [15984 15602 ] 31586
-Fwd_GETS [24502 23316 ] 47818
+Load [11524805 3762747 ] 15287552
+Ifetch [108056114 20119843 ] 128175957
+Store [7679126 3245433 ] 10924559
+Inv [28158 23311 ] 51469
+L1_Replacement [2094944 513621 ] 2608565
+Fwd_GETX [15350 14689 ] 30039
+Fwd_GETS [22649 21384 ] 44033
Fwd_GET_INSTR [5 0 ] 5
-Data [1791 950 ] 2741
-Data_Exclusive [1225558 83079 ] 1308637
-DataS_fromL1 [23316 24507 ] 47823
-Data_all_Acks [854313 427607 ] 1281920
-Ack [20626 22980 ] 43606
-Ack_all [22417 23930 ] 46347
-WB_Ack [1509156 186097 ] 1695253
+Data [1528 1030 ] 2558
+Data_Exclusive [1226643 92917 ] 1319560
+DataS_fromL1 [21384 22654 ] 44038
+Data_all_Acks [869374 422000 ] 1291374
+Ack [18918 21076 ] 39994
+Ack_all [20446 22106 ] 42552
+WB_Ack [1510125 201134 ] 1711259
PF_Load [0 0 ] 0
PF_Ifetch [0 0 ] 0
PF_Store [0 0 ] 0
- Transitions -
-NP Load [1283896 113817 ] 1397713
-NP Ifetch [500075 286188 ] 786263
-NP Store [296389 110024 ] 406413
-NP Inv [6714 2646 ] 9360
+NP Load [1280963 125209 ] 1406172
+NP Ifetch [519207 274210 ] 793417
+NP Store [295798 115226 ] 411024
+NP Inv [6575 2932 ] 9507
NP L1_Replacement [0 0 ] 0
NP PF_Load [0 0 ] 0
NP PF_Ifetch [0 0 ] 0
NP PF_Store [0 0 ] 0
-I Load [16574 16247 ] 32821
-I Ifetch [383 392 ] 775
-I Store [7661 9474 ] 17135
+I Load [15537 14910 ] 30447
+I Ifetch [111 223 ] 334
+I Store [7313 8822 ] 16135
I Inv [0 0 ] 0
-I L1_Replacement [14969 11940 ] 26909
+I L1_Replacement [13897 11112 ] 25009
I PF_Load [0 0 ] 0
I PF_Ifetch [0 0 ] 0
I PF_Store [0 0 ] 0
-S Load [793915 479736 ] 1273651
-S Ifetch [108316996 19344327 ] 127661323
-S Store [20626 22981 ] 43607
-S Inv [23501 22199 ] 45700
-S L1_Replacement [555211 310968 ] 866179
+S Load [750790 485617 ] 1236407
+S Ifetch [107536791 19845408 ] 127382199
+S Store [18918 21077 ] 39995
+S Inv [21405 20030 ] 41435
+S L1_Replacement [570922 301375 ] 872297
S PF_Load [0 0 ] 0
S PF_Store [0 0 ] 0
-E Load [3115881 532241 ] 3648122
+E Load [3053717 595327 ] 3649044
E Ifetch [0 0 ] 0
-E Store [118477 30338 ] 148815
-E Inv [42 166 ] 208
-E L1_Replacement [1105264 51360 ] 1156624
-E Fwd_GETX [95 109 ] 204
-E Fwd_GETS [1520 1047 ] 2567
+E Store [120709 32410 ] 153119
+E Inv [68 128 ] 196
+E L1_Replacement [1104096 58886 ] 1162982
+E Fwd_GETX [187 209 ] 396
+E Fwd_GETS [1490 1115 ] 2605
E Fwd_GET_INSTR [1 0 ] 1
E PF_Load [0 0 ] 0
E PF_Store [0 0 ] 0
-M Load [6446882 2553818 ] 9000700
+M Load [6423798 2541684 ] 8965482
M Ifetch [0 0 ] 0
-M Store [7269188 3081149 ] 10350337
-M Inv [60 187 ] 247
-M L1_Replacement [403892 134737 ] 538629
-M Fwd_GETX [15889 15493 ] 31382
-M Fwd_GETS [22982 22269 ] 45251
+M Store [7236388 3067898 ] 10304286
+M Inv [110 220 ] 330
+M L1_Replacement [406029 142248 ] 548277
+M Fwd_GETX [15163 14480 ] 29643
+M Fwd_GETS [21159 20269 ] 41428
M Fwd_GET_INSTR [4 0 ] 4
M PF_Load [0 0 ] 0
M PF_Store [0 0 ] 0
IS Store [0 0 ] 0
IS Inv [0 0 ] 0
IS L1_Replacement [0 0 ] 0
-IS Data_Exclusive [1225558 83079 ] 1308637
-IS DataS_fromL1 [23316 24507 ] 47823
-IS Data_all_Acks [552054 309058 ] 861112
+IS Data_Exclusive [1226643 92917 ] 1319560
+IS DataS_fromL1 [21384 22654 ] 44038
+IS Data_all_Acks [567791 298981 ] 866772
IS PF_Load [0 0 ] 0
IS PF_Store [0 0 ] 0
IM Store [0 0 ] 0
IM Inv [0 0 ] 0
IM L1_Replacement [0 0 ] 0
-IM Data [1791 950 ] 2741
-IM Data_all_Acks [302259 118549 ] 420808
+IM Data [1528 1030 ] 2558
+IM Data_all_Acks [301583 123019 ] 424602
IM Ack [0 0 ] 0
IM PF_Load [0 0 ] 0
IM PF_Store [0 0 ] 0
SM Store [0 0 ] 0
SM Inv [0 1 ] 1
SM L1_Replacement [0 0 ] 0
-SM Ack [20626 22980 ] 43606
-SM Ack_all [22417 23930 ] 46347
+SM Ack [18918 21076 ] 39994
+SM Ack_all [20446 22106 ] 42552
SM PF_Load [0 0 ] 0
SM PF_Store [0 0 ] 0
IS_I PF_Store [0 0 ] 0
M_I Load [0 0 ] 0
-M_I Ifetch [5 1 ] 6
+M_I Ifetch [5 2 ] 7
M_I Store [0 0 ] 0
M_I Inv [0 0 ] 0
M_I L1_Replacement [0 0 ] 0
M_I Fwd_GETX [0 0 ] 0
M_I Fwd_GETS [0 0 ] 0
M_I Fwd_GET_INSTR [0 0 ] 0
-M_I WB_Ack [1509156 186097 ] 1695253
+M_I WB_Ack [1510125 201134 ] 1711259
M_I PF_Load [0 0 ] 0
M_I PF_Store [0 0 ] 0
PF_IS_I Data_all_Acks [0 0 ] 0
Cache Stats: system.ruby.l1_cntrl1.L1IcacheMemory
- system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 286580
- system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 286580
+ system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 274433
+ system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 274433
system.ruby.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
system.ruby.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
system.ruby.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
system.ruby.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100%
- system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 286580 100%
+ system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 274433 100%
Cache Stats: system.ruby.l1_cntrl1.L1DcacheMemory
- system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 272543
- system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 272543
+ system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 285244
+ system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 285244
system.ruby.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
system.ruby.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
system.ruby.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
- system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 47.7224%
- system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 52.2776%
+ system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 49.1225%
+ system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 50.8775%
- system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 272543 100%
+ system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 285244 100%
Cache Stats: system.ruby.l2_cntrl0.L2cacheMemory
- system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 252639
- system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 252639
+ system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 246224
+ system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 246224
system.ruby.l2_cntrl0.L2cacheMemory_total_prefetches: 0
system.ruby.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.ruby.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
- system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 31.2133%
- system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 6.11307%
- system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 62.6732%
- system.ruby.l2_cntrl0.L2cacheMemory_request_type_UPGRADE: 0.000395822%
+ system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 30.3882%
+ system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 6.26543%
+ system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 63.346%
+ system.ruby.l2_cntrl0.L2cacheMemory_request_type_UPGRADE: 0.000406134%
- system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 252639 100%
+ system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 246224 100%
--- L2Cache ---
- Event Counts -
-L1_GET_INSTR [787039 ] 787039
-L1_GETS [1430768 ] 1430768
-L1_GETX [423555 ] 423555
-L1_UPGRADE [43607 ] 43607
-L1_PUTX [1695253 ] 1695253
+L1_GET_INSTR [793751 ] 793751
+L1_GETS [1436868 ] 1436868
+L1_GETX [427161 ] 427161
+L1_UPGRADE [39995 ] 39995
+L1_PUTX [1711259 ] 1711259
L1_PUTX_old [0 ] 0
Fwd_L1_GETX [0 ] 0
Fwd_L1_GETS [0 ] 0
Fwd_L1_GET_INSTR [0 ] 0
-L2_Replacement [94736 ] 94736
-L2_Replacement_clean [12969 ] 12969
-Mem_Data [173230 ] 173230
-Mem_Ack [107705 ] 107705
-WB_Data [47491 ] 47491
-WB_Data_clean [579 ] 579
-Ack [1875 ] 1875
-Ack_all [7047 ] 7047
-Unblock [47823 ] 47823
+L2_Replacement [94211 ] 94211
+L2_Replacement_clean [12406 ] 12406
+Mem_Data [172147 ] 172147
+Mem_Ack [106617 ] 106617
+WB_Data [43746 ] 43746
+WB_Data_clean [622 ] 622
+Ack [1695 ] 1695
+Ack_all [6892 ] 6892
+Unblock [44038 ] 44038
Unblock_Cancel [0 ] 0
-Exclusive_Unblock [1775792 ] 1775792
+Exclusive_Unblock [1786714 ] 1786714
MEM_Inv [0 ] 0
- Transitions -
-NP L1_GET_INSTR [15439 ] 15439
-NP L1_GETS [31039 ] 31039
-NP L1_GETX [126752 ] 126752
+NP L1_GET_INSTR [15422 ] 15422
+NP L1_GETS [30790 ] 30790
+NP L1_GETX [125935 ] 125935
NP L1_PUTX [0 ] 0
NP L1_PUTX_old [0 ] 0
-SS L1_GET_INSTR [771381 ] 771381
-SS L1_GETS [74079 ] 74079
-SS L1_GETX [2996 ] 2996
-SS L1_UPGRADE [43606 ] 43606
+SS L1_GET_INSTR [778075 ] 778075
+SS L1_GETS [73026 ] 73026
+SS L1_GETX [2798 ] 2798
+SS L1_UPGRADE [39994 ] 39994
SS L1_PUTX [0 ] 0
SS L1_PUTX_old [0 ] 0
-SS L2_Replacement [237 ] 237
-SS L2_Replacement_clean [6602 ] 6602
+SS L2_Replacement [248 ] 248
+SS L2_Replacement_clean [6448 ] 6448
SS MEM_Inv [0 ] 0
-M L1_GET_INSTR [213 ] 213
-M L1_GETS [1277598 ] 1277598
-M L1_GETX [262215 ] 262215
+M L1_GET_INSTR [249 ] 249
+M L1_GETS [1288770 ] 1288770
+M L1_GETX [268388 ] 268388
M L1_PUTX [0 ] 0
M L1_PUTX_old [0 ] 0
-M L2_Replacement [94369 ] 94369
-M L2_Replacement_clean [6042 ] 6042
+M L2_Replacement [93815 ] 93815
+M L2_Replacement_clean [5580 ] 5580
M MEM_Inv [0 ] 0
MT L1_GET_INSTR [5 ] 5
-MT L1_GETS [47818 ] 47818
-MT L1_GETX [31586 ] 31586
-MT L1_PUTX [1695253 ] 1695253
+MT L1_GETS [44033 ] 44033
+MT L1_GETX [30039 ] 30039
+MT L1_PUTX [1711259 ] 1711259
MT L1_PUTX_old [0 ] 0
-MT L2_Replacement [130 ] 130
-MT L2_Replacement_clean [325 ] 325
+MT L2_Replacement [148 ] 148
+MT L2_Replacement_clean [378 ] 378
MT MEM_Inv [0 ] 0
-M_I L1_GET_INSTR [1 ] 1
+M_I L1_GET_INSTR [0 ] 0
M_I L1_GETS [0 ] 0
-M_I L1_GETX [2 ] 2
+M_I L1_GETX [0 ] 0
M_I L1_UPGRADE [0 ] 0
M_I L1_PUTX [0 ] 0
M_I L1_PUTX_old [0 ] 0
-M_I Mem_Ack [107705 ] 107705
+M_I Mem_Ack [106617 ] 106617
M_I MEM_Inv [0 ] 0
MT_I L1_GET_INSTR [0 ] 0
MT_I L1_UPGRADE [0 ] 0
MT_I L1_PUTX [0 ] 0
MT_I L1_PUTX_old [0 ] 0
-MT_I WB_Data [93 ] 93
+MT_I WB_Data [117 ] 117
MT_I WB_Data_clean [0 ] 0
-MT_I Ack_all [37 ] 37
+MT_I Ack_all [31 ] 31
MT_I MEM_Inv [0 ] 0
MCT_I L1_GET_INSTR [0 ] 0
MCT_I L1_UPGRADE [0 ] 0
MCT_I L1_PUTX [0 ] 0
MCT_I L1_PUTX_old [0 ] 0
-MCT_I WB_Data [154 ] 154
+MCT_I WB_Data [213 ] 213
MCT_I WB_Data_clean [0 ] 0
-MCT_I Ack_all [171 ] 171
+MCT_I Ack_all [165 ] 165
I_I L1_GET_INSTR [0 ] 0
I_I L1_GETS [0 ] 0
I_I L1_UPGRADE [0 ] 0
I_I L1_PUTX [0 ] 0
I_I L1_PUTX_old [0 ] 0
-I_I Ack [1645 ] 1645
-I_I Ack_all [6602 ] 6602
+I_I Ack [1454 ] 1454
+I_I Ack_all [6448 ] 6448
S_I L1_GET_INSTR [0 ] 0
S_I L1_GETS [0 ] 0
S_I L1_UPGRADE [0 ] 0
S_I L1_PUTX [0 ] 0
S_I L1_PUTX_old [0 ] 0
-S_I Ack [230 ] 230
-S_I Ack_all [237 ] 237
+S_I Ack [241 ] 241
+S_I Ack_all [248 ] 248
S_I MEM_Inv [0 ] 0
ISS L1_GET_INSTR [0 ] 0
ISS L1_PUTX_old [0 ] 0
ISS L2_Replacement [0 ] 0
ISS L2_Replacement_clean [0 ] 0
-ISS Mem_Data [31039 ] 31039
+ISS Mem_Data [30790 ] 30790
ISS MEM_Inv [0 ] 0
IS L1_GET_INSTR [0 ] 0
IS L1_PUTX_old [0 ] 0
IS L2_Replacement [0 ] 0
IS L2_Replacement_clean [0 ] 0
-IS Mem_Data [15439 ] 15439
+IS Mem_Data [15422 ] 15422
IS MEM_Inv [0 ] 0
IM L1_GET_INSTR [0 ] 0
IM L1_PUTX_old [0 ] 0
IM L2_Replacement [0 ] 0
IM L2_Replacement_clean [0 ] 0
-IM Mem_Data [126752 ] 126752
+IM Mem_Data [125935 ] 125935
IM MEM_Inv [0 ] 0
SS_MB L1_GET_INSTR [0 ] 0
-SS_MB L1_GETS [179 ] 179
+SS_MB L1_GETS [193 ] 193
SS_MB L1_GETX [0 ] 0
SS_MB L1_UPGRADE [1 ] 1
SS_MB L1_PUTX [0 ] 0
SS_MB L2_Replacement [0 ] 0
SS_MB L2_Replacement_clean [0 ] 0
SS_MB Unblock_Cancel [0 ] 0
-SS_MB Exclusive_Unblock [46602 ] 46602
+SS_MB Exclusive_Unblock [42792 ] 42792
SS_MB MEM_Inv [0 ] 0
MT_MB L1_GET_INSTR [0 ] 0
-MT_MB L1_GETS [55 ] 55
-MT_MB L1_GETX [4 ] 4
+MT_MB L1_GETS [56 ] 56
+MT_MB L1_GETX [1 ] 1
MT_MB L1_UPGRADE [0 ] 0
MT_MB L1_PUTX [0 ] 0
MT_MB L1_PUTX_old [0 ] 0
MT_MB L2_Replacement [0 ] 0
MT_MB L2_Replacement_clean [0 ] 0
MT_MB Unblock_Cancel [0 ] 0
-MT_MB Exclusive_Unblock [1729190 ] 1729190
+MT_MB Exclusive_Unblock [1743922 ] 1743922
MT_MB MEM_Inv [0 ] 0
M_MB L1_GET_INSTR [0 ] 0
MT_IIB L1_PUTX_old [0 ] 0
MT_IIB L2_Replacement [0 ] 0
MT_IIB L2_Replacement_clean [0 ] 0
-MT_IIB WB_Data [47176 ] 47176
-MT_IIB WB_Data_clean [579 ] 579
-MT_IIB Unblock [68 ] 68
+MT_IIB WB_Data [43375 ] 43375
+MT_IIB WB_Data_clean [622 ] 622
+MT_IIB Unblock [41 ] 41
MT_IIB MEM_Inv [0 ] 0
MT_IB L1_GET_INSTR [0 ] 0
MT_IB L1_PUTX_old [0 ] 0
MT_IB L2_Replacement [0 ] 0
MT_IB L2_Replacement_clean [0 ] 0
-MT_IB WB_Data [68 ] 68
+MT_IB WB_Data [41 ] 41
MT_IB WB_Data_clean [0 ] 0
MT_IB Unblock_Cancel [0 ] 0
MT_IB MEM_Inv [0 ] 0
MT_SB L1_PUTX_old [0 ] 0
MT_SB L2_Replacement [0 ] 0
MT_SB L2_Replacement_clean [0 ] 0
-MT_SB Unblock [47755 ] 47755
+MT_SB Unblock [43997 ] 43997
MT_SB MEM_Inv [0 ] 0
Memory controller: system.ruby.dir_cntrl0.memBuffer:
- memory_total_requests: 268120
- memory_reads: 173230
- memory_writes: 94890
- memory_refreshes: 540175
- memory_total_request_delays: 1021995
- memory_delays_per_request: 3.81171
- memory_delays_in_input_queue: 40655
- memory_delays_behind_head_of_bank_queue: 7571
- memory_delays_stalled_at_head_of_bank_queue: 973769
- memory_stalls_for_bank_busy: 964415
+ memory_total_requests: 266571
+ memory_reads: 172147
+ memory_writes: 94424
+ memory_refreshes: 536635
+ memory_total_request_delays: 1016562
+ memory_delays_per_request: 3.81348
+ memory_delays_in_input_queue: 40063
+ memory_delays_behind_head_of_bank_queue: 7489
+ memory_delays_stalled_at_head_of_bank_queue: 969010
+ memory_stalls_for_bank_busy: 959685
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 2119
- memory_stalls_for_bus: 7204
+ memory_stalls_for_arbitration: 2157
+ memory_stalls_for_bus: 7147
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 20
- memory_stalls_for_read_read_turnaround: 11
- accesses_per_bank: 8668 7929 8035 8011 8299 8319 8160 8260 8417 8211 8203 8373 8266 8099 8224 7214 8411 8364 8280 8158 8504 8396 9002 8309 8657 8409 8646 9176 9084 8998 8838 8200
+ memory_stalls_for_read_write_turnaround: 15
+ memory_stalls_for_read_read_turnaround: 6
+ accesses_per_bank: 8989 7974 8010 8055 8487 8273 8235 8188 8380 8237 8148 8446 8268 8048 8068 7184 8265 8304 8191 8114 8382 8281 8178 8162 8416 8296 8511 9107 9086 9056 8973 8259
--- Directory ---
- Event Counts -
-Fetch [173230 ] 173230
-Data [94890 ] 94890
-Memory_Data [173230 ] 173230
-Memory_Ack [94890 ] 94890
+Fetch [172147 ] 172147
+Data [94424 ] 94424
+Memory_Data [172147 ] 172147
+Memory_Ack [94424 ] 94424
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
-CleanReplacement [12815 ] 12815
+CleanReplacement [12193 ] 12193
- Transitions -
-I Fetch [173230 ] 173230
+I Fetch [172147 ] 172147
I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
-M Data [94890 ] 94890
+M Data [94424 ] 94424
M DMA_READ [0 ] 0
M DMA_WRITE [0 ] 0
-M CleanReplacement [12815 ] 12815
+M CleanReplacement [12193 ] 12193
IM Fetch [0 ] 0
IM Data [0 ] 0
-IM Memory_Data [173230 ] 173230
+IM Memory_Data [172147 ] 172147
IM DMA_READ [0 ] 0
IM DMA_WRITE [0 ] 0
MI Fetch [0 ] 0
MI Data [0 ] 0
-MI Memory_Ack [94890 ] 94890
+MI Memory_Ack [94424 ] 94424
MI DMA_READ [0 ] 0
MI DMA_WRITE [0 ] 0
projects / gem5.git / commitdiff