use verilog namespace to export mila configuration

diff --git a/README b/README
index 895100703f422d2162fae84988da8ea12eccbc6d..a2239f92af50c10dac9e0f8268047a83b92c36fa 100644 (file)
--- a/README
+++ b/README
@@ -41,8 +41,8 @@ RangeDetector and EdgeDector terms not tested.
 
 [> Examples:
 Have a look at http://github.com/Florent-Kermarrec/misoc-de0nano
-miio.py : Led & Switch Test controlled by Python Host.
-mila.py : Logic Analyzer controlled by Python Host.
+test_miio.py : Led & Switch Test controlled by Python Host.
+test_mila.py : Logic Analyzer controlled by Python Host.
 
 [> Contact
 E-mail: florent@enjoy-digital.fr

diff --git a/miscope/mila.py b/miscope/mila.py
index 3edbdd908dbb4228861f60749be46e087d83aa7d..7678a51351b641fdb92112c89f7ab6099ccc2add 100644 (file)
--- a/miscope/mila.py
+++ b/miscope/mila.py
@@ -36,7 +36,7 @@ class MiLa(Module, AutoCSR):
                        recorder_dat_source = self.rle.source
                self.comb += recorder_dat_source.connect(recorder.dat_sink)
 
-       def get_csv(self, layout):
+       def get_csv(self, layout, ns):
                r = ""
                def format_line(*args):
                        return ",".join(args) + "\n"
@@ -46,5 +46,5 @@ class MiLa(Module, AutoCSR):
                r += format_line("config", "with_rle", str(int(self.with_rle)))
 
                for e in layout:
-                       r += format_line("layout", e.backtrace[-1][0], str(flen(e)))
+                       r += format_line("layout", ns.get_name(e), str(flen(e)))
                return r