--- /dev/null
+read_verilog ../common/add_sub.v
+hierarchy -top top
+proc
+equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 10 t:LUT4
+select -assert-none t:LUT4 t:FACADE_IO %% t:* %D
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dff # Constrain all select calls below inside the top module
select -assert-count 1 t:FACADE_FF
-select -assert-none t:FACADE_FF %% t:* %D
+select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D
design -load read
hierarchy -top dffe
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd dffe # Constrain all select calls below inside the top module
select -assert-count 2 t:FACADE_FF t:LUT4
-select -assert-none t:FACADE_FF t:LUT4 %% t:* %D
+select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 9 t:LUT4
-select -assert-none t:LUT4 %% t:* %D
+select -assert-none t:LUT4 t:FACADE_IO %% t:* %D