(no commit message)
authorlkcl <lkcl@web>
Sun, 14 Nov 2021 15:11:59 +0000 (15:11 +0000)
committerIkiWiki <ikiwiki.info>
Sun, 14 Nov 2021 15:11:59 +0000 (15:11 +0000)
docs/pinmux.mdwn

index 93c25292452aee6bdfeac2254c1ee830b0a19327..275ee179eb17e8416928eedec591d01e36474c3d 100644 (file)
@@ -4,6 +4,7 @@ Links:
 
 * <http://www2.eng.cam.ac.uk/~dmh/4b7/resource/section14.htm>
 * <https://ftp.libre-soc.org/Pin_Control_Subsystem_Overview.pdf>
+* <https://bugs.libre-soc.org/show_bug.cgi?id=50>
 
 Managing IO on an ASIC is nowhere near as simple as on an FPGA.
 An FPGA has built-in IO Pads, the wires terminate inside an