(aux_truncdfsf2): New pattern.

(movsf): Use it instead of invalid SUBREG and truncdfsf2.

From-SVN: r9902

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 19d53d4c7b7148873effbdfd7afdda8b16e55d05..da113eda76ab39c316014c536477d40b958a3e06 100644 (file)
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -2712,6 +2712,13 @@
   "frsp %0,%1"
   [(set_attr "type" "fp")])
 
+(define_insn "aux_truncdfsf2"
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+       (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))]
+  "! TARGET_POWERPC && TARGET_HARD_FLOAT"
+  "frsp %0,%1"
+  [(set_attr "type" "fp")])
+
 (define_insn "negsf2"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
        (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
@@ -4082,11 +4089,12 @@
          /* If operands[1] is a register, it may have double-precision data
             in it, so truncate it to single precision.  We need not do
             this for POWERPC.  */
-         if (! TARGET_POWERPC && GET_CODE (operands[1]) == REG)
+         if (! TARGET_POWERPC && TARGET_HARD_FLOAT
+             && GET_CODE (operands[1]) == REG)
            {
-             rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
-             emit_insn (gen_truncdfsf2 (newreg,
-                                        gen_rtx (SUBREG, DFmode, operands[1], 0)));
+             rtx newreg
+               = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
+             emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
              operands[1] = newreg;
            }