return r->nr_samples ? r->nr_samples - 1 : 0;
}
-static void r600_blit_decompress_depth(struct pipe_context *ctx,
- struct r600_texture *texture,
- struct r600_texture *staging,
- unsigned first_level, unsigned last_level,
- unsigned first_layer, unsigned last_layer,
- unsigned first_sample, unsigned last_sample)
+static void si_blit_decompress_depth(struct pipe_context *ctx,
+ struct r600_texture *texture,
+ struct r600_texture *staging,
+ unsigned first_level, unsigned last_level,
+ unsigned first_layer, unsigned last_layer,
+ unsigned first_sample, unsigned last_sample)
{
struct si_context *rctx = (struct si_context *)ctx;
unsigned layer, level, sample, checked_last_layer, max_layer, max_sample;
}
}
-void r600_decompress_color_textures(struct si_context *rctx,
- struct si_textures_info *textures)
+void si_decompress_color_textures(struct si_context *rctx,
+ struct si_textures_info *textures)
{
unsigned i;
unsigned mask = textures->compressed_colortex_mask;
rctx->b.b.resource_copy_region = r600_resource_copy_region;
rctx->b.b.blit = si_blit;
rctx->b.b.flush_resource = si_flush_resource;
- rctx->b.blit_decompress_depth = r600_blit_decompress_depth;
+ rctx->b.blit_decompress_depth = si_blit_decompress_depth;
}
#include "si.h"
#include "si_pipe.h"
-void r600_upload_index_buffer(struct si_context *rctx,
- struct pipe_index_buffer *ib, unsigned count)
+void si_upload_index_buffer(struct si_context *rctx,
+ struct pipe_index_buffer *ib, unsigned count)
{
u_upload_data(rctx->b.uploader, 0, count * ib->index_size,
ib->user_buffer, &ib->offset, &ib->buffer);
/* Flush if there's not enough space. */
if (num_dw > RADEON_MAX_CMDBUF_DWORDS) {
- radeonsi_flush(&ctx->b.b, NULL, RADEON_FLUSH_ASYNC);
+ si_flush(&ctx->b.b, NULL, RADEON_FLUSH_ASYNC);
}
}
/*
* pipe_context
*/
-void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
- unsigned flags)
+void si_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
+ unsigned flags)
{
struct si_context *rctx = (struct si_context *)ctx;
struct pipe_query *render_cond = NULL;
struct pipe_fence_handle **fence,
unsigned flags)
{
- radeonsi_flush(ctx, fence,
- flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
+ si_flush(ctx, fence,
+ flags & PIPE_FLUSH_END_OF_FRAME ? RADEON_FLUSH_END_OF_FRAME : 0);
}
static void r600_flush_from_winsys(void *ctx, unsigned flags)
{
- radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
+ si_flush((struct pipe_context*)ctx, NULL, flags);
}
static void r600_destroy_context(struct pipe_context *context)
rctx->screen = rscreen;
si_init_blit_functions(rctx);
- r600_init_query_functions(rctx);
- r600_init_context_resource_functions(rctx);
+ si_init_query_functions(rctx);
+ si_init_context_resource_functions(rctx);
si_init_compute_functions(rctx);
if (rscreen->b.info.has_uvd) {
- rctx->b.b.create_video_codec = radeonsi_uvd_create_decoder;
- rctx->b.b.create_video_buffer = radeonsi_video_buffer_create;
+ rctx->b.b.create_video_codec = si_uvd_create_decoder;
+ rctx->b.b.create_video_buffer = si_video_buffer_create;
} else {
rctx->b.b.create_video_codec = vl_create_decoder;
rctx->b.b.create_video_buffer = vl_video_buffer_create;
return "X.Org";
}
-const char *r600_get_llvm_processor_name(enum radeon_family family)
+const char *si_get_llvm_processor_name(enum radeon_family family)
{
switch (family) {
case CHIP_TAHITI: return "tahiti";
//TODO: select these params by asic
switch (param) {
case PIPE_COMPUTE_CAP_IR_TARGET: {
- const char *gpu = r600_get_llvm_processor_name(rscreen->b.family);
+ const char *gpu = si_get_llvm_processor_name(rscreen->b.family);
if (ret) {
sprintf(ret, "%s-r600--", gpu);
}
void si_init_blit_functions(struct si_context *rctx);
void si_flush_depth_textures(struct si_context *rctx,
struct si_textures_info *textures);
-void r600_decompress_color_textures(struct si_context *rctx,
- struct si_textures_info *textures);
+void si_decompress_color_textures(struct si_context *rctx,
+ struct si_textures_info *textures);
/* si_buffer.c */
-void r600_upload_index_buffer(struct si_context *rctx,
- struct pipe_index_buffer *ib, unsigned count);
+void si_upload_index_buffer(struct si_context *rctx,
+ struct pipe_index_buffer *ib, unsigned count);
/* si_pipe.c */
-void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
- unsigned flags);
-const char *r600_get_llvm_processor_name(enum radeon_family family);
+void si_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
+ unsigned flags);
+const char *si_get_llvm_processor_name(enum radeon_family family);
/* si_query.c */
-void r600_init_query_functions(struct si_context *rctx);
+void si_init_query_functions(struct si_context *rctx);
/* si_resource.c */
-void r600_init_context_resource_functions(struct si_context *r600);
+void si_init_context_resource_functions(struct si_context *r600);
/* si_translate.c */
-void r600_translate_index_buffer(struct si_context *r600,
- struct pipe_index_buffer *ib,
- unsigned count);
+void si_translate_index_buffer(struct si_context *r600,
+ struct pipe_index_buffer *ib,
+ unsigned count);
#if R600_TRACE_CS
-void r600_trace_emit(struct si_context *rctx);
+void si_trace_emit(struct si_context *rctx);
#endif
/* si_compute.c */
void si_init_compute_functions(struct si_context *rctx);
/* si_uvd.c */
-struct pipe_video_codec *radeonsi_uvd_create_decoder(struct pipe_context *context,
- const struct pipe_video_codec *templ);
+struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
+ const struct pipe_video_codec *templ);
-struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe,
- const struct pipe_video_buffer *tmpl);
+struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
+ const struct pipe_video_buffer *tmpl);
/*
* common helpers
}
}
-static inline unsigned r600_tex_aniso_filter(unsigned filter)
+static inline unsigned si_tex_aniso_filter(unsigned filter)
{
if (filter <= 1) return 0;
if (filter <= 2) return 1;
}
/* 12.4 fixed-point */
-static INLINE unsigned r600_pack_float_12p4(float x)
+static INLINE unsigned si_pack_float_12p4(float x)
{
return x <= 0 ? 0 :
x >= 4096 ? 0xffff : x * 16;
}
}
-void r600_init_query_functions(struct si_context *rctx)
+void si_init_query_functions(struct si_context *rctx)
{
rctx->b.b.create_query = r600_create_query;
rctx->b.b.destroy_query = r600_destroy_query;
screen->resource_destroy = u_resource_destroy_vtbl;
}
-void r600_init_context_resource_functions(struct si_context *r600)
+void si_init_context_resource_functions(struct si_context *r600)
{
r600->b.b.transfer_map = u_transfer_map_vtbl;
r600->b.b.transfer_flush_region = u_default_transfer_flush_region;
shader->selector ? shader->selector->tokens : NULL);
memset(&binary, 0, sizeof(binary));
radeon_llvm_compile(mod, &binary,
- r600_get_llvm_processor_name(rctx->screen->b.family), dump);
+ si_get_llvm_processor_name(rctx->screen->b.family), dump);
if (dump && ! binary.disassembled) {
fprintf(stderr, "SI CODE:\n");
for (i = 0; i < binary.code_size; i+=4 ) {
}
/* Divide by two, because 0.5 = 1 pixel. */
si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
- S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
- S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
+ S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
+ S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
tmp = (unsigned)state->line_width * 8;
si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
si_flush_depth_textures(rctx, &rctx->samplers[i]);
}
if (rctx->samplers[i].compressed_colortex_mask) {
- r600_decompress_color_textures(rctx, &rctx->samplers[i]);
+ si_decompress_color_textures(rctx, &rctx->samplers[i]);
}
}
}
ib.offset = rctx->index_buffer.offset + info->start * ib.index_size;
/* Translate or upload, if needed. */
- r600_translate_index_buffer(rctx, &ib, info->count);
+ si_translate_index_buffer(rctx, &ib, info->count);
if (ib.user_buffer && !ib.buffer) {
- r600_upload_index_buffer(rctx, &ib, info->count);
+ si_upload_index_buffer(rctx, &ib, info->count);
}
}
#include "si_pipe.h"
-void r600_translate_index_buffer(struct si_context *r600,
- struct pipe_index_buffer *ib,
- unsigned count)
+void si_translate_index_buffer(struct si_context *r600,
+ struct pipe_index_buffer *ib,
+ unsigned count)
{
struct pipe_resource *out_buffer = NULL;
unsigned out_offset;
/**
* creates an video buffer with an UVD compatible memory layout
*/
-struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe,
- const struct pipe_video_buffer *tmpl)
+struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
+ const struct pipe_video_buffer *tmpl)
{
struct si_context *ctx = (struct si_context *)pipe;
struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
/**
* creates an UVD compatible decoder
*/
-struct pipe_video_codec *radeonsi_uvd_create_decoder(struct pipe_context *context,
- const struct pipe_video_codec *templ)
+struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
+ const struct pipe_video_codec *templ)
{
return ruvd_create_decoder(context, templ, radeonsi_uvd_set_dtb);
}