gcc 4.6 is allowed in Yosys code. This will change in future releases.
In general Yosys uses "int" instead of "size_t". To avoid compiler
-warnings for implicit type casts, always use "SIZE(foobar)" instead
-of "foobar.size()". (the macro SIZE() is defined by kernel/yosys.h)
+warnings for implicit type casts, always use "GetSize(foobar)" instead
+of "foobar.size()". (GetSize() is defined by kernel/yosys.h)
Use range-based for loops whenever applicable.
*f << stringf(")\n");
for (auto &p : cell->connections()) {
RTLIL::SigSpec sig = sigmap(p.second);
- for (int i = 0; i < SIZE(sig); i++)
+ for (int i = 0; i < GetSize(sig); i++)
if (sig.size() == 1)
net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name)));
else
if (!norename && cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q"))
{
RTLIL::SigSpec sig = cell->getPort("\\Q");
- if (SIZE(sig) != 1 || sig.is_fully_const())
+ if (GetSize(sig) != 1 || sig.is_fully_const())
goto no_special_reg_name;
RTLIL::Wire *wire = sig[0].wire;
log("Calling DPI function `%s' and returning `%s':\n", fname.c_str(), rtype.c_str());
- log_assert(SIZE(args) == SIZE(argtypes));
- for (int i = 0; i < SIZE(args); i++) {
+ log_assert(GetSize(args) == GetSize(argtypes));
+ for (int i = 0; i < GetSize(args); i++) {
if (argtypes[i] == "real") {
log(" arg %d (%s): %f\n", i, argtypes[i].c_str(), args[i]->asReal(args[i]->is_signed));
value_store[i].f64 = args[i]->asReal(args[i]->is_signed);
// create initial assignments for the temporary signals
if ((flag_nolatches || always->get_bool_attribute("\\nolatches") || current_module->get_bool_attribute("\\nolatches")) && !found_clocked_sync) {
- subst_rvalue_map = subst_lvalue_from.to_sigbit_map(RTLIL::SigSpec(RTLIL::State::Sx, SIZE(subst_lvalue_from)));
+ subst_rvalue_map = subst_lvalue_from.to_sigbit_map(RTLIL::SigSpec(RTLIL::State::Sx, GetSize(subst_lvalue_from)));
} else {
addChunkActions(current_case->actions, subst_lvalue_to, subst_lvalue_from);
}
{
RTLIL::SigSpec new_lhs, new_rhs;
- log_assert(SIZE(lhs) == SIZE(rhs));
- for (int i = 0; i < SIZE(lhs); i++) {
+ log_assert(GetSize(lhs) == GetSize(rhs));
+ for (int i = 0; i < GetSize(lhs); i++) {
if (lhs[i].wire == nullptr)
continue;
new_lhs.append(lhs[i]);
{
std::vector<RTLIL::SigChunk> chunks = sig.chunks();
- for (int i = 0; i < SIZE(chunks); i++)
+ for (int i = 0; i < GetSize(chunks); i++)
{
RTLIL::SigChunk &chunk = chunks[i];
if (chunk.wire == NULL)
lvalue.replace(subst_lvalue_map.stdmap());
if (ast->type == AST_ASSIGN_EQ) {
- for (int i = 0; i < SIZE(unmapped_lvalue); i++)
+ for (int i = 0; i < GetSize(unmapped_lvalue); i++)
subst_rvalue_map.set(unmapped_lvalue[i], rvalue[i]);
}
subst_lvalue_map.save();
subst_rvalue_map.save();
- for (int i = 0; i < SIZE(this_case_eq_lvalue); i++)
+ for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
subst_lvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
RTLIL::CaseRule *backup_case = current_case;
sw->cases.push_back(default_case);
}
- for (int i = 0; i < SIZE(this_case_eq_lvalue); i++)
+ for (int i = 0; i < GetSize(this_case_eq_lvalue); i++)
subst_rvalue_map.set(this_case_eq_lvalue[i], this_case_eq_ltemp[i]);
this_case_eq_lvalue.replace(subst_lvalue_map.stdmap());
shift_val = current_module->Sub(NEW_ID, RTLIL::SigSpec(source_width - width), shift_val, fake_ast->children[1]->is_signed);
fake_ast->children[1]->is_signed = true;
}
- if (SIZE(shift_val) >= 32)
+ if (GetSize(shift_val) >= 32)
fake_ast->children[1]->is_signed = true;
RTLIL::SigSpec sig = binop2rtlil(fake_ast, "$shiftx", width, fake_ast->children[0]->genRTLIL(), shift_val);
delete left_at_zero_ast;
{
AstNode *index_expr = nullptr;
- for (int i = 0; 2*i < SIZE(id2ast->multirange_dimensions); i++)
+ for (int i = 0; 2*i < GetSize(id2ast->multirange_dimensions); i++)
{
- if (SIZE(children[0]->children) < i)
+ if (GetSize(children[0]->children) < i)
log_error("Insufficient number of array indices for %s at %s:%d.\n", log_id(str), filename.c_str(), linenum);
AstNode *new_index_expr = children[0]->children[i]->children.at(0)->clone();
index_expr = new AstNode(AST_ADD, new AstNode(AST_MUL, index_expr, AstNode::mkconst_int(id2ast->multirange_dimensions[2*i-1], true)), new_index_expr);
}
- for (int i = SIZE(id2ast->multirange_dimensions)/1; i < SIZE(children[0]->children); i++)
+ for (int i = GetSize(id2ast->multirange_dimensions)/1; i < GetSize(children[0]->children); i++)
children.push_back(children[0]->children[i]->clone());
delete children[0];
RTLIL::Const arg_value = buf->bitsAsConst();
if (arg_value.as_bool())
- arg_value = const_sub(arg_value, 1, false, false, SIZE(arg_value));
+ arg_value = const_sub(arg_value, 1, false, false, GetSize(arg_value));
delete buf;
uint32_t result = 0;
rtype = RTLIL::unescape_id(dpi_decl->children.at(0)->str);
fname = RTLIL::unescape_id(dpi_decl->children.at(1)->str);
- for (int i = 2; i < SIZE(dpi_decl->children); i++)
+ for (int i = 2; i < GetSize(dpi_decl->children); i++)
{
- if (i-2 >= SIZE(children))
+ if (i-2 >= GetSize(children))
log_error("Insufficient number of arguments in DPI function call at %s:%d.\n", filename.c_str(), linenum);
argtypes.push_back(RTLIL::unescape_id(dpi_decl->children.at(i)->str));
celltype = RTLIL::escape_id(celltype);
AstNode *cell = new AstNode(AST_CELL, new AstNode(AST_CELLTYPE));
- cell->str = prefix.substr(0, SIZE(prefix)-1);
+ cell->str = prefix.substr(0, GetSize(prefix)-1);
cell->children[0]->str = celltype;
for (auto attr : decl->attributes)
bool param_upto = current_scope[str]->range_valid && current_scope[str]->range_swapped;
int param_offset = current_scope[str]->range_valid ? current_scope[str]->range_right : 0;
int param_width = current_scope[str]->range_valid ? current_scope[str]->range_left - current_scope[str]->range_right + 1 :
- SIZE(current_scope[str]->children[0]->bits);
+ GetSize(current_scope[str]->children[0]->bits);
int tmp_range_left = children[0]->range_left, tmp_range_right = children[0]->range_right;
if (param_upto) {
tmp_range_left = (param_width + 2*param_offset) - children[0]->range_right - 1;
if (children[0]->type == AST_CONSTANT && children[0]->bits_only_01()) {
std::vector<AstNode*> new_children;
new_children.push_back(children[0]);
- for (int i = 1; i < SIZE(children); i++) {
+ for (int i = 1; i < GetSize(children); i++) {
AstNode *child = children[i];
log_assert(child->type == AST_COND);
for (auto v : child->children) {
continue;
if (v->type == AST_CONSTANT && v->bits_only_01()) {
if (v->bits == children[0]->bits) {
- while (i+1 < SIZE(children))
+ while (i+1 < GetSize(children))
delete children[++i];
goto keep_const_cond;
}
if (inst->GetCin()->IsGnd()) {
module->addAdd(RTLIL::escape_id(inst->Name()), IN1, IN2, out, SIGNED);
} else {
- RTLIL::SigSpec tmp = module->addWire(NEW_ID, SIZE(out));
+ RTLIL::SigSpec tmp = module->addWire(NEW_ID, GetSize(out));
module->addAdd(NEW_ID, IN1, IN2, tmp, SIGNED);
module->addAdd(RTLIL::escape_id(inst->Name()), tmp, net_map.at(inst->GetCin()), out, false);
}
cell->parameters["\\CLK_ENABLE"] = false;
cell->parameters["\\CLK_POLARITY"] = true;
cell->parameters["\\TRANSPARENT"] = false;
- cell->parameters["\\ABITS"] = SIZE(addr);
- cell->parameters["\\WIDTH"] = SIZE(data);
+ cell->parameters["\\ABITS"] = GetSize(addr);
+ cell->parameters["\\WIDTH"] = GetSize(data);
cell->setPort("\\CLK", RTLIL::State::S0);
cell->setPort("\\ADDR", addr);
cell->setPort("\\DATA", data);
cell->parameters["\\CLK_ENABLE"] = false;
cell->parameters["\\CLK_POLARITY"] = true;
cell->parameters["\\PRIORITY"] = 0;
- cell->parameters["\\ABITS"] = SIZE(addr);
- cell->parameters["\\WIDTH"] = SIZE(data);
- cell->setPort("\\EN", RTLIL::SigSpec(net_map.at(inst->GetControl())).repeat(SIZE(data)));
+ cell->parameters["\\ABITS"] = GetSize(addr);
+ cell->parameters["\\WIDTH"] = GetSize(data);
+ cell->setPort("\\EN", RTLIL::SigSpec(net_map.at(inst->GetControl())).repeat(GetSize(data)));
cell->setPort("\\CLK", RTLIL::State::S0);
cell->setPort("\\ADDR", addr);
cell->setPort("\\DATA", data);
RTLIL::SigSpec conn;
if (cell->hasPort(RTLIL::escape_id(port_name)))
conn = cell->getPort(RTLIL::escape_id(port_name));
- while (SIZE(conn) <= port_offset) {
+ while (GetSize(conn) <= port_offset) {
if (pr->GetPort()->GetDir() != DIR_IN)
- conn.append(module->addWire(NEW_ID, port_offset - SIZE(conn)));
+ conn.append(module->addWire(NEW_ID, port_offset - GetSize(conn)));
conn.append(RTLIL::State::Sz);
}
conn.replace(port_offset, net_map.at(pr->GetNet()));
ast_stack.push_back(current_ast);
} design {
ast_stack.pop_back();
- log_assert(SIZE(ast_stack) == 0);
+ log_assert(GetSize(ast_stack) == 0);
for (auto &it : default_attr_list)
delete it.second;
default_attr_list.clear();
RTLIL::Const RTLIL::const_shr(const RTLIL::Const &arg1, const RTLIL::Const &arg2, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;
- extend_u0(arg1_ext, std::max(result_len, SIZE(arg1)), signed1);
+ extend_u0(arg1_ext, std::max(result_len, GetSize(arg1)), signed1);
return const_shift_worker(arg1_ext, arg2, false, +1, result_len);
}
int width = cell->parameters.at("\\WIDTH").as_int();
std::vector<RTLIL::State> t = cell->parameters.at("\\LUT").bits;
- while (SIZE(t) < (1 << width))
+ while (GetSize(t) < (1 << width))
t.push_back(RTLIL::S0);
t.resize(1 << width);
RTLIL::State sel = arg1.bits.at(i);
std::vector<RTLIL::State> new_t;
if (sel == RTLIL::S0)
- new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + SIZE(t)/2);
+ new_t = std::vector<RTLIL::State>(t.begin(), t.begin() + GetSize(t)/2);
else if (sel == RTLIL::S1)
- new_t = std::vector<RTLIL::State>(t.begin() + SIZE(t)/2, t.end());
+ new_t = std::vector<RTLIL::State>(t.begin() + GetSize(t)/2, t.end());
else
- for (int j = 0; j < SIZE(t)/2; j++)
- new_t.push_back(t[j] == t[j + SIZE(t)/2] ? t[j] : RTLIL::Sx);
+ for (int j = 0; j < GetSize(t)/2; j++)
+ new_t.push_back(t[j] == t[j + GetSize(t)/2] ? t[j] : RTLIL::Sx);
t.swap(new_t);
}
- log_assert(SIZE(t) == 1);
+ log_assert(GetSize(t) == 1);
return t;
}
assign_map.apply(sig);
#ifndef NDEBUG
RTLIL::SigSpec current_val = values_map(sig);
- for (int i = 0; i < SIZE(current_val); i++)
+ for (int i = 0; i < GetSize(current_val); i++)
log_assert(current_val[i].wire != NULL || current_val[i] == value.bits[i]);
#endif
values_map.add(sig, RTLIL::SigSpec(value));
if (sig_p.is_fully_def() && sig_g.is_fully_def() && sig_ci.is_fully_def())
{
- RTLIL::Const coval(RTLIL::Sx, SIZE(sig_co));
+ RTLIL::Const coval(RTLIL::Sx, GetSize(sig_co));
bool carry = sig_ci.as_bool();
- for (int i = 0; i < SIZE(coval); i++) {
+ for (int i = 0; i < GetSize(coval); i++) {
carry = (sig_g[i] == RTLIL::S1) || (sig_p[i] == RTLIL::S1 && carry);
coval.bits[i] = carry ? RTLIL::S1 : RTLIL::S0;
}
set(sig_co, coval);
}
else
- set(sig_co, RTLIL::Const(RTLIL::Sx, SIZE(sig_co)));
+ set(sig_co, RTLIL::Const(RTLIL::Sx, GetSize(sig_co)));
return true;
}
{
RTLIL::SigSpec sig_c = cell->getPort("\\C");
RTLIL::SigSpec sig_x = cell->getPort("\\X");
- int width = SIZE(sig_c);
+ int width = GetSize(sig_c);
if (!eval(sig_a, undef, cell))
return false;
RTLIL::Const t3 = const_and(sig_c.as_const(), t1, false, false, width);
RTLIL::Const val_x = const_or(t2, t3, false, false, width);
- for (int i = 0; i < SIZE(val_y); i++)
+ for (int i = 0; i < GetSize(val_y); i++)
if (val_y.bits[i] == RTLIL::Sx)
val_x.bits[i] = RTLIL::Sx;
RTLIL::SigSpec sig_co = cell->getPort("\\CO");
bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
- sig_a.extend_u0(SIZE(sig_y), signed_a);
- sig_b.extend_u0(SIZE(sig_y), signed_b);
+ sig_a.extend_u0(GetSize(sig_y), signed_a);
+ sig_b.extend_u0(GetSize(sig_y), signed_b);
bool carry = sig_ci[0] == RTLIL::S1;
bool b_inv = sig_bi[0] == RTLIL::S1;
- for (int i = 0; i < SIZE(sig_y); i++)
+ for (int i = 0; i < GetSize(sig_y); i++)
{
RTLIL::SigSpec x_inputs = { sig_a[i], sig_b[i], sig_bi[0] };
return false;
}
- RTLIL::Const result(0, SIZE(cell->getPort("\\Y")));
+ RTLIL::Const result(0, GetSize(cell->getPort("\\Y")));
if (!macc.eval(result))
log_abort();
return module_cost;
}
- log("Warning: Can't determine cost of %s cell (%d parameters).\n", log_id(type), SIZE(parameters));
+ log("Warning: Can't determine cost of %s cell (%d parameters).\n", log_id(type), GetSize(parameters));
return 1;
}
size_t nnl_pos = str.find_last_not_of('\n');
if (nnl_pos == std::string::npos)
- log_newline_count += SIZE(str);
+ log_newline_count += GetSize(str);
else
- log_newline_count = SIZE(str) - nnl_pos - 1;
+ log_newline_count = GetSize(str) - nnl_pos - 1;
if (log_hasher)
log_hasher->update(str);
for (auto &port : ports)
{
- if (SIZE(port.in_a) == 0 && SIZE(port.in_b) == 0)
+ if (GetSize(port.in_a) == 0 && GetSize(port.in_b) == 0)
continue;
- if (SIZE(port.in_a) < SIZE(port.in_b))
+ if (GetSize(port.in_a) < GetSize(port.in_b))
std::swap(port.in_a, port.in_b);
- if (SIZE(port.in_a) == 1 && SIZE(port.in_b) == 0 && !port.is_signed && !port.do_subtract) {
+ if (GetSize(port.in_a) == 1 && GetSize(port.in_b) == 0 && !port.is_signed && !port.do_subtract) {
bit_ports.append(port.in_a);
continue;
}
if (port.in_a.is_fully_const() && port.in_b.is_fully_const()) {
RTLIL::Const v = port.in_a.as_const();
- if (SIZE(port.in_b))
+ if (GetSize(port.in_b))
v = const_mul(v, port.in_b.as_const(), port.is_signed, port.is_signed, width);
if (port.do_subtract)
off = const_sub(off, v, port.is_signed, port.is_signed, width);
}
if (port.is_signed) {
- while (SIZE(port.in_a) > 1 && port.in_a[SIZE(port.in_a)-1] == port.in_a[SIZE(port.in_a)-2])
- port.in_a.remove(SIZE(port.in_a)-1);
- while (SIZE(port.in_b) > 1 && port.in_b[SIZE(port.in_b)-1] == port.in_b[SIZE(port.in_b)-2])
- port.in_b.remove(SIZE(port.in_b)-1);
+ while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == port.in_a[GetSize(port.in_a)-2])
+ port.in_a.remove(GetSize(port.in_a)-1);
+ while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == port.in_b[GetSize(port.in_b)-2])
+ port.in_b.remove(GetSize(port.in_b)-1);
} else {
- while (SIZE(port.in_a) > 1 && port.in_a[SIZE(port.in_a)-1] == RTLIL::S0)
- port.in_a.remove(SIZE(port.in_a)-1);
- while (SIZE(port.in_b) > 1 && port.in_b[SIZE(port.in_b)-1] == RTLIL::S0)
- port.in_b.remove(SIZE(port.in_b)-1);
+ while (GetSize(port.in_a) > 1 && port.in_a[GetSize(port.in_a)-1] == RTLIL::S0)
+ port.in_a.remove(GetSize(port.in_a)-1);
+ while (GetSize(port.in_b) > 1 && port.in_b[GetSize(port.in_b)-1] == RTLIL::S0)
+ port.in_b.remove(GetSize(port.in_b)-1);
}
new_ports.push_back(port);
int config_width = cell->getParam("\\CONFIG_WIDTH").as_int();
int config_cursor = 0;
- log_assert(SIZE(config_bits) >= config_width);
+ log_assert(GetSize(config_bits) >= config_width);
int num_bits = 0;
if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 1;
if (config_bits[config_cursor++] == RTLIL::S1) num_bits |= 8;
int port_a_cursor = 0;
- while (port_a_cursor < SIZE(port_a))
+ while (port_a_cursor < GetSize(port_a))
{
log_assert(config_cursor + 2 + 2*num_bits <= config_width);
}
log_assert(config_cursor == config_width);
- log_assert(port_a_cursor == SIZE(port_a));
+ log_assert(port_a_cursor == GetSize(port_a));
}
void to_cell(RTLIL::Cell *cell) const
int max_size = 0, num_bits = 0;
for (auto &port : ports) {
- max_size = std::max(max_size, SIZE(port.in_a));
- max_size = std::max(max_size, SIZE(port.in_b));
+ max_size = std::max(max_size, GetSize(port.in_a));
+ max_size = std::max(max_size, GetSize(port.in_b));
}
while (max_size)
for (auto &port : ports)
{
- if (SIZE(port.in_a) == 0)
+ if (GetSize(port.in_a) == 0)
continue;
config_bits.push_back(port.is_signed ? RTLIL::S1 : RTLIL::S0);
config_bits.push_back(port.do_subtract ? RTLIL::S1 : RTLIL::S0);
- int size_a = SIZE(port.in_a);
+ int size_a = GetSize(port.in_a);
for (int i = 0; i < num_bits; i++)
config_bits.push_back(size_a & (1 << i) ? RTLIL::S1 : RTLIL::S0);
- int size_b = SIZE(port.in_b);
+ int size_b = GetSize(port.in_b);
for (int i = 0; i < num_bits; i++)
config_bits.push_back(size_b & (1 << i) ? RTLIL::S1 : RTLIL::S0);
cell->setPort("\\A", port_a);
cell->setPort("\\B", bit_ports);
cell->setParam("\\CONFIG", config_bits);
- cell->setParam("\\CONFIG_WIDTH", SIZE(config_bits));
- cell->setParam("\\A_WIDTH", SIZE(port_a));
- cell->setParam("\\B_WIDTH", SIZE(bit_ports));
+ cell->setParam("\\CONFIG_WIDTH", GetSize(config_bits));
+ cell->setParam("\\A_WIDTH", GetSize(port_a));
+ cell->setParam("\\B_WIDTH", GetSize(bit_ports));
}
bool eval(RTLIL::Const &result) const
return false;
RTLIL::Const summand;
- if (SIZE(port.in_b) == 0)
- summand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, SIZE(result));
+ if (GetSize(port.in_b) == 0)
+ summand = const_pos(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));
else
- summand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, SIZE(result));
+ summand = const_mul(port.in_a.as_const(), port.in_b.as_const(), port.is_signed, port.is_signed, GetSize(result));
if (port.do_subtract)
- result = const_sub(result, summand, port.is_signed, port.is_signed, SIZE(result));
+ result = const_sub(result, summand, port.is_signed, port.is_signed, GetSize(result));
else
- result = const_add(result, summand, port.is_signed, port.is_signed, SIZE(result));
+ result = const_add(result, summand, port.is_signed, port.is_signed, GetSize(result));
}
for (auto bit : bit_ports) {
if (bit.wire)
return false;
- result = const_add(result, bit.data, false, false, SIZE(result));
+ result = const_add(result, bit.data, false, false, GetSize(result));
}
return true;
void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
{
- for (int i = 0; i < SIZE(sig); i++) {
+ for (int i = 0; i < GetSize(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
if (bit.wire)
database[bit].ports.insert(PortInfo(cell, port, i));
void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
{
- for (int i = 0; i < SIZE(sig); i++) {
+ for (int i = 0; i < GetSize(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
if (bit.wire)
database[bit].ports.erase(PortInfo(cell, port, i));
database.clear();
for (auto wire : module->wires())
if (wire->port_input || wire->port_output)
- for (int i = 0; i < SIZE(wire); i++) {
+ for (int i = 0; i < GetSize(wire); i++) {
RTLIL::SigBit bit = sigmap(RTLIL::SigBit(wire, i));
if (bit.wire && wire->port_input)
database[bit].is_input = true;
for (auto &it2 : it.second->attributes)
log_assert(!it2.first.empty());
if (it.second->port_id) {
- log_assert(SIZE(ports) >= it.second->port_id);
+ log_assert(GetSize(ports) >= it.second->port_id);
log_assert(ports.at(it.second->port_id-1) == it.first);
log_assert(it.second->port_input || it.second->port_output);
- if (SIZE(ports_declared) < it.second->port_id)
+ if (GetSize(ports_declared) < it.second->port_id)
ports_declared.resize(it.second->port_id);
log_assert(ports_declared[it.second->port_id-1] == false);
ports_declared[it.second->port_id-1] = true;
}
for (auto port_declared : ports_declared)
log_assert(port_declared == true);
- log_assert(SIZE(ports) == SIZE(ports_declared));
+ log_assert(GetSize(ports) == GetSize(ports_declared));
for (auto &it : memories) {
log_assert(it.first == it.second->name);
return;
if (type == "$mux" || type == "$pmux") {
- parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
+ parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
if (type == "$pmux")
- parameters["\\S_WIDTH"] = SIZE(connections_["\\S"]);
+ parameters["\\S_WIDTH"] = GetSize(connections_["\\S"]);
check();
return;
}
if (type == "$lut") {
- parameters["\\WIDTH"] = SIZE(connections_["\\A"]);
+ parameters["\\WIDTH"] = GetSize(connections_["\\A"]);
return;
}
if (type == "$fa") {
- parameters["\\WIDTH"] = SIZE(connections_["\\Y"]);
+ parameters["\\WIDTH"] = GetSize(connections_["\\Y"]);
return;
}
if (type == "$lcu") {
- parameters["\\WIDTH"] = SIZE(connections_["\\CO"]);
+ parameters["\\WIDTH"] = GetSize(connections_["\\CO"]);
return;
}
else if (parameters.count("\\A_SIGNED") == 0)
parameters["\\A_SIGNED"] = false;
}
- parameters["\\A_WIDTH"] = SIZE(connections_["\\A"]);
+ parameters["\\A_WIDTH"] = GetSize(connections_["\\A"]);
}
if (connections_.count("\\B")) {
else if (parameters.count("\\B_SIGNED") == 0)
parameters["\\B_SIGNED"] = false;
}
- parameters["\\B_WIDTH"] = SIZE(connections_["\\B"]);
+ parameters["\\B_WIDTH"] = GetSize(connections_["\\B"]);
}
if (connections_.count("\\Y"))
- parameters["\\Y_WIDTH"] = SIZE(connections_["\\Y"]);
+ parameters["\\Y_WIDTH"] = GetSize(connections_["\\Y"]);
check();
}
{
wire = NULL;
data = value.bits;
- width = SIZE(data);
+ width = GetSize(data);
offset = 0;
}
{
wire = NULL;
data = RTLIL::Const(str).bits;
- width = SIZE(data);
+ width = GetSize(data);
offset = 0;
}
{
wire = NULL;
data = RTLIL::Const(val, width).bits;
- this->width = SIZE(data);
+ this->width = GetSize(data);
offset = 0;
}
{
wire = NULL;
data = RTLIL::Const(bit, width).bits;
- this->width = SIZE(data);
+ this->width = GetSize(data);
offset = 0;
}
std::map<RTLIL::SigBit, RTLIL::SigBit> rules;
- for (int i = 0; i < SIZE(pattern.bits_); i++)
+ for (int i = 0; i < GetSize(pattern.bits_); i++)
if (pattern.bits_[i].wire != NULL)
rules[pattern.bits_[i]] = with.bits_[i];
unpack();
other->unpack();
- for (int i = 0; i < SIZE(bits_); i++) {
+ for (int i = 0; i < GetSize(bits_); i++) {
auto it = rules.find(bits_[i]);
if (it != rules.end())
other->bits_[i] = it->second;
std::vector<RTLIL::SigBit> new_bits, new_other_bits;
- new_bits.resize(SIZE(bits_));
+ new_bits.resize(GetSize(bits_));
if (other != NULL)
- new_other_bits.resize(SIZE(bits_));
+ new_other_bits.resize(GetSize(bits_));
int k = 0;
- for (int i = 0; i < SIZE(bits_); i++) {
+ for (int i = 0; i < GetSize(bits_); i++) {
if (bits_[i].wire != NULL && pattern.count(bits_[i]))
continue;
if (other != NULL)
new_other_bits.resize(k);
bits_.swap(new_bits);
- width_ = SIZE(bits_);
+ width_ = GetSize(bits_);
if (other != NULL) {
other->bits_.swap(new_other_bits);
- other->width_ = SIZE(other->bits_);
+ other->width_ = GetSize(other->bits_);
}
check();
cover("kernel.rtlil.sigspec.remove_const.packed");
std::vector<RTLIL::SigChunk> new_chunks;
- new_chunks.reserve(SIZE(chunks_));
+ new_chunks.reserve(GetSize(chunks_));
width_ = 0;
for (auto &chunk : chunks_)
{
cover("kernel.rtlil.sigspec.check.unpacked");
- log_assert(width_ == SIZE(bits_));
+ log_assert(width_ == GetSize(bits_));
log_assert(chunks_.empty());
}
}
cover("kernel.rtlil.sigspec.is_wire");
pack();
- return SIZE(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
+ return GetSize(chunks_) == 1 && chunks_[0].wire && chunks_[0].wire->width == width_;
}
bool RTLIL::SigSpec::is_chunk() const
cover("kernel.rtlil.sigspec.is_chunk");
pack();
- return SIZE(chunks_) == 1;
+ return GetSize(chunks_) == 1;
}
bool RTLIL::SigSpec::is_fully_const() const
cover("kernel.rtlil.sigspec.as_bool");
pack();
- log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+ log_assert(is_fully_const() && GetSize(chunks_) <= 1);
if (width_)
return RTLIL::Const(chunks_[0].data).as_bool();
return false;
cover("kernel.rtlil.sigspec.as_int");
pack();
- log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+ log_assert(is_fully_const() && GetSize(chunks_) <= 1);
if (width_)
return RTLIL::Const(chunks_[0].data).as_int(is_signed);
return 0;
cover("kernel.rtlil.sigspec.as_const");
pack();
- log_assert(is_fully_const() && SIZE(chunks_) <= 1);
+ log_assert(is_fully_const() && GetSize(chunks_) <= 1);
if (width_)
return chunks_[0].data;
return RTLIL::Const();
sigmap->apply(sig);
std::vector<int> vec;
- vec.reserve(SIZE(sig));
+ vec.reserve(GetSize(sig));
for (auto &bit : sig)
if (bit.wire == NULL) {
Macc macc;
macc.from_cell(cell);
- std::vector<int> tmp(SIZE(y), ez->FALSE);
+ std::vector<int> tmp(GetSize(y), ez->FALSE);
for (auto &port : macc.ports)
{
std::vector<int> in_a = importDefSigSpec(port.in_a, timestep);
std::vector<int> in_b = importDefSigSpec(port.in_b, timestep);
- while (SIZE(in_a) < SIZE(y))
+ while (GetSize(in_a) < GetSize(y))
in_a.push_back(port.is_signed && !in_a.empty() ? in_a.back() : ez->FALSE);
- in_a.resize(SIZE(y));
+ in_a.resize(GetSize(y));
- if (SIZE(in_b))
+ if (GetSize(in_b))
{
- while (SIZE(in_b) < SIZE(y))
+ while (GetSize(in_b) < GetSize(y))
in_b.push_back(port.is_signed && !in_b.empty() ? in_b.back() : ez->FALSE);
- in_b.resize(SIZE(y));
+ in_b.resize(GetSize(y));
- for (int i = 0; i < SIZE(in_b); i++) {
+ for (int i = 0; i < GetSize(in_b); i++) {
std::vector<int> shifted_a(in_a.size(), ez->FALSE);
for (int j = i; j < int(in_a.size()); j++)
shifted_a.at(j) = in_a.at(j-i);
}
}
- for (int i = 0; i < SIZE(b); i++) {
- std::vector<int> val(SIZE(y), ez->FALSE);
+ for (int i = 0; i < GetSize(b); i++) {
+ std::vector<int> val(GetSize(y), ez->FALSE);
val.at(0) = b.at(i);
tmp = ez->vec_add(tmp, val);
}
int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
- ez->assume(ez->vec_eq(undef_y, std::vector<int>(SIZE(y), ez->OR(undef_any_a, undef_any_b))));
+ ez->assume(ez->vec_eq(undef_y, std::vector<int>(GetSize(y), ez->OR(undef_any_a, undef_any_b))));
undefGating(y, tmp, undef_y);
}
std::vector<int> lut;
for (auto bit : cell->getParam("\\LUT").bits)
lut.push_back(bit == RTLIL::S1 ? ez->TRUE : ez->FALSE);
- while (SIZE(lut) < (1 << SIZE(a)))
+ while (GetSize(lut) < (1 << GetSize(a)))
lut.push_back(ez->FALSE);
- lut.resize(1 << SIZE(a));
+ lut.resize(1 << GetSize(a));
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
- std::vector<int> t(lut), u(SIZE(t), ez->FALSE);
+ std::vector<int> t(lut), u(GetSize(t), ez->FALSE);
- for (int i = SIZE(a)-1; i >= 0; i--)
+ for (int i = GetSize(a)-1; i >= 0; i--)
{
- std::vector<int> t0(t.begin(), t.begin() + SIZE(t)/2);
- std::vector<int> t1(t.begin() + SIZE(t)/2, t.end());
+ std::vector<int> t0(t.begin(), t.begin() + GetSize(t)/2);
+ std::vector<int> t1(t.begin() + GetSize(t)/2, t.end());
- std::vector<int> u0(u.begin(), u.begin() + SIZE(u)/2);
- std::vector<int> u1(u.begin() + SIZE(u)/2, u.end());
+ std::vector<int> u0(u.begin(), u.begin() + GetSize(u)/2);
+ std::vector<int> u1(u.begin() + GetSize(u)/2, u.end());
t = ez->vec_ite(a[i], t1, t0);
u = ez->vec_ite(undef_a[i], ez->vec_or(ez->vec_xor(t0, t1), ez->vec_or(u0, u1)), ez->vec_ite(a[i], u1, u0));
}
- log_assert(SIZE(t) == 1);
- log_assert(SIZE(u) == 1);
+ log_assert(GetSize(t) == 1);
+ log_assert(GetSize(u) == 1);
undefGating(y, t, u);
ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort("\\Y"), timestep), u));
}
else
{
std::vector<int> t = lut;
- for (int i = SIZE(a)-1; i >= 0; i--)
+ for (int i = GetSize(a)-1; i >= 0; i--)
{
- std::vector<int> t0(t.begin(), t.begin() + SIZE(t)/2);
- std::vector<int> t1(t.begin() + SIZE(t)/2, t.end());
+ std::vector<int> t0(t.begin(), t.begin() + GetSize(t)/2);
+ std::vector<int> t1(t.begin() + GetSize(t)/2, t.end());
t = ez->vec_ite(a[i], t1, t0);
}
- log_assert(SIZE(t) == 1);
+ log_assert(GetSize(t) == 1);
ez->assume(ez->vec_eq(y, t));
}
return true;
std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co;
- for (int i = 0; i < SIZE(co); i++)
+ for (int i = 0; i < GetSize(co); i++)
ez->SET(yy[i], ez->OR(g[i], ez->AND(p[i], i ? yy[i-1] : ci[0])));
if (model_undef)
std::vector<int> def_x = model_undef ? ez->vec_var(x.size()) : x;
std::vector<int> def_co = model_undef ? ez->vec_var(co.size()) : co;
- log_assert(SIZE(y) == SIZE(x));
- log_assert(SIZE(y) == SIZE(co));
- log_assert(SIZE(ci) == 1);
- log_assert(SIZE(bi) == 1);
+ log_assert(GetSize(y) == GetSize(x));
+ log_assert(GetSize(y) == GetSize(co));
+ log_assert(GetSize(ci) == 1);
+ log_assert(GetSize(bi) == 1);
- for (int i = 0; i < SIZE(y); i++)
+ for (int i = 0; i < GetSize(y); i++)
{
int s1 = a.at(i), s2 = ez->XOR(b.at(i), bi.at(0)), s3 = i ? co.at(i-1) : ci.at(0);
ez->SET(def_x.at(i), ez->XOR(s1, s2));
all_inputs_undef.insert(all_inputs_undef.end(), undef_bi.begin(), undef_bi.end());
int undef_any = ez->expression(ezSAT::OpOr, all_inputs_undef);
- for (int i = 0; i < SIZE(undef_y); i++) {
+ for (int i = 0; i < GetSize(undef_y); i++) {
ez->SET(undef_y.at(i), undef_any);
ez->SET(undef_x.at(i), ez->OR(undef_a.at(i), undef_b.at(i), undef_bi.at(0)));
ez->SET(undef_co.at(i), undef_any);
void expand(RTLIL::SigSpec from, RTLIL::SigSpec to)
{
- log_assert(SIZE(from) == SIZE(to));
- for (int i = 0; i < SIZE(from); i++) {
+ log_assert(GetSize(from) == GetSize(to));
+ for (int i = 0; i < GetSize(from); i++) {
bitDef_t bit_from(from[i]), bit_to(to[i]);
if (bit_from.first != NULL && bit_to.first != NULL && bits.count(bit_from) > 0)
bits.insert(bit_to);
void add(RTLIL::SigSpec from, RTLIL::SigSpec to)
{
- log_assert(SIZE(from) == SIZE(to));
+ log_assert(GetSize(from) == GetSize(to));
- for (int i = 0; i < SIZE(from); i++)
+ for (int i = 0; i < GetSize(from); i++)
{
RTLIL::SigBit &bf = from[i];
RTLIL::SigBit &bt = to[i];
void reset(const Key &k)
{
- for (int i = SIZE(backup_state)-1; i >= 0; i--)
+ for (int i = GetSize(backup_state)-1; i >= 0; i--)
if (backup_state[i].count(k) != 0) {
if (backup_state[i].at(k) == nullptr)
current_state.erase(k);
found_loops = true;
if (analyze_loops) {
std::set<T> loop;
- for (int i = SIZE(active_stack)-1; i >= 0; i--) {
+ for (int i = GetSize(active_stack)-1; i >= 0; i--) {
loop.insert(active_stack[i]);
if (active_stack[i] == n)
break;
for (auto &it : database)
sort_worker(it.first, marked_cells, active_cells, active_stack);
- log_assert(SIZE(sorted) == SIZE(database));
+ log_assert(GetSize(sorted) == GetSize(database));
return !found_loops;
}
};
return string;
}
-int SIZE(RTLIL::Wire *wire)
+int GetSize(RTLIL::Wire *wire)
{
return wire->width;
}
int pos = 0;
std::string label;
- while (pos < SIZE(command) && (command[pos] == ' ' || command[pos] == '\t'))
+ while (pos < GetSize(command) && (command[pos] == ' ' || command[pos] == '\t'))
pos++;
- while (pos < SIZE(command) && command[pos] != ' ' && command[pos] != '\t' && command[pos] != '\r' && command[pos] != '\n')
+ while (pos < GetSize(command) && command[pos] != ' ' && command[pos] != '\t' && command[pos] != '\r' && command[pos] != '\n')
label += command[pos++];
- if (label.back() == ':' && SIZE(label) > 1)
+ if (label.back() == ':' && GetSize(label) > 1)
{
- label = label.substr(0, SIZE(label)-1);
+ label = label.substr(0, GetSize(label)-1);
command = command.substr(pos);
if (label == run_from)
std::string stringf(const char *fmt, ...);
std::string vstringf(const char *fmt, va_list ap);
-template<typename T> int SIZE(const T &obj) { return obj.size(); }
-int SIZE(RTLIL::Wire *wire);
+template<typename T> int GetSize(const T &obj) { return obj.size(); }
+int GetSize(RTLIL::Wire *wire);
YOSYS_NAMESPACE_END
// for each bit (unless it is a constant):
// check if it is used at least two times and add to stub_bits otherwise
- for (int i = 0; i < SIZE(sig); i++)
+ for (int i = 0; i < GetSize(sig); i++)
if (sig[i].wire != NULL && (bit_usage_count[sig[i]] + usage_offset) < 2)
stub_bits.insert(i);
// report stub bits and/or stub wires, don't report single bits
// if called with report_bits set to false.
- if (SIZE(stub_bits) == SIZE(sig)) {
+ if (GetSize(stub_bits) == GetSize(sig)) {
log(" found stub wire: %s\n", RTLIL::id2cstr(wire->name));
} else {
if (!report_bits)
log("Modules in current design:\n");
for (auto mod : design->modules())
log(" %s (%zd wires, %zd cells)\n", log_id(mod),
- SIZE(mod->wires()), SIZE(mod->cells()));
+ GetSize(mod->wires()), GetSize(mod->cells()));
}
} MyPass;
log("\n");
int max_alias_len = 1;
for (auto &it : loaded_plugin_aliases)
- max_alias_len = std::max(max_alias_len, SIZE(it.first));
+ max_alias_len = std::max(max_alias_len, GetSize(it.first));
for (auto &it : loaded_plugin_aliases)
log("Alias: %-*s %s\n", max_alias_len, it.first.c_str(), it.second.c_str());
}
std::string gen_signode_simple(RTLIL::SigSpec sig, bool range_check = true)
{
- if (SIZE(sig) == 0) {
+ if (GetSize(sig) == 0) {
fprintf(f, "v%d [ label=\"\" ];\n", single_idx_count);
return stringf("v%d", single_idx_count++);
}
"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
"$add", "$sub", "$mul", "$div", "$mod", "$pow")) {
- int width_a = it.second->hasPort("\\A") ? SIZE(it.second->getPort("\\A")) : 0;
- int width_b = it.second->hasPort("\\B") ? SIZE(it.second->getPort("\\B")) : 0;
- int width_y = it.second->hasPort("\\Y") ? SIZE(it.second->getPort("\\Y")) : 0;
+ int width_a = it.second->hasPort("\\A") ? GetSize(it.second->getPort("\\A")) : 0;
+ int width_b = it.second->hasPort("\\B") ? GetSize(it.second->getPort("\\B")) : 0;
+ int width_y = it.second->hasPort("\\Y") ? GetSize(it.second->getPort("\\Y")) : 0;
cell_type = stringf("%s_%d", cell_type.c_str(), std::max<int>({width_a, width_b, width_y}));
}
else if (cell_type.in("$mux", "$pmux"))
- cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Y")));
+ cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Y")));
else if (cell_type.in("$sr", "$dff", "$dffsr", "$adff", "$dlatch", "$dlatchsr"))
- cell_type = stringf("%s_%d", cell_type.c_str(), SIZE(it.second->getPort("\\Q")));
+ cell_type = stringf("%s_%d", cell_type.c_str(), GetSize(it.second->getPort("\\Q")));
}
num_cells++;
sig_aa.replace(sig_y, sig_a);
RTLIL::SigSpec sig_bb;
- for (int i = 0; i < SIZE(sig_b)/SIZE(sig_a); i++) {
+ for (int i = 0; i < GetSize(sig_b)/GetSize(sig_a); i++) {
RTLIL::SigSpec s = sig;
- s.replace(sig_y, sig_b.extract(i*SIZE(sig_a), SIZE(sig_a)));
+ s.replace(sig_y, sig_b.extract(i*GetSize(sig_a), GetSize(sig_a)));
sig_bb.append(s);
}
if (!find_states(sig_aa, dff_out, ctrl, states))
return false;
- for (int i = 0; i < SIZE(sig_bb)/SIZE(sig_aa); i++) {
- if (!find_states(sig_bb.extract(i*SIZE(sig_aa), SIZE(sig_aa)), dff_out, ctrl, states))
+ for (int i = 0; i < GetSize(sig_bb)/GetSize(sig_aa); i++) {
+ if (!find_states(sig_bb.extract(i*GetSize(sig_aa), GetSize(sig_aa)), dff_out, ctrl, states))
return false;
}
}
static RTLIL::Const sig2const(ConstEval &ce, RTLIL::SigSpec sig, RTLIL::State noconst_state, RTLIL::SigSpec dont_care = RTLIL::SigSpec())
{
if (dont_care.size() > 0) {
- for (int i = 0; i < SIZE(sig); i++)
+ for (int i = 0; i < GetSize(sig); i++)
if (dont_care.extract(sig[i]).size() > 0)
sig[i] = noconst_state;
}
ce.assign_map.apply(sig);
ce.values_map.apply(sig);
- for (int i = 0; i < SIZE(sig); i++)
+ for (int i = 0; i < GetSize(sig); i++)
if (sig[i].wire != NULL)
sig[i] = noconst_state;
tr.ctrl_out = sig2const(ce, ctrl_out, RTLIL::State::Sx);
std::map<RTLIL::SigBit, int> ctrl_in_bit_indices;
- for (int i = 0; i < SIZE(ctrl_in); i++)
+ for (int i = 0; i < GetSize(ctrl_in); i++)
ctrl_in_bit_indices[ctrl_in[i]] = i;
for (auto &it : ctrl_in_bit_indices)
log(" fsm extraction failed: state selection tree is not closed.\n");
return;
}
- if (SIZE(states) <= 1) {
+ if (GetSize(states) <= 1) {
log(" fsm extraction failed: at least two states are required.\n");
return;
}
static bool pattern_is_subset(const RTLIL::Const &super_pattern, const RTLIL::Const &sub_pattern)
{
- log_assert(SIZE(super_pattern.bits) == SIZE(sub_pattern.bits));
- for (int i = 0; i < SIZE(super_pattern.bits); i++)
+ log_assert(GetSize(super_pattern.bits) == GetSize(sub_pattern.bits));
+ for (int i = 0; i < GetSize(super_pattern.bits); i++)
if (sub_pattern.bits[i] == RTLIL::State::S0 || sub_pattern.bits[i] == RTLIL::State::S1) {
if (super_pattern.bits[i] == RTLIL::State::S0 || super_pattern.bits[i] == RTLIL::State::S1) {
if (super_pattern.bits[i] != sub_pattern.bits[i])
if (pattern_is_subset(pattern, it2.first))
complete_in_state_cache.insert(it2.second.begin(), it2.second.end());
- if (SIZE(complete_in_state_cache) < num_states)
+ if (GetSize(complete_in_state_cache) < num_states)
{
if (or_sig.size() == 1)
{
// generate next_state signal
- if (SIZE(fsm_data.state_table) == 1)
+ if (GetSize(fsm_data.state_table) == 1)
{
module->connect(next_state_wire, fsm_data.state_table.front());
}
std::vector<RTLIL::Const> new_state_table;
std::map<int, int> old_to_new_state;
- for (int i = 0; i < SIZE(fsm_data.state_table); i++)
+ for (int i = 0; i < GetSize(fsm_data.state_table); i++)
if (i != fsm_data.reset_state)
unreachable_states.insert(i);
if (unreachable_states.empty())
break;
- for (int i = 0; i < SIZE(fsm_data.state_table); i++) {
+ for (int i = 0; i < GetSize(fsm_data.state_table); i++) {
if (unreachable_states.count(i)) {
log(" Removing unreachable state %s.\n", log_signal(fsm_data.state_table[i]));
continue;
}
- old_to_new_state[i] = SIZE(new_state_table);
+ old_to_new_state[i] = GetSize(new_state_table);
new_state_table.push_back(fsm_data.state_table[i]);
}
if (!default_encoding.empty())
encoding = default_encoding;
else
- encoding = SIZE(fsm_data.state_table) < 32 ? "one-hot" : "binary";
+ encoding = GetSize(fsm_data.state_table) < 32 ? "one-hot" : "binary";
log(" mapping auto encoding to `%s` for this FSM.\n", encoding.c_str());
}
log("\n");
log(" Input signals:\n");
RTLIL::SigSpec sig_in = cell->getPort("\\CTRL_IN");
- for (int i = 0; i < SIZE(sig_in); i++)
+ for (int i = 0; i < GetSize(sig_in); i++)
log(" %3d: %s\n", i, log_signal(sig_in[i]));
log("\n");
log(" Output signals:\n");
RTLIL::SigSpec sig_out = cell->getPort("\\CTRL_OUT");
- for (int i = 0; i < SIZE(sig_out); i++)
+ for (int i = 0; i < GetSize(sig_out); i++)
log(" %3d: %s\n", i, log_signal(sig_out[i]));
log("\n");
log(" State encoding:\n");
- for (int i = 0; i < SIZE(state_table); i++)
+ for (int i = 0; i < GetSize(state_table); i++)
log(" %3d: %10s%s\n", i, log_signal(state_table[i], false),
int(i) == reset_state ? " <RESET STATE>" : "");
log("\n");
log(" Transition Table (state_in, ctrl_in, state_out, ctrl_out):\n");
- for (int i = 0; i < SIZE(transition_table); i++) {
+ for (int i = 0; i < GetSize(transition_table); i++) {
transition_t &tr = transition_table[i];
log(" %5d: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));
}
RTLIL::Wire *addr_decode(RTLIL::SigSpec addr_sig, RTLIL::SigSpec addr_val)
{
std::pair<RTLIL::SigSpec, RTLIL::SigSpec> key(addr_sig, addr_val);
- log_assert(SIZE(addr_sig) == SIZE(addr_val));
+ log_assert(GetSize(addr_sig) == GetSize(addr_val));
if (decoder_cache.count(key) == 0) {
- if (SIZE(addr_sig) < 2) {
+ if (GetSize(addr_sig) < 2) {
decoder_cache[key] = module->Eq(NEW_ID, addr_sig, addr_val);
} else {
- int split_at = SIZE(addr_sig) / 2;
+ int split_at = GetSize(addr_sig) / 2;
RTLIL::SigBit left_eq = addr_decode(addr_sig.extract(0, split_at), addr_val.extract(0, split_at));
- RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, SIZE(addr_sig) - split_at), addr_val.extract(split_at, SIZE(addr_val) - split_at));
+ RTLIL::SigBit right_eq = addr_decode(addr_sig.extract(split_at, GetSize(addr_sig) - split_at), addr_val.extract(split_at, GetSize(addr_val) - split_at));
decoder_cache[key] = module->And(NEW_ID, left_eq, right_eq);
}
}
RTLIL::SigBit bit = decoder_cache.at(key);
- log_assert(bit.wire != nullptr && SIZE(bit.wire) == 1);
+ log_assert(bit.wire != nullptr && GetSize(bit.wire) == 1);
return bit.wire;
}
if (!used_signals.check_any(s2) && wire->port_id == 0 && !wire->get_bool_attribute("\\keep")) {
maybe_del_wires.push_back(wire);
} else {
- log_assert(SIZE(s1) == SIZE(s2));
+ log_assert(GetSize(s1) == GetSize(s2));
RTLIL::SigSig new_conn;
- for (int i = 0; i < SIZE(s1); i++)
+ for (int i = 0; i < GetSize(s1); i++)
if (s1[i] != s2[i]) {
new_conn.first.append_bit(s1[i]);
new_conn.second.append_bit(s2[i]);
RTLIL::SigSpec sig = assign_map(RTLIL::SigSpec(wire));
if (!used_signals_nodrivers.check_any(sig)) {
std::string unused_bits;
- for (int i = 0; i < SIZE(sig); i++) {
+ for (int i = 0; i < GetSize(sig); i++) {
if (sig[i].wire == NULL)
continue;
if (!used_signals_nodrivers.check(sig[i])) {
bool is_signed = cell->type == "$pos" && cell->getParam("\\A_SIGNED").as_bool();
RTLIL::SigSpec a = cell->getPort("\\A");
RTLIL::SigSpec y = cell->getPort("\\Y");
- a.extend_u0(SIZE(y), is_signed);
+ a.extend_u0(GetSize(y), is_signed);
module->connect(y, a);
delcells.push_back(cell);
}
enum { GRP_DYN, GRP_CONST_A, GRP_CONST_B, GRP_CONST_AB, GRP_N };
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, std::set<RTLIL::SigBit>> grouped_bits[GRP_N];
- for (int i = 0; i < SIZE(bits_y); i++)
+ for (int i = 0; i < GetSize(bits_y); i++)
{
int group_idx = GRP_DYN;
RTLIL::SigBit bit_a = bits_a[i], bit_b = bits_b[i];
}
for (int i = 0; i < GRP_N; i++)
- if (SIZE(grouped_bits[i]) == SIZE(bits_y))
+ if (GetSize(grouped_bits[i]) == GetSize(bits_y))
return false;
log("Replacing %s cell `%s' in module `%s' with cells using grouped bits:\n",
if (grouped_bits[i].empty())
continue;
- RTLIL::Wire *new_y = module->addWire(NEW_ID, SIZE(grouped_bits[i]));
+ RTLIL::Wire *new_y = module->addWire(NEW_ID, GetSize(grouped_bits[i]));
RTLIL::SigSpec new_a, new_b;
RTLIL::SigSig new_conn;
RTLIL::SigSpec new_a, new_b;
- log_assert(SIZE(a) == SIZE(b));
- for (int i = 0; i < SIZE(a); i++) {
+ log_assert(GetSize(a) == GetSize(b));
+ for (int i = 0; i < GetSize(a); i++) {
if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ? RTLIL::State::S0 : RTLIL::State::S1);
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec sig_y(cell->type == "$shiftx" ? RTLIL::State::Sx : RTLIL::State::S0, cell->getParam("\\Y_WIDTH").as_int());
- if (SIZE(sig_a) < SIZE(sig_y))
- sig_a.extend(SIZE(sig_y), cell->getParam("\\A_SIGNED").as_bool());
+ if (GetSize(sig_a) < GetSize(sig_y))
+ sig_a.extend(GetSize(sig_y), cell->getParam("\\A_SIGNED").as_bool());
- for (int i = 0; i < SIZE(sig_y); i++) {
+ for (int i = 0; i < GetSize(sig_y); i++) {
int idx = i + shift_bits;
- if (0 <= idx && idx < SIZE(sig_a))
+ if (0 <= idx && idx < GetSize(sig_a))
sig_y[i] = sig_a[idx];
- else if (SIZE(sig_a) <= idx && sign_ext)
- sig_y[i] = sig_a[SIZE(sig_a)-1];
+ else if (GetSize(sig_a) <= idx && sign_ext)
+ sig_y[i] = sig_a[GetSize(sig_a)-1];
}
cover_list("opt.opt_const.constshift", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", cell->type.str());
if (cell->getPort("\\S").size() != new_s.size()) {
cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type.str());
log("Optimized away %d select inputs of %s cell `%s' in module `%s'.\n",
- SIZE(cell->getPort("\\S")) - SIZE(new_s), log_id(cell->type), log_id(cell), log_id(module));
+ GetSize(cell->getPort("\\S")) - GetSize(new_s), log_id(cell->type), log_id(cell), log_id(module));
cell->setPort("\\A", new_a);
cell->setPort("\\B", new_b);
cell->setPort("\\S", new_s);
std::vector<RTLIL::SigBit> new_b = RTLIL::SigSpec(i, 6);
- while (SIZE(new_b) > 1 && new_b.back() == RTLIL::State::S0)
+ while (GetSize(new_b) > 1 && new_b.back() == RTLIL::State::S0)
new_b.pop_back();
cell->type = "$shl";
- cell->parameters["\\B_WIDTH"] = SIZE(new_b);
+ cell->parameters["\\B_WIDTH"] = GetSize(new_b);
cell->parameters["\\B_SIGNED"] = false;
cell->setPort("\\B", new_b);
cell->check();
static int bits_macc_port(const Macc::port_t &p, int width)
{
- if (SIZE(p.in_a) == 0 || SIZE(p.in_b) == 0)
- return std::min(std::max(SIZE(p.in_a), SIZE(p.in_b)), width);
- return std::min(SIZE(p.in_a), width) * std::min(SIZE(p.in_b), width) / 2;
+ if (GetSize(p.in_a) == 0 || GetSize(p.in_b) == 0)
+ return std::min(std::max(GetSize(p.in_a), GetSize(p.in_b)), width);
+ return std::min(GetSize(p.in_a), width) * std::min(GetSize(p.in_b), width) / 2;
}
static int bits_macc(const Macc &m, int width)
{
- int bits = SIZE(m.bit_ports);
+ int bits = GetSize(m.bit_ports);
for (auto &p : m.ports)
bits += bits_macc_port(p, width);
return bits;
static int bits_macc(RTLIL::Cell *c)
{
Macc m(c);
- int width = SIZE(c->getPort("\\Y"));
+ int width = GetSize(c->getPort("\\Y"));
return bits_macc(m, width);
}
static bool cmp_macc_ports(const Macc::port_t &p1, const Macc::port_t &p2)
{
- bool mul1 = SIZE(p1.in_a) && SIZE(p1.in_b);
- bool mul2 = SIZE(p2.in_a) && SIZE(p2.in_b);
+ bool mul1 = GetSize(p1.in_a) && GetSize(p1.in_b);
+ bool mul2 = GetSize(p2.in_a) && GetSize(p2.in_b);
- int w1 = mul1 ? SIZE(p1.in_a) * SIZE(p1.in_b) : SIZE(p1.in_a) + SIZE(p1.in_b);
- int w2 = mul2 ? SIZE(p2.in_a) * SIZE(p2.in_b) : SIZE(p2.in_a) + SIZE(p2.in_b);
+ int w1 = mul1 ? GetSize(p1.in_a) * GetSize(p1.in_b) : GetSize(p1.in_a) + GetSize(p1.in_b);
+ int w2 = mul2 ? GetSize(p2.in_a) * GetSize(p2.in_b) : GetSize(p2.in_a) + GetSize(p2.in_b);
if (mul1 != mul2)
return mul1;
if (p1.do_subtract != p2.do_subtract)
return -1;
- bool mul1 = SIZE(p1.in_a) && SIZE(p1.in_b);
- bool mul2 = SIZE(p2.in_a) && SIZE(p2.in_b);
+ bool mul1 = GetSize(p1.in_a) && GetSize(p1.in_b);
+ bool mul2 = GetSize(p2.in_a) && GetSize(p2.in_b);
if (mul1 != mul2)
return -1;
bool force_signed = false, force_not_signed = false;
- if ((SIZE(p1.in_a) && SIZE(p1.in_a) < w1) || (SIZE(p1.in_b) && SIZE(p1.in_b) < w1)) {
+ if ((GetSize(p1.in_a) && GetSize(p1.in_a) < w1) || (GetSize(p1.in_b) && GetSize(p1.in_b) < w1)) {
if (p1.is_signed)
force_signed = true;
else
force_not_signed = true;
}
- if ((SIZE(p2.in_a) && SIZE(p2.in_a) < w2) || (SIZE(p2.in_b) && SIZE(p2.in_b) < w2)) {
+ if ((GetSize(p2.in_a) && GetSize(p2.in_a) < w2) || (GetSize(p2.in_b) && GetSize(p2.in_b) < w2)) {
if (p2.is_signed)
force_signed = true;
else
RTLIL::SigSpec sig_a1 = p1.in_a, sig_b1 = p1.in_b;
RTLIL::SigSpec sig_a2 = p2.in_a, sig_b2 = p2.in_b;
- RTLIL::SigSpec sig_a = SIZE(sig_a1) > SIZE(sig_a2) ? sig_a1 : sig_a2;
- RTLIL::SigSpec sig_b = SIZE(sig_b1) > SIZE(sig_b2) ? sig_b1 : sig_b2;
+ RTLIL::SigSpec sig_a = GetSize(sig_a1) > GetSize(sig_a2) ? sig_a1 : sig_a2;
+ RTLIL::SigSpec sig_b = GetSize(sig_b1) > GetSize(sig_b2) ? sig_b1 : sig_b2;
- sig_a1.extend_u0(SIZE(sig_a), p1.is_signed);
- sig_b1.extend_u0(SIZE(sig_b), p1.is_signed);
+ sig_a1.extend_u0(GetSize(sig_a), p1.is_signed);
+ sig_b1.extend_u0(GetSize(sig_b), p1.is_signed);
- sig_a2.extend_u0(SIZE(sig_a), p2.is_signed);
- sig_b2.extend_u0(SIZE(sig_b), p2.is_signed);
+ sig_a2.extend_u0(GetSize(sig_a), p2.is_signed);
+ sig_b2.extend_u0(GetSize(sig_b), p2.is_signed);
- if (supercell_aux && SIZE(sig_a)) {
- sig_a = module->addWire(NEW_ID, SIZE(sig_a));
+ if (supercell_aux && GetSize(sig_a)) {
+ sig_a = module->addWire(NEW_ID, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, sig_a2, sig_a1, act, sig_a));
}
- if (supercell_aux && SIZE(sig_b)) {
- sig_b = module->addWire(NEW_ID, SIZE(sig_b));
+ if (supercell_aux && GetSize(sig_b)) {
+ sig_b = module->addWire(NEW_ID, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b));
}
supermacc->ports.push_back(p);
}
- int score = 1000 + abs(SIZE(p1.in_a) - SIZE(p2.in_a)) * std::max(abs(SIZE(p1.in_b) - SIZE(p2.in_b)), 1);
+ int score = 1000 + abs(GetSize(p1.in_a) - GetSize(p2.in_a)) * std::max(abs(GetSize(p1.in_b) - GetSize(p2.in_b)), 1);
- for (int i = 0; i < std::min(SIZE(p1.in_a), SIZE(p2.in_a)); i++)
+ for (int i = 0; i < std::min(GetSize(p1.in_a), GetSize(p2.in_a)); i++)
if (p1.in_a[i] == p2.in_a[i] && score > 0)
score--;
- for (int i = 0; i < std::min(SIZE(p1.in_b), SIZE(p2.in_b)); i++)
+ for (int i = 0; i < std::min(GetSize(p1.in_b), GetSize(p2.in_b)); i++)
if (p1.in_b[i] == p2.in_b[i] && score > 0)
score--;
{
Macc m1(c1), m2(c2), supermacc;
- int w1 = SIZE(c1->getPort("\\Y")), w2 = SIZE(c2->getPort("\\Y"));
+ int w1 = GetSize(c1->getPort("\\Y")), w2 = GetSize(c2->getPort("\\Y"));
int width = std::max(w1, w2);
m1.optimize(w1);
std::set<int> m1_unmapped, m2_unmapped;
- for (int i = 0; i < SIZE(m1.ports); i++)
+ for (int i = 0; i < GetSize(m1.ports); i++)
m1_unmapped.insert(i);
- for (int i = 0; i < SIZE(m2.ports); i++)
+ for (int i = 0; i < GetSize(m2.ports); i++)
m2_unmapped.insert(i);
while (1)
RTLIL::SigSpec sig_a = m1.ports[i].in_a;
RTLIL::SigSpec sig_b = m1.ports[i].in_b;
- if (supercell_aux && SIZE(sig_a)) {
- sig_a = module->addWire(NEW_ID, SIZE(sig_a));
- supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, SIZE(sig_a)), m1.ports[i].in_a, act, sig_a));
+ if (supercell_aux && GetSize(sig_a)) {
+ sig_a = module->addWire(NEW_ID, GetSize(sig_a));
+ supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.ports[i].in_a, act, sig_a));
}
- if (supercell_aux && SIZE(sig_b)) {
- sig_b = module->addWire(NEW_ID, SIZE(sig_b));
- supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, SIZE(sig_b)), m1.ports[i].in_b, act, sig_b));
+ if (supercell_aux && GetSize(sig_b)) {
+ sig_b = module->addWire(NEW_ID, GetSize(sig_b));
+ supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.ports[i].in_b, act, sig_b));
}
Macc::port_t p;
RTLIL::SigSpec sig_a = m2.ports[i].in_a;
RTLIL::SigSpec sig_b = m2.ports[i].in_b;
- if (supercell_aux && SIZE(sig_a)) {
- sig_a = module->addWire(NEW_ID, SIZE(sig_a));
- supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_a, RTLIL::SigSpec(0, SIZE(sig_a)), act, sig_a));
+ if (supercell_aux && GetSize(sig_a)) {
+ sig_a = module->addWire(NEW_ID, GetSize(sig_a));
+ supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a));
}
- if (supercell_aux && SIZE(sig_b)) {
- sig_b = module->addWire(NEW_ID, SIZE(sig_b));
- supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_b, RTLIL::SigSpec(0, SIZE(sig_b)), act, sig_b));
+ if (supercell_aux && GetSize(sig_b)) {
+ sig_b = module->addWire(NEW_ID, GetSize(sig_b));
+ supercell_aux->insert(module->addMux(NEW_ID, m2.ports[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b));
}
Macc::port_t p;
std::map<RTLIL::SigBit, RTLIL::State> p_bits;
std::vector<RTLIL::SigBit> p_first_bits = p.first;
- for (int i = 0; i < SIZE(p_first_bits); i++) {
+ for (int i = 0; i < GetSize(p_first_bits); i++) {
RTLIL::SigBit b = p_first_bits[i];
RTLIL::State v = p.second.bits[i];
if (p_bits.count(b) && p_bits.at(b) != v)
if (cell_out_bits.count(bit))
used_in_a = true;
- for (int i = 0; i < SIZE(sig_b); i++)
+ for (int i = 0; i < GetSize(sig_b); i++)
if (cell_out_bits.count(sig_b[i]))
used_in_b_parts.insert(i / width);
if (used_in_a)
for (auto p : c_patterns) {
- for (int i = 0; i < SIZE(sig_s); i++)
+ for (int i = 0; i < GetSize(sig_s); i++)
p.first.append_bit(sig_s[i]), p.second.bits.push_back(RTLIL::State::S0);
if (sort_check_activation_pattern(p))
activation_patterns_cache[cell].insert(p);
std::vector<RTLIL::SigBit> p_first = p.first;
std::pair<RTLIL::SigSpec, RTLIL::Const> new_p;
- for (int i = 0; i < SIZE(p_first); i++)
+ for (int i = 0; i < GetSize(p_first); i++)
if (filter_bits.count(p_first[i]) == 0) {
new_p.first.append_bit(p_first[i]);
new_p.second.bits.push_back(p.second.bits.at(i));
return;
log("Found %d cells in module %s that may be considered for resource sharing.\n",
- SIZE(shareable_cells), log_id(module));
+ GetSize(shareable_cells), log_id(module));
for (auto cell : module->cells())
if (cell->type == "$pmux")
continue;
}
- log(" Found %d activation_patterns using ctrl signal %s.\n", SIZE(cell_activation_patterns), log_signal(cell_activation_signals));
+ log(" Found %d activation_patterns using ctrl signal %s.\n", GetSize(cell_activation_patterns), log_signal(cell_activation_signals));
std::vector<RTLIL::Cell*> candidates;
find_shareable_partners(candidates, cell);
continue;
}
- log(" Found %d candidates:", SIZE(candidates));
+ log(" Found %d candidates:", GetSize(candidates));
for (auto c : candidates)
log(" %s", log_id(c));
log("\n");
}
log(" Found %d activation_patterns using ctrl signal %s.\n",
- SIZE(other_cell_activation_patterns), log_signal(other_cell_activation_signals));
+ GetSize(other_cell_activation_patterns), log_signal(other_cell_activation_signals));
const std::set<RTLIL::SigBit> &cell_forbidden_controls = find_forbidden_controls(cell);
const std::set<RTLIL::SigBit> &other_cell_forbidden_controls = find_forbidden_controls(other_cell);
ez.assume(ez.AND(ez.expression(ez.OpOr, cell_active), ez.expression(ez.OpOr, other_cell_active)));
log(" Size of SAT problem: %d cells, %d variables, %d clauses\n",
- SIZE(sat_cells), ez.numCnfVariables(), ez.numCnfClauses());
+ GetSize(sat_cells), ez.numCnfVariables(), ez.numCnfClauses());
if (ez.solve(sat_model, sat_model_values)) {
log(" According to the SAT solver this pair of cells can not be shared.\n");
- log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), SIZE(sat_model_values));
- for (int i = SIZE(sat_model_values)-1; i >= 0; i--)
+ log(" Model from SAT solver: %s = %d'", log_signal(all_ctrl_signals), GetSize(sat_model_values));
+ for (int i = GetSize(sat_model_values)-1; i >= 0; i--)
log("%c", sat_model_values[i] ? '1' : '0');
log("\n");
continue;
}
if (!cells_to_remove.empty()) {
- log("Removing %d cells in module %s:\n", SIZE(cells_to_remove), log_id(module));
+ log("Removing %d cells in module %s:\n", GetSize(cells_to_remove), log_id(module));
for (auto c : cells_to_remove) {
log(" Removing cell %s (%s).\n", log_id(c), log_id(c->type));
module->remove(c);
SigSpec sig_y = mi.sigmap(cell->getPort("\\Y"));
std::vector<SigBit> bits_removed;
- for (int i = SIZE(sig_y)-1; i >= 0; i--)
+ for (int i = GetSize(sig_y)-1; i >= 0; i--)
{
auto info = mi.query(sig_y[i]);
- if (!info->is_output && SIZE(info->ports) <= 1) {
+ if (!info->is_output && GetSize(info->ports) <= 1) {
bits_removed.push_back(Sx);
continue;
}
SigBit ref = sig_a[i];
- for (int k = 0; k < SIZE(sig_s); k++) {
- if (ref != Sx && sig_b[k*SIZE(sig_a) + i] != Sx && ref != sig_b[k*SIZE(sig_a) + i])
+ for (int k = 0; k < GetSize(sig_s); k++) {
+ if (ref != Sx && sig_b[k*GetSize(sig_a) + i] != Sx && ref != sig_b[k*GetSize(sig_a) + i])
goto no_match_ab;
- if (sig_b[k*SIZE(sig_a) + i] != Sx)
- ref = sig_b[k*SIZE(sig_a) + i];
+ if (sig_b[k*GetSize(sig_a) + i] != Sx)
+ ref = sig_b[k*GetSize(sig_a) + i];
}
if (0)
no_match_ab:
return;
SigSpec sig_removed;
- for (int i = SIZE(bits_removed)-1; i >= 0; i--)
+ for (int i = GetSize(bits_removed)-1; i >= 0; i--)
sig_removed.append_bit(bits_removed[i]);
- if (SIZE(bits_removed) == SIZE(sig_y)) {
+ if (GetSize(bits_removed) == GetSize(sig_y)) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
module->connect(sig_y, sig_removed);
module->remove(cell);
}
log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n",
- SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type));
+ GetSize(sig_removed), GetSize(sig_y), log_id(module), log_id(cell), log_id(cell->type));
- int n_removed = SIZE(sig_removed);
- int n_kept = SIZE(sig_y) - SIZE(sig_removed);
+ int n_removed = GetSize(sig_removed);
+ int n_kept = GetSize(sig_y) - GetSize(sig_removed);
SigSpec new_work_queue_bits;
new_work_queue_bits.append(sig_a.extract(n_kept, n_removed));
SigSpec new_sig_y = sig_y.extract(0, n_kept);
SigSpec new_sig_b;
- for (int k = 0; k < SIZE(sig_s); k++) {
- new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept));
- new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed));
+ for (int k = 0; k < GetSize(sig_s); k++) {
+ new_sig_b.append(sig_b.extract(k*GetSize(sig_a), n_kept));
+ new_work_queue_bits.append(sig_b.extract(k*GetSize(sig_a) + n_kept, n_removed));
}
for (auto bit : new_work_queue_bits)
port_signed = false;
int bits_removed = 0;
- if (SIZE(sig) > max_port_size) {
- bits_removed = SIZE(sig) - max_port_size;
+ if (GetSize(sig) > max_port_size) {
+ bits_removed = GetSize(sig) - max_port_size;
for (auto bit : sig.extract(max_port_size, bits_removed))
work_queue_bits.insert(bit);
sig = sig.extract(0, max_port_size);
}
if (port_signed) {
- while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == sig[SIZE(sig)-2])
- work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++;
+ while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == sig[GetSize(sig)-2])
+ work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++;
} else {
- while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == S0)
- work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++;
+ while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == S0)
+ work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++;
}
if (bits_removed) {
log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
- bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type));
+ bits_removed, GetSize(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type));
cell->setPort(stringf("\\%c", port), sig);
did_something = true;
}
// Reduce size of ports A and B based on constant input bits and size of output port
- int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1;
- int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1;
+ int max_port_a_size = cell->hasPort("\\A") ? GetSize(cell->getPort("\\A")) : -1;
+ int max_port_b_size = cell->hasPort("\\B") ? GetSize(cell->getPort("\\B")) : -1;
if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
- max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y")));
- max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y")));
+ max_port_a_size = std::min(max_port_a_size, GetSize(cell->getPort("\\Y")));
+ max_port_b_size = std::min(max_port_b_size, GetSize(cell->getPort("\\Y")));
}
bool port_a_signed = false;
if (port_a_signed && cell->type == "$shr") {
// do not reduce size of output on $shr cells with signed A inputs
} else {
- while (SIZE(sig) > 0)
+ while (GetSize(sig) > 0)
{
- auto info = mi.query(sig[SIZE(sig)-1]);
+ auto info = mi.query(sig[GetSize(sig)-1]);
- if (info->is_output || SIZE(info->ports) > 1)
+ if (info->is_output || GetSize(info->ports) > 1)
break;
- sig.remove(SIZE(sig)-1);
+ sig.remove(GetSize(sig)-1);
bits_removed++;
}
}
bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
int a_size = 0, b_size = 0;
- if (cell->hasPort("\\A")) a_size = SIZE(cell->getPort("\\A"));
- if (cell->hasPort("\\B")) b_size = SIZE(cell->getPort("\\B"));
+ if (cell->hasPort("\\A")) a_size = GetSize(cell->getPort("\\A"));
+ if (cell->hasPort("\\B")) b_size = GetSize(cell->getPort("\\B"));
int max_y_size = std::max(a_size, b_size);
if (cell->type == "$mul")
max_y_size = a_size + b_size;
- while (SIZE(sig) > 1 && SIZE(sig) > max_y_size) {
- module->connect(sig[SIZE(sig)-1], is_signed ? sig[SIZE(sig)-2] : S0);
- sig.remove(SIZE(sig)-1);
+ while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) {
+ module->connect(sig[GetSize(sig)-1], is_signed ? sig[GetSize(sig)-2] : S0);
+ sig.remove(GetSize(sig)-1);
bits_removed++;
}
}
- if (SIZE(sig) == 0) {
+ if (GetSize(sig) == 0) {
log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
module->remove(cell);
return;
if (bits_removed) {
log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
- bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
+ bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
cell->setPort("\\Y", sig);
did_something = true;
}
if (w->port_id > 0 || count_nontrivial_wire_attrs(w) > 0)
continue;
- for (int i = SIZE(w)-1; i >= 0; i--) {
+ for (int i = GetSize(w)-1; i >= 0; i--) {
SigBit bit(w, i);
auto info = mi.query(bit);
- if (info && (info->is_input || info->is_output || SIZE(info->ports) > 0))
+ if (info && (info->is_input || info->is_output || GetSize(info->ports) > 0))
break;
unused_top_bits++;
}
- if (0 < unused_top_bits && unused_top_bits < SIZE(w)) {
- log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, SIZE(w), log_id(module), log_id(w));
+ if (0 < unused_top_bits && unused_top_bits < GetSize(w)) {
+ log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
Wire *nw = module->addWire(NEW_ID, w);
- nw->width = SIZE(w) - unused_top_bits;
- module->connect(nw, SigSpec(w).extract(0, SIZE(nw)));
+ nw->width = GetSize(w) - unused_top_bits;
+ module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
}
}
for (auto &action : sync->actions) {
RTLIL::SigSpec rspec = action.second;
RTLIL::SigSpec rval = RTLIL::SigSpec(RTLIL::State::Sm, rspec.size());
- for (int i = 0; i < SIZE(rspec); i++)
+ for (int i = 0; i < GetSize(rspec); i++)
if (rspec[i].wire == NULL)
rval[i] = rspec[i];
RTLIL::SigSpec last_rval;
for (size_t i = 0; i < sw->cases.size(); i++)
{
- bool is_default = SIZE(sw->cases[i]->compare) == 0 && (!pool.empty() || SIZE(sw->signal) == 0);
+ bool is_default = GetSize(sw->cases[i]->compare) == 0 && (!pool.empty() || GetSize(sw->signal) == 0);
for (size_t j = 0; j < sw->cases[i]->compare.size(); j++) {
RTLIL::SigSpec sig = sw->cases[i]->compare[j];
log_signal(undef2), log_signal(mod1_inputs), log_signal(inputs));
if (ignore_x_mod1) {
- for (int i = 0; i < SIZE(sig1); i++)
+ for (int i = 0; i < GetSize(sig1); i++)
if (sig1[i] == RTLIL::State::Sx)
sig2[i] = RTLIL::State::Sx;
}
} else if (rtl_sig.size() > 0) {
if (rtl_sig.size() != sig.size())
log_error("Output (y) has a different width in module %s compared to rtl!\n", RTLIL::id2cstr(module->name));
- for (int i = 0; i < SIZE(sig); i++)
+ for (int i = 0; i < GetSize(sig); i++)
if (rtl_sig[i] == RTLIL::State::Sx)
sig[i] = RTLIL::State::Sx;
}
if (prove_asserts) {
RTLIL::SigSpec asserts_a, asserts_en;
satgen.getAsserts(asserts_a, asserts_en, timestep);
- for (int i = 0; i < SIZE(asserts_a); i++)
+ for (int i = 0; i < GetSize(asserts_a); i++)
log("Import proof for assert: %s when %s.\n", log_signal(asserts_a[i]), log_signal(asserts_en[i]));
prove_bits.push_back(satgen.importAsserts(timestep));
}
RTLIL::SigSpec cached_cf, cached_of, cached_sf;
RTLIL::SigSpec get_lt() {
- if (SIZE(cached_lt) == 0)
+ if (GetSize(cached_lt) == 0)
cached_lt = is_signed ? alu_cell->module->Xor(NEW_ID, get_of(), get_sf()) : get_cf();
return cached_lt;
}
RTLIL::SigSpec get_gt() {
- if (SIZE(cached_gt) == 0)
+ if (GetSize(cached_gt) == 0)
cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()));
return cached_gt;
}
RTLIL::SigSpec get_eq() {
- if (SIZE(cached_eq) == 0)
+ if (GetSize(cached_eq) == 0)
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"));
return cached_eq;
}
RTLIL::SigSpec get_ne() {
- if (SIZE(cached_ne) == 0)
+ if (GetSize(cached_ne) == 0)
cached_ne = alu_cell->module->Not(NEW_ID, get_eq());
return cached_ne;
}
RTLIL::SigSpec get_cf() {
- if (SIZE(cached_cf) == 0) {
+ if (GetSize(cached_cf) == 0) {
cached_cf = alu_cell->getPort("\\CO");
- log_assert(SIZE(cached_cf) >= 1);
- cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[SIZE(cached_cf)-1]);
+ log_assert(GetSize(cached_cf) >= 1);
+ cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1]);
}
return cached_cf;
}
RTLIL::SigSpec get_of() {
- if (SIZE(cached_of) == 0) {
+ if (GetSize(cached_of) == 0) {
cached_of = {alu_cell->getPort("\\CO"), alu_cell->getPort("\\CI")};
- log_assert(SIZE(cached_of) >= 2);
- cached_of = alu_cell->module->Xor(NEW_ID, cached_of[SIZE(cached_of)-1], cached_of[SIZE(cached_of)-2]);
+ log_assert(GetSize(cached_of) >= 2);
+ cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
}
return cached_of;
}
RTLIL::SigSpec get_sf() {
- if (SIZE(cached_sf) == 0) {
+ if (GetSize(cached_sf) == 0) {
cached_sf = alu_cell->getPort("\\Y");
- cached_sf = cached_sf[SIZE(cached_sf)-1];
+ cached_sf = cached_sf[GetSize(cached_sf)-1];
}
return cached_sf;
}
return true;
if (!port.is_signed && port.do_subtract)
return true;
- if (SIZE(port.in_b))
- port_sizes.push_back(SIZE(port.in_a) + SIZE(port.in_b));
+ if (GetSize(port.in_b))
+ port_sizes.push_back(GetSize(port.in_a) + GetSize(port.in_b));
else
- port_sizes.push_back(SIZE(port.in_a));
+ port_sizes.push_back(GetSize(port.in_a));
}
std::sort(port_sizes.begin(), port_sizes.end());
if (delete_nodes.count(n))
continue;
- for (int i = 0; i < SIZE(n->macc.ports); i++)
+ for (int i = 0; i < GetSize(n->macc.ports); i++)
{
auto &port = n->macc.ports[i];
- if (SIZE(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
+ if (GetSize(port.in_b) > 0 || sig_macc.count(port.in_a) == 0)
continue;
auto other_n = sig_macc.at(port.in_a);
if (other_n->users > 1)
continue;
- if (SIZE(other_n->y) != SIZE(n->y) && macc_may_overflow(other_n->macc, SIZE(other_n->y), port.is_signed))
+ if (GetSize(other_n->y) != GetSize(n->y) && macc_may_overflow(other_n->macc, GetSize(other_n->y), port.is_signed))
continue;
log(" merging $macc model for %s into %s.\n", log_id(other_n->cell), log_id(n->cell));
bool do_subtract = port.do_subtract;
- for (int j = 0; j < SIZE(other_n->macc.ports); j++) {
+ for (int j = 0; j < GetSize(other_n->macc.ports); j++) {
if (do_subtract)
other_n->macc.ports[j].do_subtract = !other_n->macc.ports[j].do_subtract;
if (j == 0)
alunode_t *alunode;
for (auto &port : n->macc.ports)
- if (SIZE(port.in_b) > 0) {
+ if (GetSize(port.in_b) > 0) {
goto next_macc;
- } else if (SIZE(port.in_a) == 1 && !port.is_signed && !port.do_subtract) {
+ } else if (GetSize(port.in_a) == 1 && !port.is_signed && !port.do_subtract) {
C.append(port.in_a);
- } else if (SIZE(A) || port.do_subtract) {
- if (SIZE(B))
+ } else if (GetSize(A) || port.do_subtract) {
+ if (GetSize(B))
goto next_macc;
B = port.in_a;
b_signed = port.is_signed;
subtract_b = port.do_subtract;
} else {
- if (SIZE(A))
+ if (GetSize(A))
goto next_macc;
A = port.in_a;
a_signed = port.is_signed;
}
if (!a_signed || !b_signed) {
- if (SIZE(A) == SIZE(n->y))
+ if (GetSize(A) == GetSize(n->y))
a_signed = false;
- if (SIZE(B) == SIZE(n->y))
+ if (GetSize(B) == GetSize(n->y))
b_signed = false;
if (a_signed != b_signed)
goto next_macc;
}
- if (SIZE(A) == 0 && SIZE(C) > 0) {
+ if (GetSize(A) == 0 && GetSize(C) > 0) {
A = C[0];
C.remove(0);
}
- if (SIZE(B) == 0 && SIZE(C) > 0) {
+ if (GetSize(B) == 0 && GetSize(C) > 0) {
B = C[0];
C.remove(0);
}
if (subtract_b)
C.append(RTLIL::S1);
- if (SIZE(C) > 1)
+ if (GetSize(C) > 1)
goto next_macc;
- if (!subtract_b && B < A && SIZE(B))
+ if (!subtract_b && B < A && GetSize(B))
std::swap(A, B);
log(" creating $alu model for $macc %s.\n", log_id(n->cell));
log(" creating $macc cell for %s: %s\n", log_id(n->cell), log_id(cell));
- n->macc.optimize(SIZE(n->y));
+ n->macc.optimize(GetSize(n->y));
n->macc.to_cell(cell);
cell->setPort("\\Y", n->y);
cell->fixup_parameters();
RTLIL::SigSpec B = sigmap(cell->getPort("\\B"));
RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y"));
- if (B < A && SIZE(B)) {
+ if (B < A && GetSize(B)) {
cmp_less = !cmp_less;
std::swap(A, B);
}
n->a = A;
n->b = B;
n->c = RTLIL::S1;
- n->y = module->addWire(NEW_ID, std::max(SIZE(A), SIZE(B)));
+ n->y = module->addWire(NEW_ID, std::max(GetSize(A), GetSize(B)));
n->is_signed = is_signed;
n->invert_b = true;
sig_alu[RTLIL::SigSig(A, B)].insert(n);
RTLIL::SigSpec B = sigmap(cell->getPort("\\B"));
RTLIL::SigSpec Y = sigmap(cell->getPort("\\Y"));
- if (B < A && SIZE(B))
+ if (B < A && GetSize(B))
std::swap(A, B);
alunode_t *n = nullptr;
for (auto &it1 : sig_alu)
for (auto n : it1.second)
{
- if (SIZE(n->b) == 0 && SIZE(n->c) == 0 && SIZE(n->cmp) == 0)
+ if (GetSize(n->b) == 0 && GetSize(n->c) == 0 && GetSize(n->cmp) == 0)
{
n->alu_cell = module->addPos(NEW_ID, n->a, n->y, n->is_signed);
log(" creating $pos cell for ");
- for (int i = 0; i < SIZE(n->cells); i++)
+ for (int i = 0; i < GetSize(n->cells); i++)
log("%s%s", i ? ", ": "", log_id(n->cells[i]));
log(": %s\n", log_id(n->alu_cell));
alu_counter++;
log(" creating $alu cell for ");
- for (int i = 0; i < SIZE(n->cells); i++)
+ for (int i = 0; i < GetSize(n->cells); i++)
log("%s%s", i ? ", ": "", log_id(n->cells[i]));
log(": %s\n", log_id(n->alu_cell));
n->alu_cell->setPort("\\A", n->a);
n->alu_cell->setPort("\\B", n->b);
- n->alu_cell->setPort("\\CI", SIZE(n->c) ? n->c : RTLIL::S0);
+ n->alu_cell->setPort("\\CI", GetSize(n->c) ? n->c : RTLIL::S0);
n->alu_cell->setPort("\\BI", n->invert_b ? RTLIL::S1 : RTLIL::S0);
n->alu_cell->setPort("\\Y", n->y);
- n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y)));
- n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y)));
+ n->alu_cell->setPort("\\X", module->addWire(NEW_ID, GetSize(n->y)));
+ n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
for (auto &it : n->cmp)
if (cmp_eq) sig.append(n->get_eq());
if (cmp_ne) sig.append(n->get_ne());
- if (SIZE(sig) > 1)
+ if (GetSize(sig) > 1)
sig = module->ReduceOr(NEW_ID, sig);
- sig.extend(SIZE(cmp_y));
+ sig.extend(GetSize(cmp_y));
module->connect(cmp_y, sig);
}
} else
if (port.second == 'q') {
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
- sig = module->addWire(NEW_ID, SIZE(old_sig));
+ sig = module->addWire(NEW_ID, GetSize(old_sig));
module->addNotGate(NEW_ID, sig, old_sig);
} else
if ('a' <= port.second && port.second <= 'z') {
void add(RTLIL::SigSpec a, RTLIL::SigSpec b, bool is_signed, bool do_subtract)
{
- if (SIZE(a) < SIZE(b))
+ if (GetSize(a) < GetSize(b))
std::swap(a, b);
a.extend(width, is_signed);
- if (SIZE(b) > width)
+ if (GetSize(b) > width)
b.extend(width, is_signed);
- for (int i = 0; i < SIZE(b); i++)
- if (is_signed && i+1 == SIZE(b))
+ for (int i = 0; i < GetSize(b); i++)
+ if (is_signed && i+1 == GetSize(b))
{
a = {module->Not(NEW_ID, a.extract(i, width-i)), RTLIL::SigSpec(0, i)};
add(module->And(NEW_ID, a, RTLIL::SigSpec(b[i], width)), false, do_subtract);
void fulladd(RTLIL::SigSpec &in1, RTLIL::SigSpec &in2, RTLIL::SigSpec &in3, RTLIL::SigSpec &out1, RTLIL::SigSpec &out2)
{
- int start_index = 0, stop_index = SIZE(in1);
+ int start_index = 0, stop_index = GetSize(in1);
while (start_index < stop_index && in1[start_index] == RTLIL::S0 && in2[start_index] == RTLIL::S0 && in3[start_index] == RTLIL::S0)
start_index++;
if (start_index == stop_index)
{
- out1 = RTLIL::SigSpec(0, SIZE(in1));
- out2 = RTLIL::SigSpec(0, SIZE(in1));
+ out1 = RTLIL::SigSpec(0, GetSize(in1));
+ out2 = RTLIL::SigSpec(0, GetSize(in1));
}
else
{
- RTLIL::SigSpec out_zeros_lsb(0, start_index), out_zeros_msb(0, SIZE(in1)-stop_index);
+ RTLIL::SigSpec out_zeros_lsb(0, start_index), out_zeros_msb(0, GetSize(in1)-stop_index);
in1 = in1.extract(start_index, stop_index-start_index);
in2 = in2.extract(start_index, stop_index-start_index);
in3 = in3.extract(start_index, stop_index-start_index);
- int width = SIZE(in1);
+ int width = GetSize(in1);
RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
while (1)
{
- int free_bit_slots = tree_bit_slots(SIZE(summands)) - SIZE(tree_sum_bits);
+ int free_bit_slots = tree_bit_slots(GetSize(summands)) - GetSize(tree_sum_bits);
int max_depth = 0, max_position = 0;
for (int i = 0; i < width; i++)
- if (max_depth <= SIZE(bits.at(i))) {
- max_depth = SIZE(bits.at(i));
+ if (max_depth <= GetSize(bits.at(i))) {
+ max_depth = GetSize(bits.at(i));
max_position = i;
}
int required_bits = 0;
for (int i = 0; i <= max_position; i++)
- if (SIZE(bits.at(i)) == max_depth)
+ if (GetSize(bits.at(i)) == max_depth)
required_bits += 1 << i;
if (required_bits > free_bit_slots)
break;
for (int i = 0; i <= max_position; i++)
- if (SIZE(bits.at(i)) == max_depth) {
+ if (GetSize(bits.at(i)) == max_depth) {
auto it = bits.at(i).begin();
RTLIL::SigBit bit = *it;
for (int k = 0; k < (1 << i); k++, free_bit_slots--)
}
if (!tree_sum_bits.empty())
- log(" packed %d (%d) bits / %d words into adder tree\n", SIZE(tree_sum_bits), unique_tree_bits, count_tree_words);
+ log(" packed %d (%d) bits / %d words into adder tree\n", GetSize(tree_sum_bits), unique_tree_bits, count_tree_words);
- if (SIZE(summands) == 0) {
+ if (GetSize(summands) == 0) {
log_assert(tree_sum_bits.empty());
return RTLIL::SigSpec(0, width);
}
- if (SIZE(summands) == 1) {
+ if (GetSize(summands) == 1) {
log_assert(tree_sum_bits.empty());
return summands.front();
}
- while (SIZE(summands) > 2)
+ while (GetSize(summands) > 2)
{
std::vector<RTLIL::SigSpec> new_summands;
- for (int i = 0; i < SIZE(summands); i += 3)
- if (i+2 < SIZE(summands)) {
+ for (int i = 0; i < GetSize(summands); i += 3)
+ if (i+2 < GetSize(summands)) {
RTLIL::SigSpec in1 = summands[i];
RTLIL::SigSpec in2 = summands[i+1];
RTLIL::SigSpec in3 = summands[i+2];
void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
{
- int width = SIZE(cell->getPort("\\Y"));
+ int width = GetSize(cell->getPort("\\Y"));
Macc macc;
macc.from_cell(cell);
}
for (auto &port : macc.ports)
- if (SIZE(port.in_b) == 0)
+ if (GetSize(port.in_b) == 0)
log(" %s %s (%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a),
- SIZE(port.in_a), port.is_signed ? "signed" : "unsigned");
+ GetSize(port.in_a), port.is_signed ? "signed" : "unsigned");
else
log(" %s %s * %s (%dx%d bits, %s)\n", port.do_subtract ? "sub" : "add", log_signal(port.in_a), log_signal(port.in_b),
- SIZE(port.in_a), SIZE(port.in_b), port.is_signed ? "signed" : "unsigned");
+ GetSize(port.in_a), GetSize(port.in_b), port.is_signed ? "signed" : "unsigned");
- if (SIZE(macc.bit_ports) != 0)
- log(" add bits %s (%d bits)\n", log_signal(macc.bit_ports), SIZE(macc.bit_ports));
+ if (GetSize(macc.bit_ports) != 0)
+ log(" add bits %s (%d bits)\n", log_signal(macc.bit_ports), GetSize(macc.bit_ports));
if (unmap)
{
for (auto &port : macc.ports) {
summand_t this_summand;
- if (SIZE(port.in_b)) {
+ if (GetSize(port.in_b)) {
this_summand.first = module->addWire(NEW_ID, width);
module->addMul(NEW_ID, port.in_a, port.in_b, this_summand.first, port.is_signed);
- } else if (SIZE(port.in_a) != width) {
+ } else if (GetSize(port.in_a) != width) {
this_summand.first = module->addWire(NEW_ID, width);
module->addPos(NEW_ID, port.in_a, this_summand.first, port.is_signed);
} else {
for (auto &bit : macc.bit_ports)
summands.push_back(summand_t(bit, false));
- if (SIZE(summands) == 0)
+ if (GetSize(summands) == 0)
summands.push_back(summand_t(RTLIL::SigSpec(0, width), false));
- while (SIZE(summands) > 1)
+ while (GetSize(summands) > 1)
{
std::vector<summand_t> new_summands;
- for (int i = 0; i < SIZE(summands); i += 2) {
- if (i+1 < SIZE(summands)) {
+ for (int i = 0; i < GetSize(summands); i += 2) {
+ if (i+1 < GetSize(summands)) {
summand_t this_summand;
this_summand.first = module->addWire(NEW_ID, width);
this_summand.second = summands[i].second && summands[i+1].second;
MaccmapWorker worker(module, width);
for (auto &port : macc.ports)
- if (SIZE(port.in_b) == 0)
+ if (GetSize(port.in_b) == 0)
worker.add(port.in_a, port.is_signed, port.do_subtract);
else
worker.add(port.in_a, port.in_b, port.is_signed, port.do_subtract);
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
- sig_a.extend(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+ sig_a.extend(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
- for (int i = 0; i < SIZE(sig_y); i++) {
+ for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\Y", sig_y[i]);
RTLIL::SigSpec sig_a = cell->getPort("\\A");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
- sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+ sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
module->connect(RTLIL::SigSig(sig_y, sig_a));
}
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
- sig_a.extend_u0(SIZE(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
- sig_b.extend_u0(SIZE(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
+ sig_a.extend_u0(GetSize(sig_y), cell->parameters.at("\\A_SIGNED").as_bool());
+ sig_b.extend_u0(GetSize(sig_y), cell->parameters.at("\\B_SIGNED").as_bool());
if (cell->type == "$xnor")
{
- RTLIL::SigSpec sig_t = module->addWire(NEW_ID, SIZE(sig_y));
+ RTLIL::SigSpec sig_t = module->addWire(NEW_ID, GetSize(sig_y));
- for (int i = 0; i < SIZE(sig_y); i++) {
+ for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_NOT_");
gate->setPort("\\A", sig_t[i]);
gate->setPort("\\Y", sig_y[i]);
if (cell->type == "$xnor") gate_type = "$_XOR_";
log_assert(!gate_type.empty());
- for (int i = 0; i < SIZE(sig_y); i++) {
+ for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\B", sig_b[i]);
RTLIL::SigSpec sig_b = cell->getPort("\\B");
RTLIL::SigSpec sig_y = cell->getPort("\\Y");
- for (int i = 0; i < SIZE(sig_y); i++) {
+ for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, "$_MUX_");
gate->setPort("\\A", sig_a[i]);
gate->setPort("\\B", sig_b[i]);
std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
for (auto conn : cell->connections())
- for (int i = 0; i < SIZE(conn.second); i++) {
+ for (int i = 0; i < GetSize(conn.second); i++) {
RTLIL::SigBit bit = sigmap(conn.second[i]);
if (bit.wire == nullptr) {
if (verbose)
log(" %s",RTLIL::id2cstr(it.first));
if (autoproc_mode) {
Pass::call_on_module(tpl->design, tpl, "proc");
- log_assert(SIZE(tpl->processes) == 0);
+ log_assert(GetSize(tpl->processes) == 0);
} else
log_error("Technology map yielded processes -> this is not supported (use -autoproc to run 'proc' automatically).\n");
}
RTLIL::SigSpec sig = sigmap(conn.second);
sig.remove_const();
- if (SIZE(sig) == 0)
+ if (GetSize(sig) == 0)
continue;
for (auto &tpl_name : celltypeMap.at(cell_type)) {
int port_counter = 1;
for (auto &c : extmapper_cell->connections_) {
- RTLIL::Wire *w = extmapper_module->addWire(c.first, SIZE(c.second));
+ RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second));
if (w->name == "\\Y" || w->name == "\\Q")
w->port_output = true;
else
}
for (auto conn : cell->connections())
- for (int i = 0; i < SIZE(conn.second); i++)
+ for (int i = 0; i < GetSize(conn.second); i++)
{
RTLIL::SigBit bit = sigmap(conn.second[i]);
RTLIL::SigBit tplbit(tpl->wire(conn.first), i);
static RTLIL::Wire *getw(std::vector<RTLIL::Wire*> &wires, RTLIL::Wire *w)
{
while (1) {
- int idx = xorshift32(SIZE(wires));
+ int idx = xorshift32(GetSize(wires));
if (wires[idx] != w && !wires[idx]->port_output)
return wires[idx];
}
for (int i = 0; i < 16; i++)
{
std::vector<int> assumptions;
- for (int j = 0; j < SIZE(in_vec); j++)
+ for (int j = 0; j < GetSize(in_vec); j++)
assumptions.push_back((i & (1 << j)) ? in_vec.at(j) : inverse_in_vec.at(j));
std::vector<bool> results;
for (int i = 0; i < 16; i++)
{
std::vector<int> assumptions;
- for (int j = 0; j < SIZE(in_vec); j++)
+ for (int j = 0; j < GetSize(in_vec); j++)
assumptions.push_back((i & (1 << j)) ? in_vec.at(j) : inverse_in_vec.at(j));
for (int j = 0; j < 4; j++)
xorshift32_state = 0;
int argidx;
- for (argidx = 1; argidx < SIZE(args); argidx++)
+ for (argidx = 1; argidx < GetSize(args); argidx++)
{
- if (args[argidx] == "-n" && argidx+1 < SIZE(args)) {
+ if (args[argidx] == "-n" && argidx+1 < GetSize(args)) {
num_iter = atoi(args[++argidx].c_str());
continue;
}
- if (args[argidx] == "-s" && argidx+1 < SIZE(args)) {
+ if (args[argidx] == "-s" && argidx+1 < GetSize(args)) {
xorshift32_state = atoi(args[++argidx].c_str());
continue;
}
log_header("Executing TEST_AUTOTB backend (auto-generate pseudo-random test benches).\n");
int argidx;
- for (argidx = 1; argidx < SIZE(args); argidx++)
+ for (argidx = 1; argidx < GetSize(args); argidx++)
{
- if (args[argidx] == "-n" && argidx+1 < SIZE(args)) {
+ if (args[argidx] == "-n" && argidx+1 < GetSize(args)) {
num_iter = atoi(args[++argidx].c_str());
continue;
}
cell->setPort("\\BI", wire);
wire = module->addWire("\\X");
- wire->width = SIZE(cell->getPort("\\Y"));
+ wire->width = GetSize(cell->getPort("\\Y"));
wire->port_output = true;
cell->setPort("\\X", wire);
wire = module->addWire("\\CO");
- wire->width = SIZE(cell->getPort("\\Y"));
+ wire->width = GetSize(cell->getPort("\\Y"));
wire->port_output = true;
cell->setPort("\\CO", wire);
}
{
RTLIL::SigSpec sig = conn.second;
- if (SIZE(sig) == 0 || sig[0].wire == nullptr || sig[0].wire->port_output)
+ if (GetSize(sig) == 0 || sig[0].wire == nullptr || sig[0].wire->port_output)
continue;
int n, m;
switch (xorshift32(5))
{
case 0:
- n = xorshift32(SIZE(sig) + 1);
+ n = xorshift32(GetSize(sig) + 1);
for (int i = 0; i < n; i++)
sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
break;
case 1:
- n = xorshift32(SIZE(sig) + 1);
- for (int i = n; i < SIZE(sig); i++)
+ n = xorshift32(GetSize(sig) + 1);
+ for (int i = n; i < GetSize(sig); i++)
sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
break;
case 2:
- n = xorshift32(SIZE(sig));
- m = xorshift32(SIZE(sig));
+ n = xorshift32(GetSize(sig));
+ m = xorshift32(GetSize(sig));
for (int i = std::min(n, m); i < std::max(n, m); i++)
sig[i] = xorshift32(2) == 1 ? RTLIL::S1 : RTLIL::S0;
break;
for (auto port : gold_mod->ports) {
RTLIL::Wire *wire = gold_mod->wire(port);
if (wire->port_input)
- vlog_file << stringf(" reg [%d:0] %s;\n", SIZE(wire)-1, log_id(wire));
+ vlog_file << stringf(" reg [%d:0] %s;\n", GetSize(wire)-1, log_id(wire));
else
- vlog_file << stringf(" wire [%d:0] %s_expr, %s_noexpr;\n", SIZE(wire)-1, log_id(wire), log_id(wire));
+ vlog_file << stringf(" wire [%d:0] %s_expr, %s_noexpr;\n", GetSize(wire)-1, log_id(wire), log_id(wire));
}
vlog_file << stringf(" %s_expr uut_expr(", uut_name.c_str());
- for (int i = 0; i < SIZE(gold_mod->ports); i++)
+ for (int i = 0; i < GetSize(gold_mod->ports); i++)
vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]),
gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_expr");
vlog_file << stringf(");\n");
vlog_file << stringf(" %s_expr uut_noexpr(", uut_name.c_str());
- for (int i = 0; i < SIZE(gold_mod->ports); i++)
+ for (int i = 0; i < GetSize(gold_mod->ports); i++)
vlog_file << stringf("%s.%s(%s%s)", i ? ", " : "", log_id(gold_mod->ports[i]), log_id(gold_mod->ports[i]),
gold_mod->wire(gold_mod->ports[i])->port_input ? "" : "_noexpr");
vlog_file << stringf(");\n");
log_assert(gold_wire != nullptr);
log_assert(gate_wire != nullptr);
log_assert(gold_wire->port_input == gate_wire->port_input);
- log_assert(SIZE(gold_wire) == SIZE(gate_wire));
+ log_assert(GetSize(gold_wire) == GetSize(gate_wire));
if (!gold_wire->port_input)
continue;
RTLIL::Const in_value;
- for (int i = 0; i < SIZE(gold_wire); i++)
+ for (int i = 0; i < GetSize(gold_wire); i++)
in_value.bits.push_back(xorshift32(2) ? RTLIL::S1 : RTLIL::S0);
if (xorshift32(4) == 0) {
int inv_chance = 1 + xorshift32(8);
- for (int i = 0; i < SIZE(gold_wire); i++)
+ for (int i = 0; i < GetSize(gold_wire); i++)
if (xorshift32(inv_chance) == 0)
in_value.bits[i] = RTLIL::Sx;
}
gold_ce.set(gold_wire, in_value);
gate_ce.set(gate_wire, in_value);
- if (vlog_file.is_open() && SIZE(in_value) > 0) {
+ if (vlog_file.is_open() && GetSize(in_value) > 0) {
vlog_file << stringf(" %s = 'b%s;\n", log_id(gold_wire), in_value.as_string().c_str());
if (!vlog_pattern_info.empty())
vlog_pattern_info += " ";
log_assert(gold_wire != nullptr);
log_assert(gate_wire != nullptr);
log_assert(gold_wire->port_output == gate_wire->port_output);
- log_assert(SIZE(gold_wire) == SIZE(gate_wire));
+ log_assert(GetSize(gold_wire) == GetSize(gate_wire));
if (!gold_wire->port_output)
continue;
log_error("Failed to eval %s in gate module.\n", log_id(gate_wire));
bool gold_gate_mismatch = false;
- for (int i = 0; i < SIZE(gold_wire); i++) {
+ for (int i = 0; i < GetSize(gold_wire); i++) {
if (gold_outval[i] == RTLIL::Sx)
continue;
if (gold_outval[i] == gate_outval[i])
if (vlog_file.is_open()) {
vlog_file << stringf(" $display(\"[%s] %s expected: %%b, expr: %%b, noexpr: %%b\", %d'b%s, %s_expr, %s_noexpr);\n",
- vlog_pattern_info.c_str(), log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire));
- vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str());
- vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), SIZE(gold_outval), gold_outval.as_string().c_str());
+ vlog_pattern_info.c_str(), log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str(), log_id(gold_wire), log_id(gold_wire));
+ vlog_file << stringf(" if (%s_expr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str());
+ vlog_file << stringf(" if (%s_noexpr !== %d'b%s) begin $display(\"ERROR\"); $finish; end\n", log_id(gold_wire), GetSize(gold_outval), gold_outval.as_string().c_str());
}
}
if (verbose) {
log("SAT 1: ");
- for (int i = SIZE(out_sig)-1; i >= 0; i--)
+ for (int i = GetSize(out_sig)-1; i >= 0; i--)
log("%c", sat1_model_value.at(i) ? '1' : '0');
log("\n");
}
- for (int i = 0; i < SIZE(out_sig); i++) {
+ for (int i = 0; i < GetSize(out_sig); i++) {
if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1)
continue;
if (out_val[i] == RTLIL::S0 && sat1_model_value.at(i) == false)
if (verbose) {
log("SAT 2: ");
- for (int i = SIZE(out_sig)-1; i >= 0; i--)
- log("%c", sat2_model_value.at(SIZE(out_sig) + i) ? 'x' : sat2_model_value.at(i) ? '1' : '0');
+ for (int i = GetSize(out_sig)-1; i >= 0; i--)
+ log("%c", sat2_model_value.at(GetSize(out_sig) + i) ? 'x' : sat2_model_value.at(i) ? '1' : '0');
log("\n");
}
- for (int i = 0; i < SIZE(out_sig); i++) {
- if (sat2_model_value.at(SIZE(out_sig) + i)) {
+ for (int i = 0; i < GetSize(out_sig); i++) {
+ if (sat2_model_value.at(GetSize(out_sig) + i)) {
if (out_val[i] != RTLIL::S0 && out_val[i] != RTLIL::S1)
continue;
} else {
bool nosat = false;
int argidx;
- for (argidx = 1; argidx < SIZE(args); argidx++)
+ for (argidx = 1; argidx < GetSize(args); argidx++)
{
- if (args[argidx] == "-n" && argidx+1 < SIZE(args)) {
+ if (args[argidx] == "-n" && argidx+1 < GetSize(args)) {
num_iter = atoi(args[++argidx].c_str());
continue;
}
- if (args[argidx] == "-s" && argidx+1 < SIZE(args)) {
+ if (args[argidx] == "-s" && argidx+1 < GetSize(args)) {
xorshift32_state = atoi(args[++argidx].c_str());
continue;
}
- if (args[argidx] == "-map" && argidx+1 < SIZE(args)) {
+ if (args[argidx] == "-map" && argidx+1 < GetSize(args)) {
techmap_cmd += " -map " + args[++argidx];
continue;
}
- if (args[argidx] == "-f" && argidx+1 < SIZE(args)) {
+ if (args[argidx] == "-f" && argidx+1 < GetSize(args)) {
ilang_file = args[++argidx];
num_iter = 1;
continue;
}
- if (args[argidx] == "-script" && argidx+1 < SIZE(args)) {
+ if (args[argidx] == "-script" && argidx+1 < GetSize(args)) {
techmap_cmd = "script " + args[++argidx];
continue;
}
verbose = true;
continue;
}
- if (args[argidx] == "-vlog" && argidx+1 < SIZE(args)) {
+ if (args[argidx] == "-vlog" && argidx+1 < GetSize(args)) {
vlog_file.open(args[++argidx], std::ios_base::trunc);
if (!vlog_file.is_open())
log_cmd_error("Failed to open output file `%s'.\n", args[argidx].c_str());
cell_types["$macc"] = "*";
cell_types["$fa"] = "*";
- for (; argidx < SIZE(args); argidx++)
+ for (; argidx < GetSize(args); argidx++)
{
if (args[argidx].rfind("-", 0) == 0)
log_cmd_error("Unexpected option: %s\n", args[argidx].c_str());
charcount = 0;
} else
cell_type_list += " " + it.first;
- charcount += SIZE(it.first);
+ charcount += GetSize(it.first);
}
log_cmd_error("The cell type `%s' is currently not supported. Try one of these:%s\n",
args[argidx].c_str(), cell_type_list.c_str());
projects / yosys.git / commitdiff