(no commit message)

diff --git a/openpower/sv/svp64-single.mdwn b/openpower/sv/svp64-single.mdwn
index fd5a1c27f4582f4d4b8e1a1e0bb7d6a4cf279ef8..bf46167b2df0d144f17eb967772d4bec41781148 100644 (file)
--- a/openpower/sv/svp64-single.mdwn
+++ b/openpower/sv/svp64-single.mdwn
@@ -2,3 +2,16 @@
 
 * <https://bugs.libre-soc.org/show_bug.cgi?id=905>
 
+encodings concepts:
+
+* 24 bits available
+* vectors not applicable thus EXTRA4 may bring 4 bits (CR Fields) quantity 3of
+  for a total of 12 bits.
+* elwidth src/dest is 2x4 for a total 4 bits
+* single predicate mask (one bit) is 1 for type, 3 for source, totals another 4 bits
+
+totals 20 bits leaving 4 for a "Mode".
+
+* arithmetic can have saturation
+* LD/ST-update needs Post-Increment, others incl. SEA (Signed Effective Address)
+  another bit adds CIA for PC-relative