update 64-bit prefix format

diff --git a/simple_v_extension/sv_prefix_proposal.rst b/simple_v_extension/sv_prefix_proposal.rst
index 7a2c6b843c1b688915906a0e327ef7e0f11263dd..547f906548f432e515dd04d15716bda09c82da24 100644 (file)
--- a/simple_v_extension/sv_prefix_proposal.rst
+++ b/simple_v_extension/sv_prefix_proposal.rst
@@ -1,4 +1,4 @@
-SimpleV Prefix (SVprefix) Proposal v0.2
+SimpleV Prefix (SVprefix) Proposal v0.3
 =======================================
 
 This proposal is designed to be able to operate without SVcsr, but not to
@@ -40,8 +40,8 @@ are reused for additional encoding space in the 48-bit instructions.
 64-bit Prefixed Instructions
 ============================
 
-TODO.  Really need to resolve vitp7 by reducing lsk to 2 bits, or just use
-0b111111 as the prefix, then lsk can remain at 3 bits.
+The 48 bit format is further extended with the full 128-bit range on all source
+and destination registers, and the option to set both VL and MVL is provided.
 
 48-bit Instruction Encodings
 ============================
@@ -123,43 +123,85 @@ Table showing Standard RV32 encodings:
 64-bit Instruction Encodings
 ============================
 
-TODO (please disregard for now, WIP)
-
-+--------------+-------+-------+--------+--------+--------+----------+
-| Encoding     | 63:58 | 57    | 56     | 55     | 54     | 53:48    |
-+--------------+-------+-------+--------+--------+--------+----------+
-| P64-LD-type  | VLtyp | rd[6] | rs1[6] |        |        | MVLtp    |
-+--------------+-------+-------+--------+--------+--------+----------+
-| P64-ST-type  | VLtyp |       | rs1[6] | rs2[6] |        | MVLtp    |
-+--------------+-------+-------+--------+--------+--------+----------+
-| P64-R-type   | VLtyp | rd[6] | rs1[6] | rs2[6] |        | MVLtp    |
-+--------------+-------+-------+--------+--------+--------+----------+
-| P64-I-type   | VLtyp | rd[6] | rs1[6] |        |        | MVLtp    |
-+--------------+-------+-------+--------+--------+--------+----------+
-| P64-U-type   | VLtyp | rd[6] |        |        |        | MVLtp    |
-+--------------+-------+-------+--------+--------+--------+----------+
-| P64-FR-type  | VLtyp |       | rs1[6] | rs2[6] |        | MVLtp    |
-+--------------+-------+-------+--------+--------+--------+----------+
-| P64-FI-type  | VLtyp | rd[6] | rs1[6] | rs2[6] |        | MVLtp    |
-+--------------+-------+-------+--------+--------+--------+----------+
-| P64-FR4-type | VLtyp | rd[6] | rs1[6] | rs2[6] | rs3[6] | MVLtp    |
-+--------------+-------+-------+--------+--------+--------+----------+
-
-The extra bit for src and dest registers provides the full range of up to 128 registers, when combined with the extra bit from the 48 bit prefix as well.
-
-VLtyp
-
-+--------------+---------+
-| vtyp[5:1]    | vtyp[0] |
-+--------------+---------+
-| regnum       |  1      |
-+--------------+---------+
-| immed        |  0      |
-+--------------+---------+
-
-Just as in the VLIW format, when bit 0 of vtyp is zero, bits 1 to 5 specify the scalar register that VL is set from.  When bit 0 is 1, VL is set to the immediate (plus one).
+Where in the 48 bit format the prefix is "0b0011111" in bits 0 to 6, this is
+now set to "0b0111111".
+
++---------------+---------------+--------------+-----------|
+| 63:48         | 47:18         | 17:7         | 6:0       |
++---------------+---------------+--------------+-----------|
+| 64 bit prefix | RV32[31:3]    | P48[17:7]    | 0b0111111 |
++---------------+---------------+--------------+-----------|
+
+* The 64 bit prefix format is below
+* Bits 18 to 47 contain bits 3 to 31 of a standard RV32 format
+* Bits 7 to 17 contain bits 7 through 17 of the P48 format
+* Bits 0 to 6 contain the standard RV 64-bit prefix 0b0111111
+
+64 bit prefix format:
+
++--------------+-------+--------+--------+--------+--------+
+| Encoding     | 63    | 62     | 61     | 60     | 59:48  |
++--------------+-------+--------+--------+--------+--------+
+| P64-LD-type  | rd[6] | rs1[6] |        |        | SVtyp  |
++--------------+-------+--------+--------+--------+--------+
+| P64-ST-type  |       | rs1[6] | rs2[6] |        | SVtyp  |
++--------------+-------+--------+--------+--------+--------+
+| P64-R-type   | rd[6] | rs1[6] | rs2[6] |        | SVtyp  |
++--------------+-------+--------+--------+--------+--------+
+| P64-I-type   | rd[6] | rs1[6] |        |        | SVtyp  |
++--------------+-------+--------+--------+--------+--------+
+| P64-U-type   | rd[6] |        |        |        | SVtyp  |
++--------------+-------+--------+--------+--------+--------+
+| P64-FR-type  |       | rs1[6] | rs2[6] |        | SVtyp  |
++--------------+-------+--------+--------+--------+--------+
+| P64-FI-type  | rd[6] | rs1[6] | rs2[6] |        | SVtyp  |
++--------------+-------+--------+--------+--------+--------+
+| P64-FR4-type | rd[6] | rs1[6] | rs2[6] | rs3[6] | SVtyp  |
++--------------+-------+--------+--------+--------+--------+
+
+The extra bit for src and dest registers provides the full range of
+up to 128 registers, when combined with the extra bit from the 48 bit
+prefix as well.
+
+SVtyp field encoding
+====================
+
++-----------+-------------+--------------+----------+----------------------+
+| SVtyp[11] | SVtyp[10:6] | SVtyp[5:1]   | SVtyp[0] | comment              |
++-----------+-------------+--------------+----------+----------------------+
+| 0         |  000000     | 00000        |  0       | no change to VL/MVL  |
++-----------+-------------+--------------+----------+----------------------+
+| 0         |  VLdest!=0  | 00000        |  0       | reserved             |
++-----------+-------------+--------------+----------+----------------------+
+| 0         |  VLdest     | VLEN         |  vlt     | VL imm/reg mode (vlt)|
++-----------+-------------+--------------+----------+----------------------+
+| 1         |  VLdest     |  MVL+VL-immed           | MVL/VL immed mode    |
++-----------+-------------+--------------+----------+----------------------+
 
+Notes:
+
+* When SVtyp is all zeros, neither VL nor MVL are changed
+* SVtype[11]=0, SVtype[5:0]=0 and SVtype[10:6] non-zero is a reserved encoding.
+  Its uses raises an illegal instruction exception.
+
+Just as in the VLIW format, when bit 11 of SVtyp is zero:
+
+* if vlt is zero, bits 1 to 5 specify the VLEN as a 5 bit immediate
+  (offset by 1: 0b00000 represents VL=1, 0b00001 represents VL=2 etc.)
+* if vlt is 1, bits 1 to 5 specify the scalar (RV standard) register
+  from which VL is set.  x0 is not permitted
+* VL goes into the scalar register VLdest (if VLdest is not x0)
+
+When bit 11 of SVtype is 1:
+
+* both MAXVL and VL are set to (VLenimmed+1)
+* the same value goes into the scalar register VLdest (if VLdest is not x0)
 
+This gives the option to set up VL in a "loop mode" (SVtype[11]=0) or
+in a "one-off" mode (SVtype[11]=1) which sets both MVL and VL to the
+same immediate value.  This may be most useful for one-off Vectorised
+operations such as LOAD-MULTI / STORE-MULTI, for saving and restoration
+of large batches of registers in context-switches or function calls.
 
 vs#/vd Fields' Encoding
 =======================