---------- Begin Simulation Statistics ----------
-sim_seconds 2.843665 # Number of seconds simulated
-sim_ticks 2843665155500 # Number of ticks simulated
-final_tick 2843665155500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.843655 # Number of seconds simulated
+sim_ticks 2843654861000 # Number of ticks simulated
+final_tick 2843654861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 158211 # Simulator instruction rate (inst/s)
-host_op_rate 191554 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 3597700350 # Simulator tick rate (ticks/s)
-host_mem_usage 605956 # Number of bytes of host memory used
-host_seconds 790.41 # Real time elapsed on the host
-sim_insts 125052080 # Number of instructions simulated
-sim_ops 151406456 # Number of ops (including micro ops) simulated
+host_inst_rate 157498 # Simulator instruction rate (inst/s)
+host_op_rate 190690 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3581426538 # Simulator tick rate (ticks/s)
+host_mem_usage 613612 # Number of bytes of host memory used
+host_seconds 794.00 # Real time elapsed on the host
+sim_insts 125053138 # Number of instructions simulated
+sim_ops 151407658 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1364476 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766720 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1363068 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 10771008 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 533600 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 1164672 # Number of bytes read from this memory
-system.physmem.bytes_read::total 13841116 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 419072 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 26240 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 445312 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7174080 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 534304 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 1165248 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 13845276 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 418688 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 26560 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 445248 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7176128 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9510160 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9512208 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 21845 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 168230 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 21823 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 168297 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 8361 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 18198 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 216816 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 112095 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 8372 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 18207 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 216881 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 112127 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 152755 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 152787 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 3398 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 479830 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 3786212 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 479337 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 3787734 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 338 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 187645 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 409567 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4867351 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 147370 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 9228 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 156598 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2522829 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 815263 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 187893 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 409771 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4868831 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 147236 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 9340 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 156576 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2523558 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3344332 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2522829 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 815601 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 815266 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3345064 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2523558 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 3398 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 486056 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 3786212 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 485562 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 3787734 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 338 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 187659 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 409567 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 8211683 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 216816 # Number of read requests accepted
-system.physmem.writeReqs 152755 # Number of write requests accepted
-system.physmem.readBursts 216816 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 152755 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 13860032 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 16192 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9524672 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 13841116 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 9510160 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 253 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu1.inst 187907 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 409771 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 815604 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 8213896 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 216881 # Number of read requests accepted
+system.physmem.writeReqs 152787 # Number of write requests accepted
+system.physmem.readBursts 216881 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 152787 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 13864960 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 15424 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9526912 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 13845276 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 9512208 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 241 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 13536 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 13436 # Per bank write bursts
-system.physmem.perBankRdBursts::1 13084 # Per bank write bursts
-system.physmem.perBankRdBursts::2 14401 # Per bank write bursts
-system.physmem.perBankRdBursts::3 13747 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 13516 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 13445 # Per bank write bursts
+system.physmem.perBankRdBursts::1 13090 # Per bank write bursts
+system.physmem.perBankRdBursts::2 14400 # Per bank write bursts
+system.physmem.perBankRdBursts::3 13760 # Per bank write bursts
system.physmem.perBankRdBursts::4 15799 # Per bank write bursts
-system.physmem.perBankRdBursts::5 12797 # Per bank write bursts
-system.physmem.perBankRdBursts::6 13572 # Per bank write bursts
-system.physmem.perBankRdBursts::7 13744 # Per bank write bursts
-system.physmem.perBankRdBursts::8 13565 # Per bank write bursts
-system.physmem.perBankRdBursts::9 13602 # Per bank write bursts
-system.physmem.perBankRdBursts::10 13295 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11895 # Per bank write bursts
-system.physmem.perBankRdBursts::12 13378 # Per bank write bursts
-system.physmem.perBankRdBursts::13 13725 # Per bank write bursts
-system.physmem.perBankRdBursts::14 13486 # Per bank write bursts
-system.physmem.perBankRdBursts::15 13037 # Per bank write bursts
-system.physmem.perBankWrBursts::0 9315 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9418 # Per bank write bursts
-system.physmem.perBankWrBursts::2 10151 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9572 # Per bank write bursts
-system.physmem.perBankWrBursts::4 8971 # Per bank write bursts
-system.physmem.perBankWrBursts::5 8910 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9379 # Per bank write bursts
-system.physmem.perBankWrBursts::7 9378 # Per bank write bursts
+system.physmem.perBankRdBursts::5 12812 # Per bank write bursts
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+system.physmem.perBankRdBursts::7 13750 # Per bank write bursts
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+system.physmem.perBankRdBursts::9 13600 # Per bank write bursts
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+system.physmem.perBankRdBursts::11 11904 # Per bank write bursts
+system.physmem.perBankRdBursts::12 13370 # Per bank write bursts
+system.physmem.perBankRdBursts::13 13720 # Per bank write bursts
+system.physmem.perBankRdBursts::14 13497 # Per bank write bursts
+system.physmem.perBankRdBursts::15 13045 # Per bank write bursts
+system.physmem.perBankWrBursts::0 9322 # Per bank write bursts
+system.physmem.perBankWrBursts::1 9428 # Per bank write bursts
+system.physmem.perBankWrBursts::2 10143 # Per bank write bursts
+system.physmem.perBankWrBursts::3 9576 # Per bank write bursts
+system.physmem.perBankWrBursts::4 8974 # Per bank write bursts
+system.physmem.perBankWrBursts::5 8900 # Per bank write bursts
+system.physmem.perBankWrBursts::6 9376 # Per bank write bursts
+system.physmem.perBankWrBursts::7 9386 # Per bank write bursts
system.physmem.perBankWrBursts::8 9384 # Per bank write bursts
-system.physmem.perBankWrBursts::9 9425 # Per bank write bursts
-system.physmem.perBankWrBursts::10 9360 # Per bank write bursts
-system.physmem.perBankWrBursts::11 8832 # Per bank write bursts
-system.physmem.perBankWrBursts::12 9377 # Per bank write bursts
-system.physmem.perBankWrBursts::13 9192 # Per bank write bursts
-system.physmem.perBankWrBursts::14 9288 # Per bank write bursts
-system.physmem.perBankWrBursts::15 8871 # Per bank write bursts
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+system.physmem.perBankWrBursts::14 9289 # Per bank write bursts
+system.physmem.perBankWrBursts::15 8875 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
-system.physmem.totGap 2843662895000 # Total gap between requests
+system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
+system.physmem.totGap 2843652584000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 559 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 216229 # Read request sizes (log2)
+system.physmem.readPktSize::6 216294 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4436 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 148319 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 79263 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 62843 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 148351 # Write request sizes (log2)
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 92579 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 252.591884 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 143.134462 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 307.650054 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 46986 50.75% 50.75% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 18789 20.30% 71.05% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6843 7.39% 78.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3586 3.87% 82.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3022 3.26% 85.58% # Bytes accessed per row activation
+system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 92618 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 252.562223 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 143.207145 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 307.469960 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 46921 50.66% 50.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 18876 20.38% 71.04% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6855 7.40% 78.44% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3600 3.89% 82.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 3008 3.25% 85.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 2120 2.29% 87.87% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1307 1.41% 89.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1131 1.22% 90.50% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 8795 9.50% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 92579 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 7460 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 29.029759 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 529.579779 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 7459 99.99% 99.99% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::768-895 1341 1.45% 89.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1115 1.20% 90.52% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 8782 9.48% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 92618 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 7463 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 29.028407 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 529.473600 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 7462 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 7460 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 7460 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.949464 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.624141 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 10.915893 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 6155 82.51% 82.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 493 6.61% 89.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 89 1.19% 90.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 200 2.68% 92.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 188 2.52% 95.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 17 0.23% 95.74% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 27 0.36% 96.10% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 16 0.21% 96.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 36 0.48% 96.80% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 10 0.13% 96.93% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 5 0.07% 97.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 4 0.05% 97.05% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 168 2.25% 99.30% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 5 0.07% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 3 0.04% 99.41% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 4 0.05% 99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 10 0.13% 99.60% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.01% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 1 0.01% 99.62% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.01% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 2 0.03% 99.66% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 2 0.03% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 5 0.07% 99.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 4 0.05% 99.88% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.01% 99.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.01% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 3 0.04% 99.95% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 4 0.05% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 7460 # Writes before turning the bus around for reads
-system.physmem.totQLat 7660076750 # Total ticks spent queuing
-system.physmem.totMemAccLat 11720633000 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1082815000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 35371.12 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 7463 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 7463 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.946134 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.603737 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.129560 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 6171 82.69% 82.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 489 6.55% 89.24% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::52-55 6 0.08% 96.82% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::68-71 7 0.09% 99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 6 0.08% 99.33% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 18 0.24% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.01% 99.58% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::96-99 7 0.09% 99.71% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::100-103 1 0.01% 99.72% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads
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+system.physmem.wrPerTurnAround::112-115 3 0.04% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.01% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 8 0.11% 99.92% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::136-139 1 0.01% 99.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 3 0.04% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 7463 # Writes before turning the bus around for reads
+system.physmem.totQLat 7683149500 # Total ticks spent queuing
+system.physmem.totMemAccLat 11745149500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1083200000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 35465.05 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 54121.12 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s
+system.physmem.avgMemAccLat 54215.05 # Average memory access latency per DRAM burst
+system.physmem.avgRdBW 4.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.34 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing
-system.physmem.readRowHits 183124 # Number of row buffer hits during reads
-system.physmem.writeRowHits 89683 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 26.48 # Average write queue length when enqueuing
+system.physmem.readRowHits 183194 # Number of row buffer hits during reads
+system.physmem.writeRowHits 89685 # Number of row buffer hits during writes
system.physmem.readRowHitRate 84.56 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 60.25 # Row buffer hit rate for writes
-system.physmem.avgGap 7694496.85 # Average gap between requests
+system.physmem.writeRowHitRate 60.24 # Row buffer hit rate for writes
+system.physmem.avgGap 7692449.94 # Average gap between requests
system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2709761139750 # Time in different power states
-system.physmem.memoryStateTime::REF 94956160000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2709796310750 # Time in different power states
+system.physmem.memoryStateTime::REF 94955640000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 38946040250 # Time in different power states
+system.physmem.memoryStateTime::ACT 38900516750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 358880760 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 341016480 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 195817875 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 186070500 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 862524000 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 826667400 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 486609120 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 477763920 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 185734248960 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 185734248960 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 81966350835 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 81438405435 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1634297688000 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1634760798000 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1903902119550 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1903764970695 # Total energy per rank (pJ)
-system.physmem.averagePower::0 669.524448 # Core power per rank (mW)
-system.physmem.averagePower::1 669.476219 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 238011 # Transaction distribution
-system.membus.trans_dist::ReadResp 238011 # Transaction distribution
-system.membus.trans_dist::WriteReq 30931 # Transaction distribution
-system.membus.trans_dist::WriteResp 30931 # Transaction distribution
-system.membus.trans_dist::Writeback 112095 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 79719 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 39980 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 13536 # Transaction distribution
-system.membus.trans_dist::ReadExReq 30379 # Transaction distribution
-system.membus.trans_dist::ReadExResp 13328 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704855 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 826435 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 899141 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21031980 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 21223190 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 23542486 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 123442 # Total snoops (count)
-system.membus.snoop_fanout::samples 498376 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 498376 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
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-system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency
-system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 104673.151799 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 758 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 21 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs 36.095238 # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
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-system.l2c.writebacks::writebacks 112095 # number of writebacks
-system.l2c.writebacks::total 112095 # number of writebacks
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-system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2665 # number of UpgradeReq MSHR misses
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-system.l2c.overall_mshr_misses::total 213169 # number of overall MSHR misses
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69294.934641 # average ReadReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.597373 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.680889 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10125.459574 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10045.077840 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10066.928282 # average SCUpgradeReq mshr miss latency
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-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61758.029925 # average ReadExReq mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
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+system.physmem.refreshEnergy::0 185733231840 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 185733231840 # Energy for refresh commands per rank (pJ)
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+system.physmem.totalEnergy::1 1903754909880 # Total energy per rank (pJ)
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+system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 668242 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 668227 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30931 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30931 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 252491 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 92430 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 40345 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 132775 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 38935 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 38935 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370727 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368021 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1738748 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41983735 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7870623 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 49854358 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 291977 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 1090667 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.033442 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.179788 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 1054193 96.66% 96.66% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36474 3.34% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 1090667 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 1589069612 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2362873368 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 802585372 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59405 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq 35 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 326655076 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36825386 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu0.branchPred.lookups 34893743 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 17129146 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 1674704 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 20005904 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 14465623 # Number of BTB hits
+system.cpu0.branchPred.lookups 34892527 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 17126488 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 1674515 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 20008950 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 14462185 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 72.306770 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 10813555 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 822515 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 72.278580 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 10813099 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 822816 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 23970791 # DTB read hits
-system.cpu0.dtb.read_misses 62431 # DTB read misses
-system.cpu0.dtb.write_hits 17948475 # DTB write hits
-system.cpu0.dtb.write_misses 6765 # DTB write misses
+system.cpu0.dtb.read_hits 23969265 # DTB read hits
+system.cpu0.dtb.read_misses 62663 # DTB read misses
+system.cpu0.dtb.write_hits 17948332 # DTB write hits
+system.cpu0.dtb.write_misses 6711 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3473 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 1381 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1976 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3475 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1396 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 1982 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 24033222 # DTB read accesses
-system.cpu0.dtb.write_accesses 17955240 # DTB write accesses
+system.cpu0.dtb.perms_faults 568 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 24031928 # DTB read accesses
+system.cpu0.dtb.write_accesses 17955043 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 41919266 # DTB hits
-system.cpu0.dtb.misses 69196 # DTB misses
-system.cpu0.dtb.accesses 41988462 # DTB accesses
+system.cpu0.dtb.hits 41917597 # DTB hits
+system.cpu0.dtb.misses 69374 # DTB misses
+system.cpu0.dtb.accesses 41986971 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 70366530 # ITB inst hits
-system.cpu0.itb.inst_misses 3846 # ITB inst misses
+system.cpu0.itb.inst_hits 70358748 # ITB inst hits
+system.cpu0.itb.inst_misses 3854 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 7369 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 7388 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 70370376 # ITB inst accesses
-system.cpu0.itb.hits 70366530 # DTB hits
-system.cpu0.itb.misses 3846 # DTB misses
-system.cpu0.itb.accesses 70370376 # DTB accesses
-system.cpu0.numCycles 229133691 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 70362602 # ITB inst accesses
+system.cpu0.itb.hits 70358748 # DTB hits
+system.cpu0.itb.misses 3854 # DTB misses
+system.cpu0.itb.accesses 70362602 # DTB accesses
+system.cpu0.numCycles 229119066 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 109191897 # Number of instructions committed
-system.cpu0.committedOps 132018821 # Number of ops (including micro ops) committed
-system.cpu0.discardedOps 8795011 # Number of ops (including micro ops) which were discarded before commit
-system.cpu0.numFetchSuspends 1826 # Number of times Execute suspended instruction fetching
-system.cpu0.quiesceCycles 5458210303 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.cpi 2.098450 # CPI: cycles per instruction
-system.cpu0.ipc 0.476542 # IPC: instructions per cycle
+system.cpu0.committedInsts 109189984 # Number of instructions committed
+system.cpu0.committedOps 132016369 # Number of ops (including micro ops) committed
+system.cpu0.discardedOps 8791665 # Number of ops (including micro ops) which were discarded before commit
+system.cpu0.numFetchSuspends 1828 # Number of times Execute suspended instruction fetching
+system.cpu0.quiesceCycles 5458204948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.cpi 2.098352 # CPI: cycles per instruction
+system.cpu0.ipc 0.476564 # IPC: instructions per cycle
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed
-system.cpu0.tickCycles 193242697 # Number of cycles that the object actually ticked
-system.cpu0.idleCycles 35890994 # Total number of cycles that the object has spent stopped
-system.cpu0.icache.tags.replacements 1983122 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.796419 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 68375163 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1983634 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 34.469647 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 1830 # number of quiesce instructions executed
+system.cpu0.tickCycles 193229301 # Number of cycles that the object actually ticked
+system.cpu0.idleCycles 35889765 # Total number of cycles that the object has spent stopped
+system.cpu0.dcache.tags.replacements 714801 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 493.827802 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 40473769 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 715313 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 56.581901 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.inst 493.827802 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.964507 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.964507 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id
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-system.cpu0.icache.overall_avg_miss_latency::total 8339.632927 # average overall miss latency
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+system.cpu0.icache.ReadReq_miss_latency::total 16546799645 # number of ReadReq miss cycles
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+system.cpu0.icache.demand_miss_latency::total 16546799645 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 16546799645 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 16546799645 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 70351017 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 70351017 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 70351017 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 70351017 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 70351017 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 70351017 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028203 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.028203 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028203 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.028203 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028203 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.028203 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.725661 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.725661 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 8339.725661 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 8339.725661 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1983656 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 1983656 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 1983656 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 1983656 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 1983656 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 1983656 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13565509604 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 13565509604 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13565509604 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 13565509604 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13565509604 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency::total 13565509604 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1984094 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 1984094 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 1984094 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 1984094 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 1984094 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 1984094 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13568682853 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 13568682853 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13568682853 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 13568682853 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13568682853 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 13568682853 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276787500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276787500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276787500 # number of overall MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::total 276787500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028193 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total 0.028193 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total 0.028193 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.640169 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028203 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.028203 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.028203 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.729845 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 2764616 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 2669805 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 28812 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 28812 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 518092 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 696796 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 70569 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42644 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 93797 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 291655 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 282058 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3973433 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393866 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11794 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 167556 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 6546649 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127149824 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86895095 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17624 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313964 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 214376507 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 1084116 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 4385551 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.219745 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.414074 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 3421847 78.03% 78.03% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 963704 21.97% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 4385551 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 2275908733 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 119359000 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 2981732395 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1235696460 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 7392491 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 89085972 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17333419 # number of hwpf identified
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425629 # number of hwpf that were already in mshr
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16380209 # number of hwpf that were already in the cache
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9025 # number of hwpf that were already in the prefetch queue
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17337039 # number of hwpf identified
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425762 # number of hwpf that were already in mshr
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16383461 # number of hwpf that were already in the cache
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9078 # number of hwpf that were already in the prefetch queue
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6465 # number of hwpf removed because MSHR allocated
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512088 # number of hwpf issued
-system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329549 # number of hwpf spanning a virtual page
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6456 # number of hwpf removed because MSHR allocated
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512279 # number of hwpf issued
+system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329409 # number of hwpf spanning a virtual page
system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l2cache.tags.replacements 409658 # number of replacements
-system.cpu0.l2cache.tags.tagsinuse 16201.472263 # Cycle average of tags in use
-system.cpu0.l2cache.tags.total_refs 3013143 # Total number of references to valid blocks.
-system.cpu0.l2cache.tags.sampled_refs 425913 # Sample count of references to valid blocks.
-system.cpu0.l2cache.tags.avg_refs 7.074550 # Average number of references to valid blocks.
-system.cpu0.l2cache.tags.warmup_cycle 2824446064500 # Cycle when the warmup percentage was hit.
-system.cpu0.l2cache.tags.occ_blocks::writebacks 4208.967244 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.817277 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.069510 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2196.768436 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.849796 # Average occupied blocks per requestor
-system.cpu0.l2cache.tags.occ_percent::writebacks 0.256895 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002919 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.replacements 409357 # number of replacements
+system.cpu0.l2cache.tags.tagsinuse 16202.462840 # Cycle average of tags in use
+system.cpu0.l2cache.tags.total_refs 3013500 # Total number of references to valid blocks.
+system.cpu0.l2cache.tags.sampled_refs 425611 # Sample count of references to valid blocks.
+system.cpu0.l2cache.tags.avg_refs 7.080409 # Average number of references to valid blocks.
+system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.l2cache.tags.occ_blocks::writebacks 4205.324174 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 51.364575 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062072 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2198.474976 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.237044 # Average occupied blocks per requestor
+system.cpu0.l2cache.tags.occ_percent::writebacks 0.256673 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003135 # Average percentage of cache occupancy
system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134080 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594962 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_percent::total 0.988859 # Average percentage of cache occupancy
-system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8953 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7296 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 51 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 115 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2849 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5159 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 779 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134184 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594924 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_percent::total 0.988920 # Average percentage of cache occupancy
+system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8963 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id
+system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7281 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 54 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2805 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5150 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 820 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id
+system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id
system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3166 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id
-system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 286 # Occupied blocks per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.546448 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.445312 # Percentage of cache occupancy per task id
-system.cpu0.l2cache.tags.tag_accesses 55304097 # Number of tag accesses
-system.cpu0.l2cache.tags.data_accesses 55304097 # Number of data accesses
-system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77521 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4240 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2390628 # number of ReadReq hits
-system.cpu0.l2cache.ReadReq_hits::total 2472389 # number of ReadReq hits
-system.cpu0.l2cache.Writeback_hits::writebacks 518092 # number of Writeback hits
-system.cpu0.l2cache.Writeback_hits::total 518092 # number of Writeback hits
-system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4676 # number of UpgradeReq hits
-system.cpu0.l2cache.UpgradeReq_hits::total 4676 # number of UpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2297 # number of SCUpgradeReq hits
-system.cpu0.l2cache.SCUpgradeReq_hits::total 2297 # number of SCUpgradeReq hits
-system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 223112 # number of ReadExReq hits
-system.cpu0.l2cache.ReadExReq_hits::total 223112 # number of ReadExReq hits
-system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77521 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4240 # number of demand (read+write) hits
-system.cpu0.l2cache.demand_hits::cpu0.inst 2613740 # number of demand (read+write) hits
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+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27509.077572 # average ReadExReq mshr miss latency
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+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25492.815284 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38357.472316 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 714989 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 494.379861 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 40475201 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 715501 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 56.569035 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.379861 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965586 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.965586 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 83786238 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 83786238 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.inst 22803865 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 22803865 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862785 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 16862785 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381543 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 381543 # number of LoadLockedReq hits
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-system.cpu0.dcache.StoreCondReq_hits::total 362585 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.inst 39666650 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 39666650 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.inst 39666650 # number of overall hits
-system.cpu0.dcache.overall_hits::total 39666650 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.inst 537471 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 537471 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.inst 532850 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 532850 # number of WriteReq misses
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-system.cpu0.dcache.LoadLockedReq_misses::total 6422 # number of LoadLockedReq misses
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-system.cpu0.dcache.StoreCondReq_misses::total 20250 # number of StoreCondReq misses
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-system.cpu0.dcache.ReadReq_miss_latency::total 6609205728 # number of ReadReq miss cycles
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-system.cpu0.dcache.WriteReq_miss_latency::total 8024129751 # number of WriteReq miss cycles
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-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles
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-system.cpu0.dcache.LoadLockedReq_accesses::total 387965 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu0.dcache.StoreCondReq_accesses::total 382835 # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016553 # miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.overall_miss_rate::total 0.026274 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12296.860162 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12296.860162 # average ReadReq miss latency
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-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16544.261756 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21634.249037 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21634.249037 # average StoreCondReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 13671.912892 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13671.912892 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
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-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.writebacks::total 518095 # number of writebacks
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-system.cpu0.dcache.ReadReq_mshr_hits::total 42683 # number of ReadReq MSHR hits
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-system.cpu0.dcache.WriteReq_mshr_hits::total 230741 # number of WriteReq MSHR hits
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-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4273159157 # number of WriteReq MSHR miss cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93352250 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397142457 # number of StoreCondReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles
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-system.cpu0.dcache.demand_mshr_miss_latency::total 9391203337 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191390497 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191390497 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803718496 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803718496 # number of WriteReq MSHR uncacheable cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995108993 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021198 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021198 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017367 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017367 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016550 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016550 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052895 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052895 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.019562 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.019562 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10343.913312 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10343.913312 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14144.428524 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14144.428524 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14538.584333 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14538.584333 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19611.973185 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19611.973185 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 4041852 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 2340524 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 248983 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 2647417 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 1629039 # Number of BTB hits
+system.cpu0.toL2Bus.trans_dist::ReadReq 2765429 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 2670282 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 517951 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 696439 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 70465 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42615 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 93717 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 291656 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 282057 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3974309 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393187 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11845 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168040 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 6547381 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127177856 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86874167 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17764 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 315068 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 214384855 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 1083965 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 4385734 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.219720 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.414057 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 3422100 78.03% 78.03% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 963634 21.97% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 4385734 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 2275890990 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 119346000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer0.occupancy 2982392646 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy 1235371968 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer2.occupancy 7407493 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer3.occupancy 89292476 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.branchPred.lookups 4040174 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2339682 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 248924 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 2652147 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 1629183 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 61.533147 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 795039 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 55831 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 61.428835 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 794888 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 55483 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 4061119 # DTB read hits
-system.cpu1.dtb.read_misses 20366 # DTB read misses
-system.cpu1.dtb.write_hits 3327004 # DTB write hits
-system.cpu1.dtb.write_misses 1507 # DTB write misses
+system.cpu1.dtb.read_hits 4061400 # DTB read hits
+system.cpu1.dtb.read_misses 20326 # DTB read misses
+system.cpu1.dtb.write_hits 3327397 # DTB write hits
+system.cpu1.dtb.write_misses 1493 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2038 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 134 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 130 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 275 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 4081485 # DTB read accesses
-system.cpu1.dtb.write_accesses 3328511 # DTB write accesses
+system.cpu1.dtb.read_accesses 4081726 # DTB read accesses
+system.cpu1.dtb.write_accesses 3328890 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 7388123 # DTB hits
-system.cpu1.dtb.misses 21873 # DTB misses
-system.cpu1.dtb.accesses 7409996 # DTB accesses
+system.cpu1.dtb.hits 7388797 # DTB hits
+system.cpu1.dtb.misses 21819 # DTB misses
+system.cpu1.dtb.accesses 7410616 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 7667797 # ITB inst hits
-system.cpu1.itb.inst_misses 2228 # ITB inst misses
+system.cpu1.itb.inst_hits 7665717 # ITB inst hits
+system.cpu1.itb.inst_misses 2240 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1155 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1890 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 7670025 # ITB inst accesses
-system.cpu1.itb.hits 7667797 # DTB hits
-system.cpu1.itb.misses 2228 # DTB misses
-system.cpu1.itb.accesses 7670025 # DTB accesses
-system.cpu1.numCycles 40526065 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 7667957 # ITB inst accesses
+system.cpu1.itb.hits 7665717 # DTB hits
+system.cpu1.itb.misses 2240 # DTB misses
+system.cpu1.itb.accesses 7667957 # DTB accesses
+system.cpu1.numCycles 40520229 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 15860183 # Number of instructions committed
-system.cpu1.committedOps 19387635 # Number of ops (including micro ops) committed
-system.cpu1.discardedOps 1556469 # Number of ops (including micro ops) which were discarded before commit
-system.cpu1.numFetchSuspends 2802 # Number of times Execute suspended instruction fetching
-system.cpu1.quiesceCycles 5646205885 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.cpi 2.555208 # CPI: cycles per instruction
-system.cpu1.ipc 0.391358 # IPC: instructions per cycle
+system.cpu1.committedInsts 15863154 # Number of instructions committed
+system.cpu1.committedOps 19391289 # Number of ops (including micro ops) committed
+system.cpu1.discardedOps 1555006 # Number of ops (including micro ops) which were discarded before commit
+system.cpu1.numFetchSuspends 2808 # Number of times Execute suspended instruction fetching
+system.cpu1.quiesceCycles 5646190749 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.cpi 2.554361 # CPI: cycles per instruction
+system.cpu1.ipc 0.391487 # IPC: instructions per cycle
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2803 # number of quiesce instructions executed
-system.cpu1.tickCycles 29467033 # Number of cycles that the object actually ticked
-system.cpu1.idleCycles 11059032 # Total number of cycles that the object has spent stopped
-system.cpu1.icache.tags.replacements 893075 # number of replacements
-system.cpu1.icache.tags.tagsinuse 499.459055 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 6772156 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 893587 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 7.578620 # Average number of references to valid blocks.
+system.cpu1.kern.inst.quiesce 2810 # number of quiesce instructions executed
+system.cpu1.tickCycles 29462484 # Number of cycles that the object actually ticked
+system.cpu1.idleCycles 11057745 # Total number of cycles that the object has spent stopped
+system.cpu1.dcache.tags.replacements 188500 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 474.724355 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 6998456 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 188865 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 37.055336 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.inst 474.724355 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927196 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.927196 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 14854828 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 14854828 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.inst 3752021 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 3752021 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051608 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 3051608 # number of WriteReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88860 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 88860 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69213 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 69213 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.inst 6803629 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 6803629 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.inst 6803629 # number of overall hits
+system.cpu1.dcache.overall_hits::total 6803629 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.inst 182037 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 182037 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.inst 139457 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 139457 # number of WriteReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5164 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 5164 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23160 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 23160 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.inst 321494 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 321494 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.inst 321494 # number of overall misses
+system.cpu1.dcache.overall_misses::total 321494 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2747896424 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 2747896424 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3339347493 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 3339347493 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93721501 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 93721501 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540094758 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 540094758 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 317500 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 317500 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.inst 6087243917 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 6087243917 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.inst 6087243917 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 6087243917 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3934058 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 3934058 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3191065 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 3191065 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94024 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 94024 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92373 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 92373 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.inst 7125123 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 7125123 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.inst 7125123 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 7125123 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046272 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.046272 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043702 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.043702 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054922 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054922 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250723 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250723 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045121 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.045121 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045121 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.045121 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15095.263183 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15095.263183 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23945.355866 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 23945.355866 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18149.012587 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18149.012587 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23320.153627 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23320.153627 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 18934.238017 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18934.238017 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks 115754 # number of writebacks
+system.cpu1.dcache.writebacks::total 115754 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15456 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 15456 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49471 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 49471 # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64927 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 64927 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64927 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 64927 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166581 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 166581 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89986 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 89986 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5164 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5164 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23160 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23160 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256567 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 256567 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256567 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 256567 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2204876516 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2204876516 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 1996537354 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1996537354 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83385499 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83385499 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492548242 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492548242 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 303500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 303500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4201413870 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4201413870 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4201413870 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4201413870 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329634997 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329634997 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202961999 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202961999 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532596996 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532596996 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042343 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042343 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028199 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028199 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054922 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054922 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250723 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250723 # mshr miss rate for StoreCondReq accesses
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+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.036009 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13236.062432 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13236.062432 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22187.199720 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22187.199720 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16147.463013 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.463013 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21267.195250 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21267.195250 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements 893030 # number of replacements
+system.cpu1.icache.tags.tagsinuse 499.459009 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 6770083 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 893542 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 7.576681 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 71221486500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459055 # Average occupied blocks per requestor
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459009 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::2 465 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 16225073 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 16225073 # Number of data accesses
-system.cpu1.icache.ReadReq_hits::cpu1.inst 6772156 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 6772156 # number of ReadReq hits
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-system.cpu1.icache.demand_hits::total 6772156 # number of demand (read+write) hits
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-system.cpu1.icache.overall_hits::total 6772156 # number of overall hits
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-system.cpu1.icache.ReadReq_misses::total 893587 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 893587 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 893587 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 893587 # number of overall misses
-system.cpu1.icache.overall_misses::total 893587 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7266352748 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 7266352748 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 7266352748 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 7266352748 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 7266352748 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 7266352748 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 7665743 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 7665743 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::cpu1.inst 7665743 # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total 7665743 # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::cpu1.inst 7665743 # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total 7665743 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116569 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.116569 # miss rate for ReadReq accesses
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-system.cpu1.icache.demand_miss_rate::total 0.116569 # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::total 0.116569 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8131.667927 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 8131.667927 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 8131.667927 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 8131.667927 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 16220792 # Number of tag accesses
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+system.cpu1.icache.demand_miss_latency::total 7266670468 # number of demand (read+write) miss cycles
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+system.cpu1.icache.overall_miss_latency::total 7266670468 # number of overall miss cycles
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+system.cpu1.icache.overall_accesses::total 7663625 # number of overall (read+write) accesses
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+system.cpu1.icache.demand_miss_rate::total 0.116595 # miss rate for demand accesses
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+system.cpu1.icache.overall_miss_rate::total 0.116595 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8132.433023 # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_miss_latency::total 8132.433023 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency
+system.cpu1.icache.demand_avg_miss_latency::total 8132.433023 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::total 8132.433023 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893587 # number of ReadReq MSHR misses
-system.cpu1.icache.ReadReq_mshr_misses::total 893587 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses::cpu1.inst 893587 # number of demand (read+write) MSHR misses
-system.cpu1.icache.demand_mshr_misses::total 893587 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses::cpu1.inst 893587 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_misses::total 893587 # number of overall MSHR misses
-system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923590752 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923590752 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923590752 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 5923590752 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923590752 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::total 5923590752 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893542 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 893542 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 893542 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 893542 # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst 893542 # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total 893542 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923954530 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923954530 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923954530 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 5923954530 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923954530 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 5923954530 # number of overall MSHR miss cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10589750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10589750 # number of ReadReq MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10589750 # number of overall MSHR uncacheable cycles
system.cpu1.icache.overall_mshr_uncacheable_latency::total 10589750 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116569 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total 0.116569 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.116569 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.002830 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.743795 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 1582924 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 1137885 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 2119 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 2119 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 115746 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 150971 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 84405 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41125 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 85149 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 76810 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 64398 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787404 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 768912 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6948 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51790 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2615054 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57196928 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24920351 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10668 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 94516 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 82222463 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 838516 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 2085340 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.363825 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.481099 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 1326642 63.62% 63.62% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 758698 36.38% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 2085340 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 782793185 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 78444000 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 1341767498 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 381370915 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
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+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.066269 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.065467 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.940435 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.940435 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.966690 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.966690 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.532527 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.532527 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091092 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089745 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091092 # mshr miss rate for overall accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.939566 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.939566 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.968048 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.968048 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.531648 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.531648 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089776 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181461 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15537.988048 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15526.856414 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27956.720991 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27956.720991 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14366.724933 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14366.724933 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13752.978129 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13752.978129 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181579 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15556.048375 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15542.478332 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27988.792401 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14371.563433 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14371.563433 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13747.490054 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13747.490054 # average SCUpgradeReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency
system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27041.387971 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27041.387971 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19126.060404 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19089.071657 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19126.060404 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27956.720991 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23571.079693 # average overall mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27011.845416 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27011.845416 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19084.266825 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23586.237254 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 188481 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 475.009191 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 6997616 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 188846 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 37.054616 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.inst 475.009191 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927752 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.927752 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 14853075 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 14853075 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.inst 3751603 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 3751603 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051213 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 3051213 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88863 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 88863 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69198 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 69198 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.inst 6802816 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 6802816 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.inst 6802816 # number of overall hits
-system.cpu1.dcache.overall_hits::total 6802816 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.inst 182008 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 182008 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.inst 139434 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 139434 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5163 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 5163 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23176 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23176 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.inst 321442 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 321442 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.inst 321442 # number of overall misses
-system.cpu1.dcache.overall_misses::total 321442 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2744686684 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2744686684 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3345931004 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 3345931004 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93833250 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 93833250 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540125753 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 540125753 # number of StoreCondReq miss cycles
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-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 353500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.inst 6090617688 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 6090617688 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.inst 6090617688 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 6090617688 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3933611 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 3933611 # number of ReadReq accesses(hits+misses)
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-system.cpu1.dcache.WriteReq_accesses::total 3190647 # number of WriteReq accesses(hits+misses)
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-system.cpu1.dcache.LoadLockedReq_accesses::total 94026 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92374 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 92374 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.inst 7124258 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 7124258 # number of demand (read+write) accesses
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-system.cpu1.dcache.overall_accesses::total 7124258 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046270 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.046270 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043701 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.043701 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054910 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054910 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250893 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250893 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045119 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.045119 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045119 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.045119 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15080.033207 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15080.033207 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23996.521681 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 23996.521681 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18174.171993 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18174.171993 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23305.391483 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23305.391483 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 18947.796766 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18947.796766 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 115746 # number of writebacks
-system.cpu1.dcache.writebacks::total 115746 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15462 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 15462 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49475 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 49475 # number of WriteReq MSHR hits
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-system.cpu1.dcache.demand_mshr_hits::total 64937 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64937 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 64937 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166546 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 166546 # number of ReadReq MSHR misses
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-system.cpu1.dcache.WriteReq_mshr_misses::total 89959 # number of WriteReq MSHR misses
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-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5163 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23176 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23176 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256505 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 256505 # number of demand (read+write) MSHR misses
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-system.cpu1.dcache.overall_mshr_misses::total 256505 # number of overall MSHR misses
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-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202025254 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2000006836 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2000006836 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83498750 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83498750 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492542247 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492542247 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 337500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 337500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4202032090 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4202032090 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4202032090 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4202032090 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329591498 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329591498 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202938498 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202938498 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532529996 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532529996 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042339 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042339 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028195 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028195 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054910 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054910 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250893 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250893 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.036004 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.036004 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13221.724052 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13221.724052 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22232.426283 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22232.426283 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16172.525663 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16172.525663 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21252.254358 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21252.254358 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 1582615 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 1137834 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 2120 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 2120 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 115754 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 151048 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 84372 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41116 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 85179 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 76804 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 64396 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787314 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 769072 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6988 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51360 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2614734 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57194048 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24925415 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10728 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93220 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 82223411 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 838592 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 2085067 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.363773 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.481085 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 1326575 63.62% 63.62% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 758492 36.38% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 2085067 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 782771935 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 78513000 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer0.occupancy 1341710719 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 381436893 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 4307996 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer3.occupancy 28057498 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 31012 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31012 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59407 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326658321 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36824131 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36417 # number of replacements
-system.iocache.tags.tagsinuse 0.992209 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 0.992159 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 268855800000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 0.992209 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.062013 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.062013 # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide 0.992159 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.062010 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.062010 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328483 # Number of tag accesses
-system.iocache.tags.data_accesses 328483 # Number of data accesses
+system.iocache.tags.tag_accesses 328467 # Number of tag accesses
+system.iocache.tags.data_accesses 328467 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses
system.iocache.ReadReq_misses::total 243 # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide 35 # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total 35 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses
system.iocache.demand_misses::total 243 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 243 # number of overall misses
system.iocache.overall_misses::total 243 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 31692627 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 31692627 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 31692627 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 31692627 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 31692627 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 31692627 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 31254127 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 31254127 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 31254127 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 31254127 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 31254127 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 31254127 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide 36259 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 36259 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 238091 # Transaction distribution
+system.membus.trans_dist::ReadResp 238091 # Transaction distribution
+system.membus.trans_dist::WriteReq 30933 # Transaction distribution
+system.membus.trans_dist::WriteResp 30933 # Transaction distribution
+system.membus.trans_dist::Writeback 112127 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 79652 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 39985 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 13516 # Transaction distribution
+system.membus.trans_dist::ReadExReq 30363 # Transaction distribution
+system.membus.trans_dist::ReadExResp 13313 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13576 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704934 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 826518 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 899224 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27152 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21038188 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 21229406 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 23548702 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 123399 # Total snoops (count)
+system.membus.snoop_fanout::samples 498406 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 498406 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 498406 # Request fanout histogram
+system.membus.reqLayer0.occupancy 87864494 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 11666999 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1620379248 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer2.occupancy 2120601580 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38542869 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 668340 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 668325 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30933 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30933 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 252536 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 92316 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 40369 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 132685 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 38932 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 38932 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370044 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368770 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1738814 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41959415 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7901735 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 49861150 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 291964 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 1090717 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.033437 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.179774 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 1054247 96.66% 96.66% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36470 3.34% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 1090717 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1589301055 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2361799867 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 804005619 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.852223 # Number of seconds simulated
-sim_ticks 2852222670000 # Number of ticks simulated
-final_tick 2852222670000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.852237 # Number of seconds simulated
+sim_ticks 2852237227000 # Number of ticks simulated
+final_tick 2852237227000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 166317 # Simulator instruction rate (inst/s)
-host_op_rate 201081 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4259610797 # Simulator tick rate (ticks/s)
-host_mem_usage 558772 # Number of bytes of host memory used
-host_seconds 669.60 # Real time elapsed on the host
-sim_insts 111365458 # Number of instructions simulated
-sim_ops 134642914 # Number of ops (including micro ops) simulated
+host_inst_rate 157725 # Simulator instruction rate (inst/s)
+host_op_rate 190692 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4039440180 # Simulator tick rate (ticks/s)
+host_mem_usage 566224 # Number of bytes of host memory used
+host_seconds 706.10 # Real time elapsed on the host
+sim_insts 111368950 # Number of instructions simulated
+sim_ops 134647110 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu.dtb.walker 6208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst 10897572 # Number of bytes read from this memory
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 6464 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 10896868 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10904484 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1667584 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1667584 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5681792 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_read::total 10904868 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1667392 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1667392 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5682816 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8017652 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8018676 # Number of bytes written to this memory
+system.physmem.num_reads::cpu.dtb.walker 97 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst 170794 # Number of read requests responded to by this memory
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 101 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 170783 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 170902 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 88778 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_reads::total 170908 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 88794 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 129383 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 129399 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu.dtb.walker 2177 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 3820710 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 2266 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.itb.walker 67 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 3820483 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3823153 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 584661 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 584661 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1992058 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 812817 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3823268 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 584591 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 584591 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1992407 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.inst 6144 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2811019 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1992058 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 813154 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 2266 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.itb.walker 67 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 3826627 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6634172 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 170902 # Number of read requests accepted
-system.physmem.writeReqs 129383 # Number of write requests accepted
-system.physmem.readBursts 170902 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 129383 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 10927488 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 10240 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8031232 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 10904484 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 8017652 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 160 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_write::realview.ide 812813 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2811364 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1992407 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 2177 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 3826854 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 813150 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6634632 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 170908 # Number of read requests accepted
+system.physmem.writeReqs 129399 # Number of write requests accepted
+system.physmem.readBursts 170908 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 129399 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 10927552 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 10560 # Total number of bytes read from write queue
+system.physmem.bytesWritten 8032256 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 10904868 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 8018676 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 165 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3869 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4593 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 10513 # Per bank write bursts
-system.physmem.perBankRdBursts::1 10240 # Per bank write bursts
-system.physmem.perBankRdBursts::2 10772 # Per bank write bursts
-system.physmem.perBankRdBursts::3 10550 # Per bank write bursts
-system.physmem.perBankRdBursts::4 13501 # Per bank write bursts
-system.physmem.perBankRdBursts::5 10124 # Per bank write bursts
-system.physmem.perBankRdBursts::6 11177 # Per bank write bursts
-system.physmem.perBankRdBursts::7 10891 # Per bank write bursts
-system.physmem.perBankRdBursts::8 10227 # Per bank write bursts
-system.physmem.perBankRdBursts::9 10892 # Per bank write bursts
-system.physmem.perBankRdBursts::10 10093 # Per bank write bursts
-system.physmem.perBankRdBursts::11 9609 # Per bank write bursts
-system.physmem.perBankRdBursts::12 10331 # Per bank write bursts
-system.physmem.perBankRdBursts::13 11217 # Per bank write bursts
-system.physmem.perBankRdBursts::14 10288 # Per bank write bursts
-system.physmem.perBankRdBursts::15 10317 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 4597 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 10514 # Per bank write bursts
+system.physmem.perBankRdBursts::1 10246 # Per bank write bursts
+system.physmem.perBankRdBursts::2 10769 # Per bank write bursts
+system.physmem.perBankRdBursts::3 10552 # Per bank write bursts
+system.physmem.perBankRdBursts::4 13499 # Per bank write bursts
+system.physmem.perBankRdBursts::5 10126 # Per bank write bursts
+system.physmem.perBankRdBursts::6 11178 # Per bank write bursts
+system.physmem.perBankRdBursts::7 10889 # Per bank write bursts
+system.physmem.perBankRdBursts::8 10228 # Per bank write bursts
+system.physmem.perBankRdBursts::9 10887 # Per bank write bursts
+system.physmem.perBankRdBursts::10 10100 # Per bank write bursts
+system.physmem.perBankRdBursts::11 9610 # Per bank write bursts
+system.physmem.perBankRdBursts::12 10315 # Per bank write bursts
+system.physmem.perBankRdBursts::13 11222 # Per bank write bursts
+system.physmem.perBankRdBursts::14 10292 # Per bank write bursts
+system.physmem.perBankRdBursts::15 10316 # Per bank write bursts
system.physmem.perBankWrBursts::0 7730 # Per bank write bursts
-system.physmem.perBankWrBursts::1 7662 # Per bank write bursts
-system.physmem.perBankWrBursts::2 8408 # Per bank write bursts
-system.physmem.perBankWrBursts::3 8127 # Per bank write bursts
-system.physmem.perBankWrBursts::4 7860 # Per bank write bursts
+system.physmem.perBankWrBursts::1 7667 # Per bank write bursts
+system.physmem.perBankWrBursts::2 8410 # Per bank write bursts
+system.physmem.perBankWrBursts::3 8128 # Per bank write bursts
+system.physmem.perBankWrBursts::4 7856 # Per bank write bursts
system.physmem.perBankWrBursts::5 7340 # Per bank write bursts
-system.physmem.perBankWrBursts::6 8206 # Per bank write bursts
-system.physmem.perBankWrBursts::7 8039 # Per bank write bursts
-system.physmem.perBankWrBursts::8 7784 # Per bank write bursts
-system.physmem.perBankWrBursts::9 8077 # Per bank write bursts
-system.physmem.perBankWrBursts::10 7518 # Per bank write bursts
+system.physmem.perBankWrBursts::6 8209 # Per bank write bursts
+system.physmem.perBankWrBursts::7 8042 # Per bank write bursts
+system.physmem.perBankWrBursts::8 7786 # Per bank write bursts
+system.physmem.perBankWrBursts::9 8073 # Per bank write bursts
+system.physmem.perBankWrBursts::10 7525 # Per bank write bursts
system.physmem.perBankWrBursts::11 7421 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7767 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8402 # Per bank write bursts
-system.physmem.perBankWrBursts::14 7544 # Per bank write bursts
+system.physmem.perBankWrBursts::12 7760 # Per bank write bursts
+system.physmem.perBankWrBursts::13 8405 # Per bank write bursts
+system.physmem.perBankWrBursts::14 7549 # Per bank write bursts
system.physmem.perBankWrBursts::15 7603 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
-system.physmem.totGap 2852222186000 # Total gap between requests
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+system.physmem.totGap 2852236741500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 541 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.bytesPerActivate::mean 311.666217 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 184.364711 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.290387 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 22259 36.59% 36.59% # Bytes accessed per row activation
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-system.physmem.bytesPerActivate::256-383 6771 11.13% 71.42% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3560 5.85% 77.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2627 4.32% 81.59% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1563 2.57% 84.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1081 1.78% 85.94% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1081 1.78% 87.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7471 12.28% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 60830 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6311 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 27.051339 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 576.967682 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6309 99.97% 99.97% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6311 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6311 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.884012 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.375867 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 11.802704 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::96-99 7 0.11% 99.64% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::total 6311 # Writes before turning the bus around for reads
-system.physmem.totQLat 1715938250 # Total ticks spent queuing
-system.physmem.totMemAccLat 4917350750 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 853710000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 10049.89 # Average queueing delay per DRAM burst
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+system.physmem.wrPerTurnAround::total 6321 # Writes before turning the bus around for reads
+system.physmem.totQLat 1722371500 # Total ticks spent queuing
+system.physmem.totMemAccLat 4923802750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 853715000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 10087.51 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 28799.89 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 28837.51 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.83 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.82 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.82 # Average system read bandwidth in MiByte/s
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 23.21 # Average write queue length when enqueuing
-system.physmem.readRowHits 140944 # Number of row buffer hits during reads
-system.physmem.writeRowHits 94455 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 26.39 # Average write queue length when enqueuing
+system.physmem.readRowHits 140948 # Number of row buffer hits during reads
+system.physmem.writeRowHits 94469 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes
-system.physmem.avgGap 9498383.82 # Average gap between requests
+system.physmem.writeRowHitRate 75.26 # Row buffer hit rate for writes
+system.physmem.avgGap 9497736.45 # Average gap between requests
system.physmem.pageHitRate 79.46 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2712510439500 # Time in different power states
-system.physmem.memoryStateTime::REF 95241900000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2712717626000 # Time in different power states
+system.physmem.memoryStateTime::REF 95242420000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 44470242000 # Time in different power states
+system.physmem.memoryStateTime::ACT 44277091000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 234798480 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 225076320 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 128114250 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 122809500 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 684590400 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 647189400 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 410650560 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 402511680 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 186293156400 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 186293156400 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 83147145165 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 82654300080 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1638396165000 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1638828485250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1909294620255 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1909173528630 # Total energy per rank (pJ)
-system.physmem.averagePower::0 669.406404 # Core power per rank (mW)
-system.physmem.averagePower::1 669.363949 # Core power per rank (mW)
+system.physmem.actEnergy::0 234707760 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 225159480 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 128064750 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 122854875 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 684629400 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 647158200 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 410715360 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 402550560 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 186294173520 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 186294173520 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 83068916085 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 82611072135 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1638474130500 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1638875748000 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1909295337375 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1909178716770 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.403001 # Core power per rank (mW)
+system.physmem.averagePower::1 669.362113 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 157 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 157 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 157 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 71842 # Transaction distribution
-system.membus.trans_dist::ReadResp 71842 # Transaction distribution
-system.membus.trans_dist::WriteReq 27607 # Transaction distribution
-system.membus.trans_dist::WriteResp 27607 # Transaction distribution
-system.membus.trans_dist::Writeback 88778 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4591 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4593 # Transaction distribution
-system.membus.trans_dist::ReadExReq 129869 # Transaction distribution
-system.membus.trans_dist::ReadExResp 129869 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448500 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556132 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 628829 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16602840 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16766621 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19085917 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 219 # Total snoops (count)
-system.membus.snoop_fanout::samples 297178 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 297178 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 297178 # Request fanout histogram
-system.membus.reqLayer0.occupancy 87065000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1712000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1386132250 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1718569157 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer3.occupancy 38335749 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 326584849 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36809251 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 30769128 # Number of BP lookups
-system.cpu.branchPred.condPredicted 16730733 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 2480939 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 18423796 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 13205412 # Number of BTB hits
+system.cpu.branchPred.lookups 30773662 # Number of BP lookups
+system.cpu.branchPred.condPredicted 16735793 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 2481146 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 18414792 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 13204104 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 71.675848 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 7765211 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 1476374 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 71.703791 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 7765871 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 1476448 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 24572928 # DTB read hits
-system.cpu.dtb.read_misses 58429 # DTB read misses
-system.cpu.dtb.write_hits 19368405 # DTB write hits
-system.cpu.dtb.write_misses 5913 # DTB write misses
+system.cpu.dtb.read_hits 24574985 # DTB read hits
+system.cpu.dtb.read_misses 58557 # DTB read misses
+system.cpu.dtb.write_hits 19368965 # DTB write hits
+system.cpu.dtb.write_misses 5915 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4349 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 1245 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 1816 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 4353 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 1231 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 1821 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 752 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 24631357 # DTB read accesses
-system.cpu.dtb.write_accesses 19374318 # DTB write accesses
+system.cpu.dtb.perms_faults 755 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 24633542 # DTB read accesses
+system.cpu.dtb.write_accesses 19374880 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 43941333 # DTB hits
-system.cpu.dtb.misses 64342 # DTB misses
-system.cpu.dtb.accesses 44005675 # DTB accesses
+system.cpu.dtb.hits 43943950 # DTB hits
+system.cpu.dtb.misses 64472 # DTB misses
+system.cpu.dtb.accesses 44008422 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 57038768 # ITB inst hits
-system.cpu.itb.inst_misses 5411 # ITB inst misses
+system.cpu.itb.inst_hits 57039019 # ITB inst hits
+system.cpu.itb.inst_misses 5418 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
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system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
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system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching
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-system.cpu.ipc 0.355405 # IPC: instructions per cycle
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
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system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu.toL2Bus.trans_dist::ReadReq 3575187 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3575091 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 697424 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36234 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::ReadExResp 295755 # Transaction distribution
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-system.cpu.toL2Bus.snoops 60174 # Total snoops (count)
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-system.cpu.toL2Bus.snoop_fanout::mean 5.007974 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.088941 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 4536814 99.20% 99.20% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 36468 0.80% 100.00% # Request fanout histogram
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-system.cpu.toL2Bus.respLayer2.occupancy 10501000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 86895250 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
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system.cpu.l2cache.tags.warmup_cycle 93462601500 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022478 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015921 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015921 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017842 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017842 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.019595 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019595 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.019595 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12796.950774 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12796.950774 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37736.512818 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37736.512818 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12182.758206 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12182.758206 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 24499 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21705.923644 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21705.923644 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 3576313 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3576217 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 697938 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2821 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2823 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 295804 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 295804 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5802238 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2505111 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15298 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 156293 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8478940 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185670592 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98744797 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19124 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 276596 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 284711109 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 60360 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4574965 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.007969 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.088914 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 4538506 99.20% 99.20% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 36459 0.80% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 4574965 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 3011909666 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 4357140777 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 1340495452 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 10517000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 87146500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36804753 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36424 # number of replacements
-system.iocache.tags.tagsinuse 1.031475 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 1.031563 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 269946820000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 1.031475 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.064467 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.064467 # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide 1.031563 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.064473 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.064473 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.demand_misses::total 234 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 234 # number of overall misses
system.iocache.overall_misses::total 234 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 27954377 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 27954377 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 27954377 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 27954377 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 27954377 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 27954377 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 27956377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 27956377 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 27956377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 27956377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 27956377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 27956377 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses)
system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 119463.149573 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119463.149573 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 119463.149573 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 119463.149573 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 119463.149573 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119471.696581 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119471.696581 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::realview.ide 119471.696581 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 119471.696581 # average overall miss latency
+system.iocache.overall_avg_miss_latency::realview.ide 119471.696581 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 119471.696581 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 15785377 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 15785377 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2212496723 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2212496723 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::realview.ide 15785377 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 15785377 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::realview.ide 15785377 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 15785377 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::realview.ide 15787377 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 15787377 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2211427725 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2211427725 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::realview.ide 15787377 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 15787377 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::realview.ide 15787377 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 15787377 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67458.876068 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67458.876068 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67467.423077 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67467.423077 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 67458.876068 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 67458.876068 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67467.423077 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67467.423077 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67467.423077 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67467.423077 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 71836 # Transaction distribution
+system.membus.trans_dist::ReadResp 71836 # Transaction distribution
+system.membus.trans_dist::WriteReq 27607 # Transaction distribution
+system.membus.trans_dist::WriteResp 27607 # Transaction distribution
+system.membus.trans_dist::Writeback 88794 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4595 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4597 # Transaction distribution
+system.membus.trans_dist::ReadExReq 129881 # Transaction distribution
+system.membus.trans_dist::ReadExResp 129881 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 448536 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 556168 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 628865 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16604248 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16768029 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19087325 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 219 # Total snoops (count)
+system.membus.snoop_fanout::samples 297195 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 297195 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 297195 # Request fanout histogram
+system.membus.reqLayer0.occupancy 87032500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 1706500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1386266250 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1718628403 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38334247 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
sim_ticks 2826844351500 # Number of ticks simulated
final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 73855 # Simulator instruction rate (inst/s)
-host_op_rate 89582 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1844239732 # Simulator tick rate (ticks/s)
-host_mem_usage 559768 # Number of bytes of host memory used
-host_seconds 1532.80 # Real time elapsed on the host
-sim_insts 113205077 # Number of instructions simulated
-sim_ops 137311743 # Number of ops (including micro ops) simulated
+host_inst_rate 74392 # Simulator instruction rate (inst/s)
+host_op_rate 90233 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1857645684 # Simulator tick rate (ticks/s)
+host_mem_usage 566256 # Number of bytes of host memory used
+host_seconds 1521.74 # Real time elapsed on the host
+sim_insts 113204796 # Number of instructions simulated
+sim_ops 137311416 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 172165 # Number of read requests accepted
system.physmem.writeReqs 131231 # Number of write requests accepted
system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11009344 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM 11009408 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue
system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10989 # Per bank write bursts
system.physmem.perBankRdBursts::6 11171 # Per bank write bursts
system.physmem.perBankRdBursts::7 11539 # Per bank write bursts
system.physmem.perBankRdBursts::8 10356 # Per bank write bursts
-system.physmem.perBankRdBursts::9 11055 # Per bank write bursts
+system.physmem.perBankRdBursts::9 11056 # Per bank write bursts
system.physmem.perBankRdBursts::10 10496 # Per bank write bursts
system.physmem.perBankRdBursts::11 9259 # Per bank write bursts
system.physmem.perBankRdBursts::12 10183 # Per bank write bursts
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 126850 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 151967 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 16017 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 151969 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 16016 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2547 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5742 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6541 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 7276 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7533 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 8094 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1968 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2544 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5739 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6276 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6540 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7277 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7536 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 8095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 9475 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8903 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8389 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7979 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7945 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6915 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 9476 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 8902 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 8388 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 7977 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 7946 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6912 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6631 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 6632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 136 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 149 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 62143 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 308.305682 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 180.941865 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.713467 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 23390 37.64% 37.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14779 23.78% 61.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 62147 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 308.286868 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 180.931959 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 329.707872 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 23391 37.64% 37.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 14782 23.79% 61.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3678 5.92% 77.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2603 4.19% 81.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3679 5.92% 77.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2602 4.19% 81.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1126 1.81% 86.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1131 1.82% 87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7554 12.16% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 62143 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6421 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 26.789285 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 556.595179 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6419 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::768-895 1126 1.81% 86.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1130 1.82% 87.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7555 12.16% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 62147 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6420 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 26.793614 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 556.638433 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6418 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6421 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6421 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.831802 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.368831 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 11.481886 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5612 87.40% 87.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 55 0.86% 88.26% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 6420 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6420 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.834891 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.369444 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.492928 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5612 87.41% 87.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 54 0.84% 88.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 14 0.22% 95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 15 0.23% 96.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 17 0.26% 96.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 4 0.06% 96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 3 0.05% 96.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 5 0.08% 96.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 166 2.59% 99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 13 0.20% 95.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 15 0.23% 96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 17 0.26% 96.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 4 0.06% 96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 3 0.05% 96.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 5 0.08% 96.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 167 2.60% 99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6421 # Writes before turning the bus around for reads
-system.physmem.totQLat 2071957750 # Total ticks spent queuing
-system.physmem.totMemAccLat 5297351500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 860105000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12044.80 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 6420 # Writes before turning the bus around for reads
+system.physmem.totQLat 2072280000 # Total ticks spent queuing
+system.physmem.totMemAccLat 5297692500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 860110000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12046.60 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30794.80 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 30796.60 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing
-system.physmem.readRowHits 141999 # Number of row buffer hits during reads
-system.physmem.writeRowHits 95218 # Number of row buffer hits during writes
+system.physmem.readRowHits 142002 # Number of row buffer hits during reads
+system.physmem.writeRowHits 95212 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes
system.physmem.avgGap 9317341.50 # Average gap between requests
-system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2694663327000 # Time in different power states
+system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2694665773000 # Time in different power states
system.physmem.memoryStateTime::REF 94394300000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 37786710500 # Time in different power states
+system.physmem.memoryStateTime::ACT 37784264500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 245972160 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 134211000 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ)
+system.physmem.actEnergy::0 245987280 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 223844040 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 134219250 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 122137125 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 638843400 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 638851200 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 80261886105 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 79073133435 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1625697180750 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1626739946250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1892103680775 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1891832027520 # Total energy per rank (pJ)
-system.physmem.averagePower::0 669.335912 # Core power per rank (mW)
-system.physmem.averagePower::1 669.239814 # Core power per rank (mW)
+system.physmem.actBackEnergy::0 80264555415 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 79079779350 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1625694839250 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1626734116500 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1892104031955 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1891832874855 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.336036 # Core power per rank (mW)
+system.physmem.averagePower::1 669.240113 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 67834 # Transaction distribution
-system.membus.trans_dist::ReadResp 67833 # Transaction distribution
-system.membus.trans_dist::WriteReq 27608 # Transaction distribution
-system.membus.trans_dist::WriteResp 27608 # Transaction distribution
-system.membus.trans_dist::Writeback 90626 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution
-system.membus.trans_dist::ReadExReq 135127 # Transaction distribution
-system.membus.trans_dist::ReadExResp 135127 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 205 # Total snoops (count)
-system.membus.snoop_fanout::samples 300222 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 300222 # Request fanout histogram
-system.membus.reqLayer0.occupancy 94199000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1696000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1357979249 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1678023705 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 46964481 # Number of BP lookups
-system.cpu.branchPred.condPredicted 24050206 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1232756 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 29560774 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 21375284 # Number of BTB hits
+system.cpu.branchPred.lookups 46964274 # Number of BP lookups
+system.cpu.branchPred.condPredicted 24050124 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1232745 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 29560624 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 21375180 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.309622 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 11765183 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 72.309637 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 11765118 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
-system.cpu.checker.dtb.read_hits 24601451 # DTB read hits
+system.cpu.checker.dtb.read_hits 24601402 # DTB read hits
system.cpu.checker.dtb.read_misses 8241 # DTB read misses
-system.cpu.checker.dtb.write_hits 19645361 # DTB write hits
+system.cpu.checker.dtb.write_hits 19645330 # DTB write hits
system.cpu.checker.dtb.write_misses 1441 # DTB write misses
system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.checker.dtb.prefetch_faults 1773 # Number of TLB faults due to prefetch
system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
-system.cpu.checker.dtb.read_accesses 24609692 # DTB read accesses
-system.cpu.checker.dtb.write_accesses 19646802 # DTB write accesses
+system.cpu.checker.dtb.read_accesses 24609643 # DTB read accesses
+system.cpu.checker.dtb.write_accesses 19646771 # DTB write accesses
system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.checker.dtb.hits 44246812 # DTB hits
+system.cpu.checker.dtb.hits 44246732 # DTB hits
system.cpu.checker.dtb.misses 9682 # DTB misses
-system.cpu.checker.dtb.accesses 44256494 # DTB accesses
+system.cpu.checker.dtb.accesses 44256414 # DTB accesses
system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.checker.itb.inst_hits 115909457 # ITB inst hits
+system.cpu.checker.itb.inst_hits 115909165 # ITB inst hits
system.cpu.checker.itb.inst_misses 4826 # ITB inst misses
system.cpu.checker.itb.read_hits 0 # DTB read hits
system.cpu.checker.itb.read_misses 0 # DTB read misses
system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.checker.itb.read_accesses 0 # DTB read accesses
system.cpu.checker.itb.write_accesses 0 # DTB write accesses
-system.cpu.checker.itb.inst_accesses 115914283 # ITB inst accesses
-system.cpu.checker.itb.hits 115909457 # DTB hits
+system.cpu.checker.itb.inst_accesses 115913991 # ITB inst accesses
+system.cpu.checker.itb.hits 115909165 # DTB hits
system.cpu.checker.itb.misses 4826 # DTB misses
-system.cpu.checker.itb.accesses 115914283 # DTB accesses
-system.cpu.checker.numCycles 139168167 # number of cpu cycles simulated
+system.cpu.checker.itb.accesses 115913991 # DTB accesses
+system.cpu.checker.numCycles 139167829 # number of cpu cycles simulated
system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25471928 # DTB read hits
-system.cpu.dtb.read_misses 60410 # DTB read misses
-system.cpu.dtb.write_hits 19919780 # DTB write hits
+system.cpu.dtb.read_hits 25471879 # DTB read hits
+system.cpu.dtb.read_misses 60408 # DTB read misses
+system.cpu.dtb.write_hits 19919747 # DTB write hits
system.cpu.dtb.write_misses 9388 # DTB write misses
system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA
system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25532338 # DTB read accesses
-system.cpu.dtb.write_accesses 19929168 # DTB write accesses
+system.cpu.dtb.read_accesses 25532287 # DTB read accesses
+system.cpu.dtb.write_accesses 19929135 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 45391708 # DTB hits
-system.cpu.dtb.misses 69798 # DTB misses
-system.cpu.dtb.accesses 45461506 # DTB accesses
+system.cpu.dtb.hits 45391626 # DTB hits
+system.cpu.dtb.misses 69796 # DTB misses
+system.cpu.dtb.accesses 45461422 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 66240861 # ITB inst hits
+system.cpu.itb.inst_hits 66240582 # ITB inst hits
system.cpu.itb.inst_misses 11936 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 66252797 # ITB inst accesses
-system.cpu.itb.hits 66240861 # DTB hits
+system.cpu.itb.inst_accesses 66252518 # ITB inst accesses
+system.cpu.itb.hits 66240582 # DTB hits
system.cpu.itb.misses 11936 # DTB misses
-system.cpu.itb.accesses 66252797 # DTB accesses
-system.cpu.numCycles 260549216 # number of cpu cycles simulated
+system.cpu.itb.accesses 66252518 # DTB accesses
+system.cpu.numCycles 260548868 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 104910072 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 184559148 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 46964481 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 33140467 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 145575314 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6162280 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 104909639 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 184558460 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 46964274 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33140298 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 145575332 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6162234 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 66241173 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1039454 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.CacheLines 66240894 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 254585789 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.884455 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 254585351 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.884453 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 155338785 61.02% 61.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 29243956 11.49% 72.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 14083385 5.53% 78.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 55919663 21.96% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 155338707 61.02% 61.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 29243843 11.49% 72.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 14083345 5.53% 78.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55919456 21.96% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 254585789 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.180252 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.708347 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 78109166 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 105363541 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 64680872 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3828813 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2603397 # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total 254585351 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.180251 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.708345 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 78108823 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 105363724 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 64680632 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3828797 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2603375 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 485997 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 157495514 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3691335 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2603397 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 83950162 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 10012692 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 74490237 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 62673576 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 20855725 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 146846377 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 950168 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 437835 # Number of times rename has blocked due to ROB full
+system.cpu.decode.BranchMispred 485996 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 157495015 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3691306 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2603375 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 83949795 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 10013130 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 74489960 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 62673363 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 20855728 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 146845952 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 950144 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 437842 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 18093431 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 150531293 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 678956016 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 164473250 # Number of integer rename lookups
+system.cpu.rename.SQFullEvents 18093439 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 150530803 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 678954009 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 164472740 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 141875837 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 8655453 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2847783 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2651540 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13851138 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26418180 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 21304101 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1686584 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2099607 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 143580968 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.CommittedMaps 141875467 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 8655333 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2847772 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2651529 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13851116 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26418132 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 21304063 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1686589 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2099460 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 143580575 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 143376402 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 269122 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6250831 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14651334 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 143376028 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 269119 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6250781 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14651223 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 254585789 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 254585351 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 166208039 65.29% 65.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 45306668 17.80% 83.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 31957154 12.55% 95.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 10300319 4.05% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 813576 0.32% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 166207835 65.29% 65.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 45306594 17.80% 83.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 31956972 12.55% 95.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 10300343 4.05% 99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 813574 0.32% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 254585789 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 254585351 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 7371881 32.63% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 7371879 32.63% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5631992 24.93% 57.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 9586808 42.44% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5632028 24.93% 57.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 9586948 42.44% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 96038375 66.98% 66.99% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 113990 0.08% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 96038086 66.98% 66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 113978 0.08% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26201034 18.27% 85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21012076 14.66% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26200986 18.27% 85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21012051 14.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 143376402 # Type of FU issued
+system.cpu.iq.FU_type_0::total 143376028 # Type of FU issued
system.cpu.iq.rate 0.550285 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 22590713 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.157562 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 564162773 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 151957708 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 140260829 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_cnt 22590887 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.157564 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 564161758 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 151957264 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 140260479 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 165941427 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 165941227 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 324400 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 324401 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18272 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 701019 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18271 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 701002 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2603397 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 948146 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 290514 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 145902754 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 2603375 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 948323 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 290944 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 145902361 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26418180 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 21304101 # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts 26418132 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 21304063 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 255642 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18272 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 317514 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 471623 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 789137 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 142433961 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25800026 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 872747 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewLSQFullEvents 256072 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18271 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 317509 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 471618 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 789127 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 142433599 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25799978 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 872737 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 200927 # number of nop insts executed
-system.cpu.iew.exec_refs 46682620 # number of memory reference insts executed
-system.cpu.iew.exec_branches 26544157 # Number of branches executed
-system.cpu.iew.exec_stores 20882594 # Number of stores executed
+system.cpu.iew.exec_refs 46682549 # number of memory reference insts executed
+system.cpu.iew.exec_branches 26544085 # Number of branches executed
+system.cpu.iew.exec_stores 20882571 # Number of stores executed
system.cpu.iew.exec_rate 0.546668 # Inst execution rate
-system.cpu.iew.wb_sent 142046877 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 140272260 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 63301722 # num instructions producing a value
-system.cpu.iew.wb_consumers 95887432 # num instructions consuming a value
+system.cpu.iew.wb_sent 142046516 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 140271910 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 63301578 # num instructions producing a value
+system.cpu.iew.wb_consumers 95887209 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 7592023 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 7591975 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 755013 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 251649482 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 755003 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 251649065 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.145558 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.145555 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 178084591 70.77% 70.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 43398091 17.25% 88.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 15481937 6.15% 94.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4357709 1.73% 95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 178084267 70.77% 70.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 43398054 17.25% 88.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 15481884 6.15% 94.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 4357721 1.73% 95.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1589348 0.63% 99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 777595 0.31% 99.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 414354 0.16% 99.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1083835 0.43% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1589357 0.63% 99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 777637 0.31% 99.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 414343 0.16% 99.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1083780 0.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 251649482 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 113359982 # Number of instructions committed
-system.cpu.commit.committedOps 137466648 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 251649065 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 113359701 # Number of instructions committed
+system.cpu.commit.committedOps 137466321 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 45531388 # Number of memory references committed
-system.cpu.commit.loads 24928306 # Number of loads committed
+system.cpu.commit.refs 45531319 # Number of memory references committed
+system.cpu.commit.loads 24928258 # Number of loads committed
system.cpu.commit.membars 814674 # Number of memory barriers committed
-system.cpu.commit.branches 26060542 # Number of branches committed
+system.cpu.commit.branches 26060472 # Number of branches committed
system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 120282409 # Number of committed integer instructions.
-system.cpu.commit.function_calls 4896404 # Number of function calls committed.
+system.cpu.commit.int_insts 120282111 # Number of committed integer instructions.
+system.cpu.commit.function_calls 4896381 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 91813673 66.79% 66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 112998 0.08% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 91813423 66.79% 66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 24928306 18.13% 85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 20603082 14.99% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 24928258 18.13% 85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 20603061 14.99% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 137466648 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1083835 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 137466321 # Class of committed instruction
+system.cpu.commit.bw_lim_events 1083780 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 373371044 # The number of ROB reads
-system.cpu.rob.rob_writes 293051212 # The number of ROB writes
-system.cpu.timesIdled 892832 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 5963427 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 5393139488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 113205077 # Number of Instructions Simulated
-system.cpu.committedOps 137311743 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.301568 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.301568 # CPI: Total CPI of All Threads
+system.cpu.rob.rob_reads 373370450 # The number of ROB reads
+system.cpu.rob.rob_writes 293050441 # The number of ROB writes
+system.cpu.timesIdled 892831 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5963517 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 5393139836 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 113204796 # Number of Instructions Simulated
+system.cpu.committedOps 137311416 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 2.301571 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.301571 # CPI: Total CPI of All Threads
system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 155870959 # number of integer regfile reads
-system.cpu.int_regfile_writes 88663006 # number of integer regfile writes
+system.cpu.int_regfile_reads 155870535 # number of integer regfile reads
+system.cpu.int_regfile_writes 88662744 # number of integer regfile writes
system.cpu.fp_regfile_reads 9591 # number of floating regfile reads
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
-system.cpu.cc_regfile_reads 503160198 # number of cc regfile reads
-system.cpu.cc_regfile_writes 53196607 # number of cc regfile writes
-system.cpu.misc_regfile_reads 444137179 # number of misc regfile reads
+system.cpu.cc_regfile_reads 503158962 # number of cc regfile reads
+system.cpu.cc_regfile_writes 53196475 # number of cc regfile writes
+system.cpu.misc_regfile_reads 444136009 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq 2564960 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2564895 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 695414 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795107 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495169 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128721 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 6450177 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298256 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349665 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215436 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 219910025 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 65488 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3561861 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 9.010233 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::9 3525412 98.98% 98.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::10 36449 1.02% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3561861 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 2502933529 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2849443906 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1334434109 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 74884707 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 1894038 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 64256715 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1894550 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 33.916611 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.998777 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id
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-system.cpu.dcache.overall_avg_miss_latency::total 32591.645718 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 503676 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.701501 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 695414 # number of writebacks
-system.cpu.dcache.writebacks::total 695414 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286306 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 286306 # number of ReadReq MSHR hits
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-system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3560912 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3560912 # number of demand (read+write) MSHR hits
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-system.cpu.dcache.overall_mshr_hits::total 3560912 # number of overall MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses::total 414156 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses
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-system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses
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-system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 713418 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_misses::cpu.data 832724 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 832724 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5342017166 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5342017166 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883030705 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883030705 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479647251 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479647251 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225047871 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 17225047871 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18704695122 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 18704695122 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792723750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792723750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457953 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457953 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233181703 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233181703 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.562778 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.562778 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39707.783497 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39707.783497 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12402.119349 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12402.119349 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24144.397634 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24144.397634 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.058404 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.058404 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 2564949 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2564884 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 695413 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795093 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495164 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128717 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 6450154 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121297808 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349473 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215428 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 219909377 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 65488 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3561849 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 9.010233 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::9 3525400 98.98% 98.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::10 36449 1.02% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3561849 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2502926529 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 2849434655 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 1334430859 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 74882707 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36410 # number of replacements
system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 67834 # Transaction distribution
+system.membus.trans_dist::ReadResp 67833 # Transaction distribution
+system.membus.trans_dist::WriteReq 27608 # Transaction distribution
+system.membus.trans_dist::WriteResp 27608 # Transaction distribution
+system.membus.trans_dist::Writeback 90626 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution
+system.membus.trans_dist::ReadExReq 135127 # Transaction distribution
+system.membus.trans_dist::ReadExResp 135127 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 205 # Total snoops (count)
+system.membus.snoop_fanout::samples 300222 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 300222 # Request fanout histogram
+system.membus.reqLayer0.occupancy 94200000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 1697000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1357984749 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1678025205 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 2.824341 # Number of seconds simulated
-sim_ticks 2824340874000 # Number of ticks simulated
-final_tick 2824340874000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.824366 # Number of seconds simulated
+sim_ticks 2824365837500 # Number of ticks simulated
+final_tick 2824365837500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 96866 # Simulator instruction rate (inst/s)
-host_op_rate 117519 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2277239721 # Simulator tick rate (ticks/s)
-host_mem_usage 609056 # Number of bytes of host memory used
-host_seconds 1240.25 # Real time elapsed on the host
-sim_insts 120137719 # Number of instructions simulated
-sim_ops 145752951 # Number of ops (including micro ops) simulated
+host_inst_rate 90810 # Simulator instruction rate (inst/s)
+host_op_rate 110172 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2134851185 # Simulator tick rate (ticks/s)
+host_mem_usage 669748 # Number of bytes of host memory used
+host_seconds 1322.98 # Real time elapsed on the host
+sim_insts 120140086 # Number of instructions simulated
+sim_ops 145755972 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 2176 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 512 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 286816 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 1046908 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 10513536 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 286496 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 1047804 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 10514048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 31952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 549344 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 1344384 # Number of bytes read from this memory
-system.physmem.bytes_read::total 13777356 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 286816 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 31952 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 318768 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7262336 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 32208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 549728 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 1343808 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 13778252 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 286496 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 32208 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 318704 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7259968 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9598416 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9596048 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 34 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 8 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 6727 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 16883 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 164274 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 6722 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 16897 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 164282 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 566 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8607 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 21006 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 218132 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 113474 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 570 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 8613 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 20997 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 218146 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 113437 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 154134 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 154097 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 770 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 181 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 101551 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 370673 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 3722474 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 113 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 101437 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 370987 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 3722623 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 227 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 11313 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 194503 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 475999 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4878078 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 101551 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 11313 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 112865 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2571338 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 820841 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 11404 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 194638 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 475791 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4878352 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 101437 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 11404 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 112841 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2570477 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6268 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3398462 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2571338 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 821181 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 820834 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3397594 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2570477 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 770 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 181 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 101551 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 376942 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 3722474 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 113 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 101437 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 377256 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 3722623 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 227 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 11313 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 194518 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 475999 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 8276541 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 218132 # Number of read requests accepted
-system.physmem.writeReqs 154134 # Number of write requests accepted
-system.physmem.readBursts 218132 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 154134 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 13944832 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue
-system.physmem.bytesWritten 9612032 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 13777356 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 9598416 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue
+system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 11404 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 194652 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.l2cache.prefetcher 475791 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 821174 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 8275946 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 218146 # Number of read requests accepted
+system.physmem.writeReqs 154097 # Number of write requests accepted
+system.physmem.readBursts 218146 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 154097 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 13946112 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 15232 # Total number of bytes read from write queue
+system.physmem.bytesWritten 9610368 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 13778252 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 9596048 # Total written bytes from the system interface side
+system.physmem.servicedByWrQ 238 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 13729 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 13731 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 13753 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 13737 # Per bank write bursts
system.physmem.perBankRdBursts::1 13637 # Per bank write bursts
-system.physmem.perBankRdBursts::2 14382 # Per bank write bursts
-system.physmem.perBankRdBursts::3 14282 # Per bank write bursts
-system.physmem.perBankRdBursts::4 15946 # Per bank write bursts
-system.physmem.perBankRdBursts::5 13017 # Per bank write bursts
-system.physmem.perBankRdBursts::6 13909 # Per bank write bursts
-system.physmem.perBankRdBursts::7 13917 # Per bank write bursts
-system.physmem.perBankRdBursts::8 13612 # Per bank write bursts
-system.physmem.perBankRdBursts::9 13371 # Per bank write bursts
-system.physmem.perBankRdBursts::10 12787 # Per bank write bursts
-system.physmem.perBankRdBursts::11 11726 # Per bank write bursts
-system.physmem.perBankRdBursts::12 13349 # Per bank write bursts
-system.physmem.perBankRdBursts::13 14174 # Per bank write bursts
-system.physmem.perBankRdBursts::14 13344 # Per bank write bursts
-system.physmem.perBankRdBursts::15 12704 # Per bank write bursts
-system.physmem.perBankWrBursts::0 9692 # Per bank write bursts
-system.physmem.perBankWrBursts::1 9790 # Per bank write bursts
-system.physmem.perBankWrBursts::2 10299 # Per bank write bursts
-system.physmem.perBankWrBursts::3 9942 # Per bank write bursts
-system.physmem.perBankWrBursts::4 9060 # Per bank write bursts
-system.physmem.perBankWrBursts::5 9040 # Per bank write bursts
-system.physmem.perBankWrBursts::6 9465 # Per bank write bursts
-system.physmem.perBankWrBursts::7 9428 # Per bank write bursts
+system.physmem.perBankRdBursts::2 14389 # Per bank write bursts
+system.physmem.perBankRdBursts::3 14286 # Per bank write bursts
+system.physmem.perBankRdBursts::4 15951 # Per bank write bursts
+system.physmem.perBankRdBursts::5 13008 # Per bank write bursts
+system.physmem.perBankRdBursts::6 13922 # Per bank write bursts
+system.physmem.perBankRdBursts::7 13905 # Per bank write bursts
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system.physmem.bytesPerActivate::1024-1151 8937 9.63% 100.00% # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::76-79 4 0.05% 99.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 13 0.17% 99.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.01% 99.67% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.01% 99.68% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 6 0.08% 99.76% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 2 0.03% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::108-111 2 0.03% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 2 0.03% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 3 0.04% 99.88% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 7 0.09% 99.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 1 0.01% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 7530 # Writes before turning the bus around for reads
+system.physmem.totQLat 8946488000 # Total ticks spent queuing
+system.physmem.totMemAccLat 13032263000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1089540000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 41056.26 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 59629.63 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 59806.26 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.94 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.40 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.88 # Average system read bandwidth in MiByte/s
system.physmem.busUtil 0.07 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.59 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 21.20 # Average write queue length when enqueuing
-system.physmem.readRowHits 185267 # Number of row buffer hits during reads
-system.physmem.writeRowHits 90008 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.03 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 59.92 # Row buffer hit rate for writes
-system.physmem.avgGap 7586884.90 # Average gap between requests
-system.physmem.pageHitRate 74.78 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2697410352000 # Time in different power states
-system.physmem.memoryStateTime::REF 94310840000 # Time in different power states
+system.physmem.avgRdQLen 1.56 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 23.08 # Average write queue length when enqueuing
+system.physmem.readRowHits 185273 # Number of row buffer hits during reads
+system.physmem.writeRowHits 89950 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 85.02 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 59.89 # Row buffer hit rate for writes
+system.physmem.avgGap 7587422.14 # Average gap between requests
+system.physmem.pageHitRate 74.77 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2697372741500 # Time in different power states
+system.physmem.memoryStateTime::REF 94311620000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 32616675500 # Time in different power states
+system.physmem.memoryStateTime::ACT 32676864750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 364754880 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 336820680 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 199023000 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 183781125 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 880003800 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 819522600 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 497119680 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 476098560 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 184472003040 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 184472003040 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 78880301865 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 78435436815 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1625409465000 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1625799697500 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1890702671265 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1890523360320 # Total energy per rank (pJ)
-system.physmem.averagePower::0 669.432189 # Core power per rank (mW)
-system.physmem.averagePower::1 669.368701 # Core power per rank (mW)
+system.physmem.actEnergy::0 364906080 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 337017240 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 199105500 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 183888375 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 880113000 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 819569400 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 496944720 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 476105040 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 184473528720 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 184473528720 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 78935898240 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 78466357035 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1625374711500 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1625786589750 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1890725207760 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1890543055560 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.434632 # Core power per rank (mW)
+system.physmem.averagePower::1 669.370138 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 320 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 45 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 68 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 113 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 237823 # Transaction distribution
-system.membus.trans_dist::ReadResp 237823 # Transaction distribution
-system.membus.trans_dist::WriteReq 30977 # Transaction distribution
-system.membus.trans_dist::WriteResp 30977 # Transaction distribution
-system.membus.trans_dist::Writeback 113474 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 79489 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 40661 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 13729 # Transaction distribution
-system.membus.trans_dist::ReadExReq 31194 # Transaction distribution
-system.membus.trans_dist::ReadExResp 14874 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13738 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708779 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 830527 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72710 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 903237 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27476 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21056476 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 21247122 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 23566418 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 122973 # Total snoops (count)
-system.membus.snoop_fanout::samples 500866 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 500866 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 500866 # Request fanout histogram
-system.membus.reqLayer0.occupancy 81235490 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 11626497 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1642596998 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer2.occupancy 2113984385 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer3.occupancy 38546403 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 153419 # number of replacements
-system.l2c.tags.tagsinuse 64440.075057 # Cycle average of tags in use
-system.l2c.tags.total_refs 521049 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 218085 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.389201 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 14106.989110 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.481706 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 2.879098 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 1413.448081 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 2144.570039 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 39278.457251 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.502209 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 0.002709 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 292.869735 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 885.757521 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6295.117598 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.215256 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000221 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000044 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.004469 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.013516 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.096056 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.983278 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022 44367 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023 19 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 20280 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2 411 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3 7792 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4 36164 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 20 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 342 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 4621 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 15296 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022 0.676987 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000290 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.309448 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 6602520 # Number of tag accesses
-system.l2c.tags.data_accesses 6602520 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 282 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 122 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 12559 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 39006 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 182592 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 97 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 55 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 4109 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 11553 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 44326 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 294701 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 252802 # number of Writeback hits
-system.l2c.Writeback_hits::total 252802 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 11705 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 727 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 12432 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 184 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 173 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 357 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 3642 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 1229 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 4871 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 282 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 122 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 12559 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 42648 # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.inst 4109 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 12782 # number of demand (read+write) hits
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-system.l2c.demand_hits::total 299572 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 282 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 122 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 12559 # number of overall hits
-system.l2c.overall_hits::cpu0.data 42648 # number of overall hits
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-system.l2c.overall_hits::cpu1.inst 4109 # number of overall hits
-system.l2c.overall_hits::cpu1.data 12782 # number of overall hits
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-system.l2c.overall_hits::total 299572 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 34 # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu0.data 8647 # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu1.data 1383 # number of ReadReq misses
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-system.l2c.ReadReq_misses::total 199597 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 8851 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 2828 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 11679 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 749 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 1203 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1952 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 7757 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 7215 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 14972 # number of ReadExReq misses
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-system.l2c.demand_misses::cpu0.data 16404 # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.data 8598 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher 21024 # number of demand (read+write) misses
-system.l2c.demand_misses::total 214569 # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu0.itb.walker 8 # number of overall misses
-system.l2c.overall_misses::cpu0.inst 3733 # number of overall misses
-system.l2c.overall_misses::cpu0.data 16404 # number of overall misses
-system.l2c.overall_misses::cpu0.l2cache.prefetcher 164277 # number of overall misses
-system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses
-system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses
-system.l2c.overall_misses::cpu1.inst 479 # number of overall misses
-system.l2c.overall_misses::cpu1.data 8598 # number of overall misses
-system.l2c.overall_misses::cpu1.l2cache.prefetcher 21024 # number of overall misses
-system.l2c.overall_misses::total 214569 # number of overall misses
-system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2727250 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.itb.walker 613750 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.inst 350075996 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.data 761569744 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18989592837 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 768250 # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_latency::cpu1.itb.walker 150000 # number of ReadReq miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 105134250 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 20343291231 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 89616766 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 28576308 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 118193074 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 7674203 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 12103692 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 19777895 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 615195579 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 471924516 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 1087120095 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 513750 # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu0.data 1269353323 # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu1.inst 41455250 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 577058766 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 21430411326 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2306250 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 513750 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 303960496 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 1269353323 # number of overall MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 643750 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 125000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 41455250 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 577058766 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2264811654 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 21430411326 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 159081750 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3686341747 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5350750 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 1919844500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 5770618747 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2713885499 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 1535420500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 4249305999 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 159081750 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 6400227246 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5350750 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 3455265000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 10019924746 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.181437 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.106911 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.403750 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.430580 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.795499 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.484385 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.802787 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.874273 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.845388 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.680498 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.854453 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.754523 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.417288 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.107595 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.061538 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.229131 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.277772 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.473591 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.093458 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.035088 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.103967 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.402152 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.321438 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.417288 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 75660.160074 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 76018.980477 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 101934.085427 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10125.044176 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10104.776521 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10120.136484 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10245.931909 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10061.256858 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10132.118340 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 79308.441279 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 65408.803326 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 72610.212063 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67830.882353 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 64218.750000 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 81425.260113 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77385.436993 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 103304.132650 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64375 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 86908.280922 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67115.464759 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 107817.369037 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 99887.722044 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 660487 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 660472 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30977 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30977 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 252802 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 91823 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 41018 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 132841 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 40090 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 40090 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1299997 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426747 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1726744 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 40789878 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8569500 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 49359378 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 291335 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 1084475 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.033634 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.180285 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 1048000 96.64% 96.64% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36475 3.36% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 1084475 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 1587731325 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2275347621 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 846816900 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 31016 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31016 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59425 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq 15 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180912 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321208 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321208 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2484058 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 326640327 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36831597 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu0.branchPred.lookups 24028098 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 15717962 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 977131 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 14655901 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 10773369 # Number of BTB hits
+system.cpu0.branchPred.lookups 24027931 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 15718166 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 977317 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 14657289 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 10772949 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 73.508746 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 3877913 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 32441 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 73.498919 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 3877670 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 32392 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 17721911 # DTB read hits
-system.cpu0.dtb.read_misses 56434 # DTB read misses
-system.cpu0.dtb.write_hits 14647364 # DTB write hits
-system.cpu0.dtb.write_misses 8710 # DTB write misses
+system.cpu0.dtb.read_hits 17722563 # DTB read hits
+system.cpu0.dtb.read_misses 56347 # DTB read misses
+system.cpu0.dtb.write_hits 14648246 # DTB write hits
+system.cpu0.dtb.write_misses 8736 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 318 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 2358 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3529 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 316 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 2360 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 855 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 17778345 # DTB read accesses
-system.cpu0.dtb.write_accesses 14656074 # DTB write accesses
+system.cpu0.dtb.perms_faults 858 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 17778910 # DTB read accesses
+system.cpu0.dtb.write_accesses 14656982 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 32369275 # DTB hits
-system.cpu0.dtb.misses 65144 # DTB misses
-system.cpu0.dtb.accesses 32434419 # DTB accesses
+system.cpu0.dtb.hits 32370809 # DTB hits
+system.cpu0.dtb.misses 65083 # DTB misses
+system.cpu0.dtb.accesses 32435892 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 37749203 # ITB inst hits
-system.cpu0.itb.inst_misses 10291 # ITB inst misses
+system.cpu0.itb.inst_hits 37749898 # ITB inst hits
+system.cpu0.itb.inst_misses 10270 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2371 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2361 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1952 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1943 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 37759494 # ITB inst accesses
-system.cpu0.itb.hits 37749203 # DTB hits
-system.cpu0.itb.misses 10291 # DTB misses
-system.cpu0.itb.accesses 37759494 # DTB accesses
-system.cpu0.numCycles 126930318 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 37760168 # ITB inst accesses
+system.cpu0.itb.hits 37749898 # DTB hits
+system.cpu0.itb.misses 10270 # DTB misses
+system.cpu0.itb.accesses 37760168 # DTB accesses
+system.cpu0.numCycles 126937172 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 18136746 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 112711782 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 24028098 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 14651282 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 104771989 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 2822564 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 133376 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 38789 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 365072 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 429907 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 37570 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 37749815 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 265004 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3918 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 125324731 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.084977 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 1.263079 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 18140410 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 112713647 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 24027931 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 14650619 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 104775763 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 2822832 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 131776 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 38634 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 364177 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 430173 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 37568 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 37750515 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 265085 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 3932 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 125329917 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.084963 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 1.263075 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 62770441 50.09% 50.09% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 21460959 17.12% 67.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 8766539 7.00% 74.21% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 32326792 25.79% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 62773644 50.09% 50.09% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 21461872 17.12% 67.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 8766803 6.99% 74.21% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 32327598 25.79% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 125324731 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.189301 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.887982 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 19209269 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 58676701 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 41413260 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 4958284 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1067217 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 3055385 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 348256 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 110724808 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 3997323 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1067217 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 24959463 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 12008700 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 36549302 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 40482992 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 10257057 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 105644030 # Number of instructions processed by rename
-system.cpu0.rename.SquashedInsts 1060860 # Number of squashed instructions processed by rename
-system.cpu0.rename.ROBFullEvents 1434602 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 161076 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 61450 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 6058216 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 109726611 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 482367040 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 120917485 # Number of integer rename lookups
+system.cpu0.fetch.rateDist::total 125329917 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.189290 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.887948 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 19211260 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 58677383 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 41416135 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 4957927 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1067212 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 3055574 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 348409 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 110727822 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 3998029 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1067212 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 24961632 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 12004838 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 36556596 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 40485229 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 10254410 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 105647594 # Number of instructions processed by rename
+system.cpu0.rename.SquashedInsts 1060765 # Number of squashed instructions processed by rename
+system.cpu0.rename.ROBFullEvents 1435224 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 161199 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 61281 # Number of times rename has blocked due to LQ full
+system.cpu0.rename.SQFullEvents 6055537 # Number of times rename has blocked due to SQ full
+system.cpu0.rename.RenamedOperands 109729609 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 482383818 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 120922156 # Number of integer rename lookups
system.cpu0.rename.fp_rename_lookups 9389 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 98135067 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 11591541 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1228775 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 1087468 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 12318365 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 18735262 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 16202067 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1700806 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 2287265 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 102683814 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1694438 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 100667981 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 483835 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 9019913 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 22488132 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 122848 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 125324731 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.803257 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.034844 # Number of insts issued each cycle
+system.cpu0.rename.CommittedMaps 98138163 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 11591443 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1228785 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 1087461 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 12318010 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 18735902 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 16202980 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1699572 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 2289990 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 102687216 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1694558 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 100671408 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 483936 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 9020941 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 22487287 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 122833 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 125329917 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::mean 0.803251 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::stdev 1.034851 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 69182553 55.20% 55.20% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 23178514 18.49% 73.70% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 22516011 17.97% 91.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 9333204 7.45% 99.11% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 1114412 0.89% 100.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 37 0.00% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 69186063 55.20% 55.20% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 23179586 18.49% 73.70% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 22515563 17.97% 91.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 9334163 7.45% 99.11% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 1114503 0.89% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 39 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 125324731 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 125329917 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 9379454 40.76% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 82 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.76% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 5581640 24.26% 65.02% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 8050330 34.98% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 9379139 40.75% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 80 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.75% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 5583986 24.26% 65.02% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 8051096 34.98% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 66408183 65.97% 65.97% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 93140 0.09% 66.06% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 66410061 65.97% 65.97% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 93146 0.09% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.06% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 2 0.00% 66.06% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 8109 0.01% 66.07% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 8111 0.01% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.07% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.07% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 18430252 18.31% 84.38% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 15726021 15.62% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 18430824 18.31% 84.38% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 15726990 15.62% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 100667981 # Type of FU issued
-system.cpu0.iq.rate 0.793096 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 23011506 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.228588 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 350124170 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 113406012 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 98579580 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 31864 # Number of floating instruction queue reads
+system.cpu0.iq.FU_type_0::total 100671408 # Type of FU issued
+system.cpu0.iq.rate 0.793081 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 23014301 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.228608 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 350139117 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 113410576 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 98583429 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 31853 # Number of floating instruction queue reads
system.cpu0.iq.fp_inst_queue_writes 11293 # Number of floating instruction queue writes
system.cpu0.iq.fp_inst_queue_wakeup_accesses 9723 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 123656622 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 20592 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 365489 # Number of loads that had data forwarded from stores
+system.cpu0.iq.int_alu_accesses 123662855 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 20581 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 365420 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2006492 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2605 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 19209 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1022192 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2006460 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2583 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 19225 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1022371 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 106472 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 336634 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 106487 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 336614 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1067217 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 1619268 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 191305 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 104552982 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewSquashCycles 1067212 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 1617559 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 190582 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 104556500 # Number of instructions dispatched to IQ
system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 18735262 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 16202067 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 876141 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 27204 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 140421 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 19209 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 291739 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 400527 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 692266 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 99570429 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 17973451 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 1032544 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewDispLoadInsts 18735902 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 16202980 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 876211 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 27258 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 139659 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 19225 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 291750 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 400567 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 692317 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 99574081 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 17974103 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 1032379 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 174730 # number of nop insts executed
-system.cpu0.iew.exec_refs 33508210 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 16843179 # Number of branches executed
-system.cpu0.iew.exec_stores 15534759 # Number of stores executed
-system.cpu0.iew.exec_rate 0.784450 # Inst execution rate
-system.cpu0.iew.wb_sent 99039643 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 98589303 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 51320532 # num instructions producing a value
-system.cpu0.iew.wb_consumers 84799978 # num instructions consuming a value
+system.cpu0.iew.exec_nop 174726 # number of nop insts executed
+system.cpu0.iew.exec_refs 33509859 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 16843488 # Number of branches executed
+system.cpu0.iew.exec_stores 15535756 # Number of stores executed
+system.cpu0.iew.exec_rate 0.784436 # Inst execution rate
+system.cpu0.iew.wb_sent 99043344 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 98593152 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 51321674 # num instructions producing a value
+system.cpu0.iew.wb_consumers 84801576 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.776720 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.605195 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.776708 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.605197 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 8525678 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 1571590 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 633066 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 123570875 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.768216 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.481246 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 8525747 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 1571725 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 633113 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 123576047 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.768210 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.481297 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 79246760 64.13% 64.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 24711613 20.00% 84.13% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 8248135 6.67% 90.80% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 3213746 2.60% 93.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 3439781 2.78% 96.19% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 1516341 1.23% 97.41% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 1141391 0.92% 98.34% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 534018 0.43% 98.77% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1519090 1.23% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 79251877 64.13% 64.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 24711108 20.00% 84.13% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 8248464 6.67% 90.80% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 3214478 2.60% 93.40% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 3439388 2.78% 96.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 1513562 1.22% 97.41% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 1143910 0.93% 98.34% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 534023 0.43% 98.77% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1519237 1.23% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 123570875 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 78899754 # Number of instructions committed
-system.cpu0.commit.committedOps 94929142 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 123576047 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 78902307 # Number of instructions committed
+system.cpu0.commit.committedOps 94932349 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 31908645 # Number of memory references committed
-system.cpu0.commit.loads 16728770 # Number of loads committed
-system.cpu0.commit.membars 647107 # Number of memory barriers committed
-system.cpu0.commit.branches 16205360 # Number of branches committed
+system.cpu0.commit.refs 31910051 # Number of memory references committed
+system.cpu0.commit.loads 16729442 # Number of loads committed
+system.cpu0.commit.membars 647161 # Number of memory barriers committed
+system.cpu0.commit.branches 16205593 # Number of branches committed
system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 81878721 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 1929507 # Number of function calls committed.
+system.cpu0.commit.int_insts 81881586 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 1929479 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 62921673 66.28% 66.28% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 90715 0.10% 66.38% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 62923469 66.28% 66.28% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 90718 0.10% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 8109 0.01% 66.39% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 8111 0.01% 66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.39% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.39% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 16728770 17.62% 84.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 15179875 15.99% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 16729442 17.62% 84.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 15180609 15.99% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 94929142 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1519090 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 94932349 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1519237 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 221323955 # The number of ROB reads
-system.cpu0.rob.rob_writes 208662740 # The number of ROB writes
-system.cpu0.timesIdled 109422 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 1605587 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 5521751456 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 78777703 # Number of Instructions Simulated
-system.cpu0.committedOps 94807091 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.611247 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.611247 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.620637 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.620637 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 110612001 # number of integer regfile reads
-system.cpu0.int_regfile_writes 59736021 # number of integer regfile writes
+system.cpu0.rob.rob_reads 221333052 # The number of ROB reads
+system.cpu0.rob.rob_writes 208669303 # The number of ROB writes
+system.cpu0.timesIdled 109478 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 1607255 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 5521794529 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 78780256 # Number of Instructions Simulated
+system.cpu0.committedOps 94810298 # Number of Ops (including micro ops) Simulated
+system.cpu0.cpi 1.611282 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 1.611282 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.620624 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.620624 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 110616528 # number of integer regfile reads
+system.cpu0.int_regfile_writes 59738270 # number of integer regfile writes
system.cpu0.fp_regfile_reads 8164 # number of floating regfile reads
system.cpu0.fp_regfile_writes 2269 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 350763374 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 41072426 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 246706358 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 1224463 # number of misc regfile writes
-system.cpu0.toL2Bus.trans_dist::ReadReq 2021709 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1920443 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 19105 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 19105 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 512971 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 647722 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 80908 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43157 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 104918 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 291878 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 281134 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2533809 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360432 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28914 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120703 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 5043858 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80936864 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86195670 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50328 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 219428 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 167402290 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 1041040 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 3611543 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.254928 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.435821 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 2690859 74.51% 74.51% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 920684 25.49% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3611543 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 1890112247 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 117326747 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 1900909092 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1220029643 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 16342731 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 65878690 # Layer occupancy (ticks)
-system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu0.icache.tags.replacements 1263367 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.774258 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 36446077 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1263879 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 28.836682 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 6311559000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774258 # Average occupied blocks per requestor
+system.cpu0.cc_regfile_reads 350776322 # number of cc regfile reads
+system.cpu0.cc_regfile_writes 41073406 # number of cc regfile writes
+system.cpu0.misc_regfile_reads 245816593 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 1224552 # number of misc regfile writes
+system.cpu0.dcache.tags.replacements 712837 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 493.082878 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 28842463 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 713349 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 40.432471 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 256881000 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 493.082878 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 63484078 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 63484078 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 15589241 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 15589241 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 12071944 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 12071944 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 310964 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 310964 # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363200 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 363200 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360654 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 360654 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 27661185 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 27661185 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 27972149 # number of overall hits
+system.cpu0.dcache.overall_hits::total 27972149 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 638343 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 638343 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 1832165 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 1832165 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146120 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 146120 # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20612 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 20612 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 2470508 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 2470508 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 2616628 # number of overall misses
+system.cpu0.dcache.overall_misses::total 2616628 # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8099233830 # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total 8099233830 # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24956974532 # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total 24956974532 # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395327755 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total 395327755 # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453888287 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total 453888287 # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 344500 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.StoreCondFailReq_miss_latency::total 344500 # number of StoreCondFailReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data 33056208362 # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total 33056208362 # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data 33056208362 # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total 33056208362 # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 16227584 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 16227584 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 13904109 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 13904109 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457084 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 457084 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388176 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 388176 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381266 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 381266 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 30131693 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 30131693 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 30588777 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 30588777 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039337 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.039337 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131771 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.131771 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319679 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319679 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064342 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064342 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054062 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054062 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081990 # miss rate for demand accesses
+system.cpu0.dcache.demand_miss_rate::total 0.081990 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085542 # miss rate for overall accesses
+system.cpu0.dcache.overall_miss_rate::total 0.085542 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12687.902632 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 12687.902632 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13621.575858 # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::total 13621.575858 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15828.305373 # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15828.305373 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22020.584465 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22020.584465 # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
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+system.cpu0.dcache.overall_mshr_hits::total 1767726 # number of overall MSHR hits
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14927.230664 # average LoadLockedReq mshr miss latency
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system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 244130748 # number of ReadReq MSHR uncacheable cycles
system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 244130748 # number of overall MSHR uncacheable cycles
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system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
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system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu0.dcache.tags.avg_refs 40.431815 # Average number of references to valid blocks.
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-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.963052 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.963052 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 176 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 321 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 63481444 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 63481444 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 15588806 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 15588806 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 12071580 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 12071580 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 311031 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 311031 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363190 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 363190 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 360636 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 360636 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 27660386 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 27660386 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 27971417 # number of overall hits
-system.cpu0.dcache.overall_hits::total 27971417 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 638107 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 638107 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1831928 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1831928 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 146057 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 146057 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24976 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 24976 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20607 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 20607 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 2470035 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 2470035 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 2616092 # number of overall misses
-system.cpu0.dcache.overall_misses::total 2616092 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8089240805 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 8089240805 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24966494558 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 24966494558 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 395038253 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 395038253 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 453870788 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 453870788 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 394000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 394000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 33055735363 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 33055735363 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 33055735363 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 33055735363 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 16226913 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 16226913 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 13903508 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 13903508 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 457088 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 457088 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388166 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 388166 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381243 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 381243 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 30130421 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 30130421 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 30587509 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 30587509 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039324 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.039324 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.131760 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.131760 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.319538 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.319538 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064344 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064344 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.054052 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.054052 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.081978 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.081978 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.085528 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.085528 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12676.934754 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12676.934754 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 13628.534832 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 13628.534832 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15816.714166 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15816.714166 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22025.078274 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22025.078274 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13382.699178 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13382.699178 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12635.540097 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 12635.540097 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 1333 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 3370028 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 68 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 191306 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.602941 # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets 17.615903 # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 512971 # number of writebacks
-system.cpu0.dcache.writebacks::total 512971 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 247929 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 247929 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1519381 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 1519381 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18420 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18420 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 1767310 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 1767310 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 1767310 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 1767310 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 390178 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 390178 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312547 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 312547 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101517 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 101517 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6556 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6556 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20607 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 20607 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 702725 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 702725 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 804242 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 804242 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4170870238 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4170870238 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4998082086 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4998082086 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1413907491 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1413907491 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97710498 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97710498 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 411958212 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 411958212 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 372000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 372000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9168952324 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 9168952324 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10582859815 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 10582859815 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4217153741 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4217153741 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3187052487 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3187052487 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7404206228 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7404206228 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024045 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024045 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.022480 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.022480 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222095 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222095 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016890 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016890 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.054052 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.054052 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023323 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.023323 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026293 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.026293 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10689.660201 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10689.660201 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15991.457560 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15991.457560 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 13927.790331 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 13927.790331 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14903.980781 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14903.980781 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19991.178337 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19991.178337 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13047.710447 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13047.710447 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13158.800231 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13158.800231 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 33910931 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 11562938 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 305104 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 18756149 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 14959197 # Number of BTB hits
+system.cpu0.toL2Bus.trans_dist::ReadReq 2021884 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1920690 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 19107 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 19107 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 513073 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 646583 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 80962 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43193 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 104964 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 291894 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 281156 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2534332 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2360691 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28712 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 120464 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 5044199 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 80953568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86204446 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 49568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 218536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 167426118 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 1040274 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 3610797 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.254659 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.435670 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 2691274 74.53% 74.53% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 919523 25.47% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 3610797 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 1890423984 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 117333499 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer0.occupancy 1901305348 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer1.occupancy 1220101128 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer2.occupancy 16329482 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu0.toL2Bus.respLayer3.occupancy 65866183 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu1.branchPred.lookups 33911271 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 11563003 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 305102 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 18755199 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 14959397 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 79.756228 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 12490116 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 7241 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 79.761334 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 12490268 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 7230 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 10163466 # DTB read hits
-system.cpu1.dtb.read_misses 18799 # DTB read misses
-system.cpu1.dtb.write_hits 6542146 # DTB write hits
-system.cpu1.dtb.write_misses 2834 # DTB write misses
+system.cpu1.dtb.read_hits 10163694 # DTB read hits
+system.cpu1.dtb.read_misses 18763 # DTB read misses
+system.cpu1.dtb.write_hits 6542250 # DTB write hits
+system.cpu1.dtb.write_misses 2833 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 2050 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 53 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 373 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 406 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 10182265 # DTB read accesses
-system.cpu1.dtb.write_accesses 6544980 # DTB write accesses
+system.cpu1.dtb.perms_faults 411 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 10182457 # DTB read accesses
+system.cpu1.dtb.write_accesses 6545083 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 16705612 # DTB hits
-system.cpu1.dtb.misses 21633 # DTB misses
-system.cpu1.dtb.accesses 16727245 # DTB accesses
+system.cpu1.dtb.hits 16705944 # DTB hits
+system.cpu1.dtb.misses 21596 # DTB misses
+system.cpu1.dtb.accesses 16727540 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 43642051 # ITB inst hits
-system.cpu1.itb.inst_misses 6989 # ITB inst misses
+system.cpu1.itb.inst_hits 43642438 # ITB inst hits
+system.cpu1.itb.inst_misses 7000 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 1203 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 1205 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 541 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 538 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 43649040 # ITB inst accesses
-system.cpu1.itb.hits 43642051 # DTB hits
-system.cpu1.itb.misses 6989 # DTB misses
-system.cpu1.itb.accesses 43649040 # DTB accesses
-system.cpu1.numCycles 104614253 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 43649438 # ITB inst accesses
+system.cpu1.itb.hits 43642438 # DTB hits
+system.cpu1.itb.misses 7000 # DTB misses
+system.cpu1.itb.accesses 43649438 # DTB accesses
+system.cpu1.numCycles 104622324 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 9984991 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 109167147 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 33910931 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 27449313 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 91788694 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3775566 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 78493 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 31389 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 199715 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 294230 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 7403 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 43641443 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 116254 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 2254 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 104272698 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.296959 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 1.339784 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 9983715 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 109168018 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 33911271 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 27449665 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 91793931 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3775602 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 78298 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 31640 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 200637 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 294928 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 7575 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 43641835 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 116209 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 2258 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 104278525 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.296897 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 1.339782 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 47324573 45.39% 45.39% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 14035291 13.46% 58.85% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 7536357 7.23% 66.07% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 35376477 33.93% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 47329971 45.39% 45.39% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 14035379 13.46% 58.85% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 7536372 7.23% 66.07% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 35376803 33.93% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 104272698 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.324152 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 1.043521 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 13017206 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 61665780 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 26725185 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 1111466 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1753061 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 754244 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 137628 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 68061507 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 1169291 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1753061 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 17449719 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 2249370 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 56981821 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 23380432 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 2458295 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 55156803 # Number of instructions processed by rename
-system.cpu1.rename.SquashedInsts 230618 # Number of squashed instructions processed by rename
-system.cpu1.rename.ROBFullEvents 263094 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 35438 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 18102 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 1431236 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 55002903 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 260522537 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 58680311 # Number of integer rename lookups
+system.cpu1.fetch.rateDist::total 104278525 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.324130 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 1.043449 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 13017622 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 61671390 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 26724772 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 1111637 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1753104 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 754173 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 137598 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 68061604 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 1168958 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1753104 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 17450100 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 2254257 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 56981217 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 23380222 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 2459625 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 55156752 # Number of instructions processed by rename
+system.cpu1.rename.SquashedInsts 230613 # Number of squashed instructions processed by rename
+system.cpu1.rename.ROBFullEvents 263389 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 35416 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 18082 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 1432431 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 55002738 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 260522478 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 58680214 # Number of integer rename lookups
system.cpu1.rename.fp_rename_lookups 1689 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 52222762 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 2780141 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1878015 # count of serializing insts renamed
+system.cpu1.rename.CommittedMaps 52222609 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 2780129 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1878054 # count of serializing insts renamed
system.cpu1.rename.tempSerializingInsts 1805384 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 13100914 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 10457203 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 6914095 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 629486 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 832023 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 54264845 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 589076 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 53908335 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 111707 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 2293120 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 5811368 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 48776 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 104272698 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.516994 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 0.852584 # Number of insts issued each cycle
+system.cpu1.rename.skidInsts 13101359 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 10457131 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 6914141 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 629237 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 831086 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 54264809 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 589071 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 53908897 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 111732 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 2292977 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 5809537 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 48790 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 104278525 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.516970 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 0.852578 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 71021448 68.11% 68.11% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 16528398 15.85% 83.96% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 13076148 12.54% 96.50% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 3359187 3.22% 99.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 287505 0.28% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 71027306 68.11% 68.11% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 16528003 15.85% 83.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 13076309 12.54% 96.50% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 3359364 3.22% 99.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 287531 0.28% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 104272698 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 104278525 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 2925111 45.11% 45.11% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 678 0.01% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.12% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 1673253 25.80% 70.93% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 1885198 29.07% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 2925381 45.12% 45.12% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 677 0.01% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.13% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 1673591 25.81% 70.94% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 1884116 29.06% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 36727070 68.13% 68.13% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 46542 0.09% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 36727260 68.13% 68.13% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 46535 0.09% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued
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+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 2 0.00% 68.21% # Type of FU issued
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+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued
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+system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMisc 3339 0.01% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.22% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.22% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 10379930 19.25% 87.48% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 6751385 12.52% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 10380151 19.25% 87.48% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 6751543 12.52% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 53908335 # Type of FU issued
-system.cpu1.iq.rate 0.515306 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 6484240 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.120283 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 218679535 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 57155155 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 51920155 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 5780 # Number of floating instruction queue reads
+system.cpu1.iq.FU_type_0::total 53908897 # Type of FU issued
+system.cpu1.iq.rate 0.515271 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 6483765 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.120273 # FU busy rate (busy events/executed inst)
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+system.cpu1.iq.int_inst_queue_writes 57154966 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 51920427 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 5790 # Number of floating instruction queue reads
system.cpu1.iq.fp_inst_queue_writes 2052 # Number of floating instruction queue writes
system.cpu1.iq.fp_inst_queue_wakeup_accesses 1786 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 60388817 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 3692 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 91403 # Number of loads that had data forwarded from stores
+system.cpu1.iq.int_alu_accesses 60388895 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 3701 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 91393 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 490692 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 490676 # Number of loads squashed
system.cpu1.iew.lsq.thread0.ignoredResponses 687 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 10198 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 355978 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 10193 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 356081 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 51963 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 70332 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 51970 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 70495 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1753061 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 546569 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 114085 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 54906076 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewSquashCycles 1753104 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 548003 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 114295 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 54906042 # Number of instructions dispatched to IQ
system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 10457203 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 6914095 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 301562 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 9838 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 96727 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 10198 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 54956 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 127310 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 182266 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 53638370 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 10277968 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 248350 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewDispLoadInsts 10457131 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 6914141 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 301584 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 9824 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 96972 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 10193 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 54960 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 127313 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 182273 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 53638837 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 10278190 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 248481 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 52155 # number of nop insts executed
-system.cpu1.iew.exec_refs 16965083 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 11807834 # Number of branches executed
-system.cpu1.iew.exec_stores 6687115 # Number of stores executed
-system.cpu1.iew.exec_rate 0.512725 # Inst execution rate
-system.cpu1.iew.wb_sent 53497576 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 51921941 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 25229731 # num instructions producing a value
-system.cpu1.iew.wb_consumers 38490253 # num instructions consuming a value
+system.cpu1.iew.exec_nop 52162 # number of nop insts executed
+system.cpu1.iew.exec_refs 16965416 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 11807917 # Number of branches executed
+system.cpu1.iew.exec_stores 6687226 # Number of stores executed
+system.cpu1.iew.exec_rate 0.512690 # Inst execution rate
+system.cpu1.iew.wb_sent 53497875 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 51922213 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 25229776 # num instructions producing a value
+system.cpu1.iew.wb_consumers 38490454 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.496318 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.655484 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.496282 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.655481 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 3658728 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 540300 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 170382 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 102340769 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.498127 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.159192 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 3658692 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 540281 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 170405 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 102346479 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.498098 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.159114 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 76762339 75.01% 75.01% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 14287767 13.96% 88.97% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6080575 5.94% 94.91% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 703802 0.69% 95.60% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1980023 1.93% 97.53% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 1565125 1.53% 99.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 446359 0.44% 99.50% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 123712 0.12% 99.62% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 391067 0.38% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 76767559 75.01% 75.01% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 14288132 13.96% 88.97% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6080244 5.94% 94.91% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 703970 0.69% 95.60% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1980102 1.93% 97.53% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 1566998 1.53% 99.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 444730 0.43% 99.50% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 123732 0.12% 99.62% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 391012 0.38% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 102340769 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 41392870 # Number of instructions committed
-system.cpu1.commit.committedOps 50978714 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 102346479 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 41392684 # Number of instructions committed
+system.cpu1.commit.committedOps 50978528 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 16524628 # Number of memory references committed
-system.cpu1.commit.loads 9966511 # Number of loads committed
-system.cpu1.commit.membars 209715 # Number of memory barriers committed
-system.cpu1.commit.branches 11639820 # Number of branches committed
+system.cpu1.commit.refs 16524515 # Number of memory references committed
+system.cpu1.commit.loads 9966455 # Number of loads committed
+system.cpu1.commit.membars 209698 # Number of memory barriers committed
+system.cpu1.commit.branches 11639872 # Number of branches committed
system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 45828641 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 3366594 # Number of function calls committed.
+system.cpu1.commit.int_insts 45828467 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 3366626 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 34405110 67.49% 67.49% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 45637 0.09% 67.58% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 34405041 67.49% 67.49% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 45633 0.09% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.58% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.59% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.59% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 9966511 19.55% 87.14% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 6558117 12.86% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 9966455 19.55% 87.14% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 6558060 12.86% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 50978714 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 391067 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 50978528 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 391012 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 136550879 # The number of ROB reads
-system.cpu1.rob.rob_writes 111203214 # The number of ROB writes
-system.cpu1.timesIdled 53373 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 341555 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 5543525682 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 41360016 # Number of Instructions Simulated
-system.cpu1.committedOps 50945860 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 2.529357 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 2.529357 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.395357 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.395357 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 56284604 # number of integer regfile reads
-system.cpu1.int_regfile_writes 35740768 # number of integer regfile writes
+system.cpu1.rob.rob_reads 136555973 # The number of ROB reads
+system.cpu1.rob.rob_writes 111202855 # The number of ROB writes
+system.cpu1.timesIdled 53415 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 343799 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 5543567058 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 41359830 # Number of Instructions Simulated
+system.cpu1.committedOps 50945674 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 2.529564 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 2.529564 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.395325 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.395325 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 56285102 # number of integer regfile reads
+system.cpu1.int_regfile_writes 35740910 # number of integer regfile writes
system.cpu1.fp_regfile_reads 1413 # number of floating regfile reads
system.cpu1.fp_regfile_writes 520 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 191160889 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 15560745 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 205861724 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 388836 # number of misc regfile writes
-system.cpu1.toL2Bus.trans_dist::ReadReq 1295167 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 865146 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 11872 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 11872 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 117435 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 157667 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36228 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 84819 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41863 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 87089 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 79490 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 66369 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215695 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 824924 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17344 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37959 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2095922 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38897296 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25431436 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30740 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67228 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 64426700 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 835314 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1798151 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.418656 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.493339 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 1045344 58.13% 58.13% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 752807 41.87% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1798151 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 659597923 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 81215248 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 913005612 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 403790804 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 9801715 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 21218619 # Layer occupancy (ticks)
-system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu1.icache.tags.replacements 607233 # number of replacements
-system.cpu1.icache.tags.tagsinuse 499.524677 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 43016935 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 607745 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 70.781224 # Average number of references to valid blocks.
+system.cpu1.cc_regfile_reads 191162273 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 15560809 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 205875636 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 388862 # number of misc regfile writes
+system.cpu1.dcache.tags.replacements 191071 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 472.558495 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 15741437 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 82.245811 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558495 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 32983767 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 32983767 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 9574609 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 9574609 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 5910607 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 5910607 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49573 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 49573 # number of SoftPFReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79145 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 79145 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71001 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 71001 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 15485216 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 15485216 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 15534789 # number of overall hits
+system.cpu1.dcache.overall_hits::total 15534789 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 219415 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 219415 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 398307 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 398307 # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30093 # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total 30093 # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18121 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 18121 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23394 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 23394 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 617722 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 617722 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 647815 # number of overall misses
+system.cpu1.dcache.overall_misses::total 647815 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3455998019 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 3455998019 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8728631208 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 8728631208 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 363006249 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 363006249 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542688316 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 542688316 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 504500 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 504500 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 12184629227 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 12184629227 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 12184629227 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 12184629227 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 9794024 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 9794024 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308914 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 6308914 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79666 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total 79666 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97266 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 97266 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94395 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 94395 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 16102938 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 16102938 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 16182604 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 16182604 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022403 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.022403 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063134 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.063134 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.377740 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.377740 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186304 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186304 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247831 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247831 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038361 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.038361 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040032 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.040032 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15750.965153 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15750.965153 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21914.330424 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 21914.330424 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20032.351912 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20032.351912 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23197.756519 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23197.756519 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19725.101627 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 19725.101627 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18808.809964 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 18808.809964 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 357 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 1112453 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 37 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 39616 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.648649 # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets 28.080902 # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 0 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks 117473 # number of writebacks
+system.cpu1.dcache.writebacks::total 117473 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79558 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 79558 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306502 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 306502 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 386060 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 386060 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 386060 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 386060 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139857 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 139857 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91805 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 91805 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28628 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 28628 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4934 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4934 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23394 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 23394 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 231662 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 231662 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 260290 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 260290 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1829354050 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1829354050 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2195265722 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2195265722 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 493416244 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 493416244 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87143250 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87143250 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494733684 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494733684 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 482500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 482500 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4024619772 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 4024619772 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4518036016 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 4518036016 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298838492 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298838492 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826630495 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826630495 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125468987 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125468987 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014280 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014280 # mshr miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23912.267545 # average WriteReq mshr miss latency
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+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17235.442364 # average SoftPFReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17661.785570 # average LoadLockedReq mshr miss latency
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+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21147.887664 # average StoreCondReq mshr miss latency
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system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id
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system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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+system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2050488838 # number of overall MSHR miss cycles
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system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7340750 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2182190507 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189531257 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 1737661499 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737661499 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2189537757 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 1737457999 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7340750 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919852006 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3927192756 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415231 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.095956 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 3919655006 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 3926995756 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.027670 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.034424 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.007590 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.415556 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.096087 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926501 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926501 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.964223 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.964223 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.926261 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.926261 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.965715 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.965715 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.512366 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.512366 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.125634 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028084 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034092 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007529 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.440763 # mshr miss rate for overall accesses
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+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027670 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.034424 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.007590 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.441022 # mshr miss rate for demand accesses
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+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027670 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.034424 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.007590 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.441022 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.251927 # mshr miss rate for overall accesses
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-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15354.903784 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16036.495240 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31593.880532 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14685.116035 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14685.116035 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.930136 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.930136 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 183999.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 183999.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29815.851433 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29815.851433 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20041.586878 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15099.048729 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13969.465649 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 26974.985577 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19773.394936 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31593.880532 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 25832.852571 # average overall mshr miss latency
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+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15359.971092 # average ReadReq mshr miss latency
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+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 31767.605426 # average HardPFReq mshr miss latency
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+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14701.156825 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13669.313236 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13669.313236 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 197249.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 197249.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 29786.484471 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 29786.484471 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15002.161987 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19765.843492 # average overall mshr miss latency
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+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13522.731061 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 27408.670208 # average overall mshr miss latency
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+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 31767.605426 # average overall mshr miss latency
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system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 191071 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 472.558673 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 15741841 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 191395 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 82.247922 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 102871508500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.558673 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922966 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.922966 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 324 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.632812 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 32983753 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 32983753 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 9574420 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 9574420 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 5910665 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 5910665 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 49536 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 49536 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 79144 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 79144 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71002 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 71002 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 15485085 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 15485085 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 15534621 # number of overall hits
-system.cpu1.dcache.overall_hits::total 15534621 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 219558 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 219558 # number of ReadReq misses
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-system.cpu1.dcache.WriteReq_misses::total 398300 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30127 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 30127 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18119 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 18119 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23397 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23397 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 617858 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 617858 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 647985 # number of overall misses
-system.cpu1.dcache.overall_misses::total 647985 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3453411003 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 3453411003 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 8719629262 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 8719629262 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362936751 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 362936751 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 542268315 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 542268315 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 468000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 468000 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 12173040265 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 12173040265 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 12173040265 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 12173040265 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 9793978 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 9793978 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 6308965 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 6308965 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79663 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 79663 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97263 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 97263 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94399 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 94399 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 16102943 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 16102943 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 16182606 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 16182606 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022418 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.022418 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.063132 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.063132 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378181 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378181 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.186289 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.186289 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.247852 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.247852 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038369 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.038369 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.040042 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.040042 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15728.923578 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 15728.923578 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21892.114642 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21892.114642 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20030.727468 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20030.727468 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23176.831004 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23176.831004 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19702.003154 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 19702.003154 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18785.990825 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 18785.990825 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 1110000 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 39631 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.421053 # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets 28.008377 # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 117436 # number of writebacks
-system.cpu1.dcache.writebacks::total 117436 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79714 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 79714 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306518 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 306518 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13187 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13187 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 386232 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 386232 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 386232 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 386232 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 139844 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 139844 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91782 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 91782 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28626 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 28626 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4932 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4932 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23397 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23397 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 231626 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 231626 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 260252 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 260252 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1827153559 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1827153559 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2193887187 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2193887187 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494621242 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494621242 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86939750 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86939750 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 494306685 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 494306685 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 448000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 448000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4021040746 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 4021040746 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4515661988 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4515661988 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2298831492 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2298831492 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1826840995 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1826840995 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4125672487 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4125672487 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014279 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014279 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014548 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014548 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.359339 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.359339 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050708 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050708 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.247852 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.247852 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014384 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.014384 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016082 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.016082 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13065.655724 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13065.655724 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23903.240145 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23903.240145 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17278.741075 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17278.741075 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17627.686537 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17627.686537 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21126.925888 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21126.925888 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17360.057791 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17360.057791 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17351.113490 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17351.113490 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.toL2Bus.trans_dist::ReadReq 1294408 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 865128 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 11871 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 11871 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 117472 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 157468 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 84838 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41861 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 87109 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 79574 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 66376 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1215557 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 825064 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17352 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37871 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2095844 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 38892880 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25436874 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30676 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66932 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 64427362 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 834611 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1797339 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.418381 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.493294 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 1045366 58.16% 58.16% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 751973 41.84% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::total 1797339 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 659657903 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 81258998 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer0.occupancy 912908354 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer1.occupancy 403842529 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer2.occupancy 9825216 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu1.toL2Bus.respLayer3.occupancy 21209360 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 31016 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31016 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59408 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59439 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 31 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56654 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107968 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72942 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72942 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180910 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71598 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.798489 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.484867 # mshr miss rate for UpgradeReq accesses
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+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.873822 # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.853996 # mshr miss rate for ReadExReq accesses
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10120.690852 # average UpgradeReq mshr miss latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 708866 # Packet count per connected master and slave (bytes)
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+system.membus.pkt_count_system.iocache.mem_side::total 72710 # Packet count per connected master and slave (bytes)
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+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27484 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21055004 # Cumulative packet size per connected master and slave (bytes)
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+system.membus.pkt_size::total 23564952 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 123021 # Total snoops (count)
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+system.membus.snoop_fanout::mean 1 # Request fanout histogram
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+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 500917 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 500917 # Request fanout histogram
+system.membus.reqLayer0.occupancy 81243492 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 26500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 11638997 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1642210248 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer2.occupancy 2114152611 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38560639 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 659694 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 659679 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30978 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30978 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 252624 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36230 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 91840 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 41050 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 132890 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 21 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 40171 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 40171 # Transaction distribution
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+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 426600 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1725141 # Packet count per connected master and slave (bytes)
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+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8560538 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 49298520 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 291438 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 1083643 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.033661 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.180356 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 1047166 96.63% 96.63% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36477 3.37% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 1083643 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1586607093 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 1044000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2272505602 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 846502909 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed
+system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2744 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 2770 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
sim_ticks 2826844351500 # Number of ticks simulated
final_tick 2826844351500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 97337 # Simulator instruction rate (inst/s)
-host_op_rate 118064 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2430592330 # Simulator tick rate (ticks/s)
-host_mem_usage 558776 # Number of bytes of host memory used
-host_seconds 1163.03 # Real time elapsed on the host
-sim_insts 113205077 # Number of instructions simulated
-sim_ops 137311743 # Number of ops (including micro ops) simulated
+host_inst_rate 107954 # Simulator instruction rate (inst/s)
+host_op_rate 130942 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2695726613 # Simulator tick rate (ticks/s)
+host_mem_usage 568304 # Number of bytes of host memory used
+host_seconds 1048.64 # Real time elapsed on the host
+sim_insts 113204796 # Number of instructions simulated
+sim_ops 137311416 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 1216 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1324048 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9514916 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 10841588 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1324048 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1324048 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5800064 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::total 8135924 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 19 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 22933 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 149190 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 172164 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 90626 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::total 131231 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 430 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 468384 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3365914 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3835226 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 468384 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 468384 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2051780 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 820114 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2878094 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2051780 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 430 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 468384 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3372113 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 820454 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6713320 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 172165 # Number of read requests accepted
system.physmem.writeReqs 131231 # Number of write requests accepted
system.physmem.readBursts 172165 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 131231 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 11009344 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 9216 # Total number of bytes read from write queue
+system.physmem.bytesReadDRAM 11009408 # Total number of bytes read from DRAM
+system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue
system.physmem.bytesWritten 8149760 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10841652 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 8135924 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 144 # Number of DRAM read bursts serviced by the write queue
+system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 4545 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10989 # Per bank write bursts
system.physmem.perBankRdBursts::6 11171 # Per bank write bursts
system.physmem.perBankRdBursts::7 11539 # Per bank write bursts
system.physmem.perBankRdBursts::8 10356 # Per bank write bursts
-system.physmem.perBankRdBursts::9 11055 # Per bank write bursts
+system.physmem.perBankRdBursts::9 11056 # Per bank write bursts
system.physmem.perBankRdBursts::10 10496 # Per bank write bursts
system.physmem.perBankRdBursts::11 9259 # Per bank write bursts
system.physmem.perBankRdBursts::12 10183 # Per bank write bursts
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 126850 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 151967 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 16017 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 151969 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 16016 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 3231 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 789 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1969 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 2547 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 5742 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 6279 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 6541 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 7276 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 7533 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 8094 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1968 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 2544 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 5739 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 6276 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 6540 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 7277 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 7536 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 8095 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 8630 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 9475 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 8903 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 8389 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 7979 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 7945 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 6915 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 9476 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 8902 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 8388 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 7977 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 7946 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 6912 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 6791 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 6777 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 6631 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 6632 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 233 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 196 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 185 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 155 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 147 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 136 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 141 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 133 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::35 187 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::36 158 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::37 149 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::38 137 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::39 142 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 125 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 127 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 119 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 18 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 62143 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 308.305682 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 180.941865 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 329.713467 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 23390 37.64% 37.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14779 23.78% 61.42% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 62147 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 308.286868 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 180.931959 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 329.707872 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 23391 37.64% 37.64% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 14782 23.79% 61.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 6350 10.22% 71.64% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3678 5.92% 77.56% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2603 4.19% 81.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3679 5.92% 77.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2602 4.19% 81.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1532 2.47% 84.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1126 1.81% 86.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1131 1.82% 87.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7554 12.16% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 62143 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6421 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 26.789285 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 556.595179 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6419 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::768-895 1126 1.81% 86.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1130 1.82% 87.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7555 12.16% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 62147 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6420 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 26.793614 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 556.638433 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6418 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6421 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6421 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.831802 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.368831 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 11.481886 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5612 87.40% 87.40% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 55 0.86% 88.26% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 6420 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6420 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.834891 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.369444 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.492928 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5612 87.41% 87.41% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 54 0.84% 88.26% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24-27 30 0.47% 88.72% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28-31 211 3.29% 92.01% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::32-35 221 3.44% 95.45% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 14 0.22% 95.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 14 0.22% 95.89% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 15 0.23% 96.12% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 17 0.26% 96.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 4 0.06% 96.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 3 0.05% 96.50% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 5 0.08% 96.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 166 2.59% 99.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 13 0.20% 95.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 15 0.23% 96.11% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 17 0.26% 96.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 4 0.06% 96.43% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 3 0.05% 96.48% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 5 0.08% 96.56% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 167 2.60% 99.16% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::68-71 7 0.11% 99.27% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::72-75 3 0.05% 99.31% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::76-79 4 0.06% 99.38% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::128-131 3 0.05% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::132-135 1 0.02% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6421 # Writes before turning the bus around for reads
-system.physmem.totQLat 2071957750 # Total ticks spent queuing
-system.physmem.totMemAccLat 5297351500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 860105000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12044.80 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 6420 # Writes before turning the bus around for reads
+system.physmem.totQLat 2072280000 # Total ticks spent queuing
+system.physmem.totMemAccLat 5297692500 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 860110000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12046.60 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 30794.80 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 30796.60 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.88 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.84 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
system.physmem.avgWrQLen 27.07 # Average write queue length when enqueuing
-system.physmem.readRowHits 141999 # Number of row buffer hits during reads
-system.physmem.writeRowHits 95218 # Number of row buffer hits during writes
+system.physmem.readRowHits 142002 # Number of row buffer hits during reads
+system.physmem.writeRowHits 95212 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 74.76 # Row buffer hit rate for writes
system.physmem.avgGap 9317341.50 # Average gap between requests
-system.physmem.pageHitRate 79.24 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2694663327000 # Time in different power states
+system.physmem.pageHitRate 79.23 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2694665773000 # Time in different power states
system.physmem.memoryStateTime::REF 94394300000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 37786710500 # Time in different power states
+system.physmem.memoryStateTime::ACT 37784264500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 245972160 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 223828920 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 134211000 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 122128875 # Energy for precharge commands per rank (pJ)
+system.physmem.actEnergy::0 245987280 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 223844040 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 134219250 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 122137125 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 702912600 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 638843400 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 638851200 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 426267360 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 398895840 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 184635250800 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 184635250800 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 80261886105 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 79073133435 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1625697180750 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1626739946250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1892103680775 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1891832027520 # Total energy per rank (pJ)
-system.physmem.averagePower::0 669.335912 # Core power per rank (mW)
-system.physmem.averagePower::1 669.239814 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 67834 # Transaction distribution
-system.membus.trans_dist::ReadResp 67833 # Transaction distribution
-system.membus.trans_dist::WriteReq 27608 # Transaction distribution
-system.membus.trans_dist::WriteResp 27608 # Transaction distribution
-system.membus.trans_dist::Writeback 90626 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution
-system.membus.trans_dist::ReadExReq 135127 # Transaction distribution
-system.membus.trans_dist::ReadExResp 135127 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 205 # Total snoops (count)
-system.membus.snoop_fanout::samples 300222 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 300222 # Request fanout histogram
-system.membus.reqLayer0.occupancy 94199000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1696000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1357979249 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1678023705 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.physmem.actBackEnergy::0 80264555415 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 79079779350 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1625694839250 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1626734116500 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1892104031955 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1891832874855 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.336036 # Core power per rank (mW)
+system.physmem.averagePower::1 669.240113 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 128 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 128 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 8 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 8 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 45 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 45 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 45 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 45 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 45 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 45 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.branchPred.lookups 46964481 # Number of BP lookups
-system.cpu.branchPred.condPredicted 24050206 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1232756 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 29560774 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 21375284 # Number of BTB hits
+system.cpu.branchPred.lookups 46964274 # Number of BP lookups
+system.cpu.branchPred.condPredicted 24050124 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1232745 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 29560624 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 21375180 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 72.309622 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 11765183 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.BTBHitPct 72.309637 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 11765118 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 33710 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 25471928 # DTB read hits
-system.cpu.dtb.read_misses 60410 # DTB read misses
-system.cpu.dtb.write_hits 19919780 # DTB write hits
+system.cpu.dtb.read_hits 25471879 # DTB read hits
+system.cpu.dtb.read_misses 60408 # DTB read misses
+system.cpu.dtb.write_hits 19919747 # DTB write hits
system.cpu.dtb.write_misses 9388 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.prefetch_faults 2316 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 1300 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 25532338 # DTB read accesses
-system.cpu.dtb.write_accesses 19929168 # DTB write accesses
+system.cpu.dtb.read_accesses 25532287 # DTB read accesses
+system.cpu.dtb.write_accesses 19929135 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 45391708 # DTB hits
-system.cpu.dtb.misses 69798 # DTB misses
-system.cpu.dtb.accesses 45461506 # DTB accesses
+system.cpu.dtb.hits 45391626 # DTB hits
+system.cpu.dtb.misses 69796 # DTB misses
+system.cpu.dtb.accesses 45461422 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 66240861 # ITB inst hits
+system.cpu.itb.inst_hits 66240582 # ITB inst hits
system.cpu.itb.inst_misses 11936 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 2163 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 66252797 # ITB inst accesses
-system.cpu.itb.hits 66240861 # DTB hits
+system.cpu.itb.inst_accesses 66252518 # ITB inst accesses
+system.cpu.itb.hits 66240582 # DTB hits
system.cpu.itb.misses 11936 # DTB misses
-system.cpu.itb.accesses 66252797 # DTB accesses
-system.cpu.numCycles 260549216 # number of cpu cycles simulated
+system.cpu.itb.accesses 66252518 # DTB accesses
+system.cpu.numCycles 260548868 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 104910072 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 184559148 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 46964481 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 33140467 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 145575314 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 6162280 # Number of cycles fetch has spent squashing
+system.cpu.fetch.icacheStallCycles 104909639 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 184558460 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 46964274 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 33140298 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 145575332 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 6162234 # Number of cycles fetch has spent squashing
system.cpu.fetch.TlbCycles 168611 # Number of cycles fetch has spent waiting for tlb
system.cpu.fetch.MiscStallCycles 8187 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 338898 # Number of stall cycles due to pending traps
system.cpu.fetch.PendingQuiesceStallCycles 503455 # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles 112 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 66241173 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 1039454 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.CacheLines 66240894 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.ItlbSquashes 4991 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 254585789 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.884455 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::samples 254585351 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.884453 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 1.237226 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 155338785 61.02% 61.02% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 29243956 11.49% 72.50% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 14083385 5.53% 78.04% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 55919663 21.96% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 155338707 61.02% 61.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 29243843 11.49% 72.50% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 14083345 5.53% 78.04% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 55919456 21.96% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 254585789 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.180252 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.708347 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 78109166 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 105363541 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 64680872 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3828813 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 2603397 # Number of cycles decode is squashing
+system.cpu.fetch.rateDist::total 254585351 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.180251 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.708345 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 78108823 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 105363724 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 64680632 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3828797 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 2603375 # Number of cycles decode is squashing
system.cpu.decode.BranchResolved 3422156 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 485997 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 157495514 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 3691335 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 2603397 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 83950162 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 10012692 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 74490237 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 62673576 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 20855725 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 146846377 # Number of instructions processed by rename
-system.cpu.rename.SquashedInsts 950168 # Number of squashed instructions processed by rename
-system.cpu.rename.ROBFullEvents 437835 # Number of times rename has blocked due to ROB full
+system.cpu.decode.BranchMispred 485996 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 157495015 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 3691306 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 2603375 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 83949795 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 10013130 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 74489960 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 62673363 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 20855728 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 146845952 # Number of instructions processed by rename
+system.cpu.rename.SquashedInsts 950144 # Number of squashed instructions processed by rename
+system.cpu.rename.ROBFullEvents 437842 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 62734 # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents 16405 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 18093431 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 150531293 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 678956016 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 164473250 # Number of integer rename lookups
+system.cpu.rename.SQFullEvents 18093439 # Number of times rename has blocked due to SQ full
+system.cpu.rename.RenamedOperands 150530803 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 678954009 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 164472740 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10951 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 141875837 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 8655453 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 2847783 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 2651540 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 13851138 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 26418180 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 21304101 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1686584 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2099607 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 143580968 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.rename.CommittedMaps 141875467 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 8655333 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 2847772 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 2651529 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 13851116 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 26418132 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 21304063 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1686589 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2099460 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 143580575 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 2120859 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 143376402 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 269122 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 6250831 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 14651334 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqInstsIssued 143376028 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 269119 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 6250781 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 14651223 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 125281 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 254585789 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::samples 254585351 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 0.563175 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 0.882138 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 166208039 65.29% 65.29% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 45306668 17.80% 83.08% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 31957154 12.55% 95.63% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 10300319 4.05% 99.68% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 813576 0.32% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 166207835 65.29% 65.29% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 45306594 17.80% 83.08% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 31956972 12.55% 95.63% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 10300343 4.05% 99.68% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 813574 0.32% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 254585789 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 254585351 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 7371881 32.63% 32.63% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 7371879 32.63% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 5631992 24.93% 57.56% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 9586808 42.44% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 5632028 24.93% 57.56% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 9586948 42.44% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 96038375 66.98% 66.99% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 113990 0.08% 67.06% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 96038086 66.98% 66.98% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 113978 0.08% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 26201034 18.27% 85.34% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 21012076 14.66% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 26200986 18.27% 85.34% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 21012051 14.66% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 143376402 # Type of FU issued
+system.cpu.iq.FU_type_0::total 143376028 # Type of FU issued
system.cpu.iq.rate 0.550285 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 22590713 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.157562 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 564162773 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 151957708 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 140260829 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fu_busy_cnt 22590887 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.157564 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 564161758 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 151957264 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 140260479 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 35655 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 13185 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 165941427 # Number of integer alu accesses
+system.cpu.iq.int_alu_accesses 165941227 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 23351 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 324400 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread0.forwLoads 324401 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 1489874 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 18272 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 701019 # Number of stores squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 18271 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 701002 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 87957 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 6348 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 2603397 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 948146 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 290514 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 145902754 # Number of instructions dispatched to IQ
+system.cpu.iew.iewSquashCycles 2603375 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 948323 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 290944 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 145902361 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 26418180 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 21304101 # Number of dispatched store instructions
+system.cpu.iew.iewDispLoadInsts 26418132 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 21304063 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1096021 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 17856 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 255642 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 18272 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 317514 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 471623 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 789137 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 142433961 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 25800026 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 872747 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewLSQFullEvents 256072 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 18271 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 317509 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 471618 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 789127 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 142433599 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 25799978 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 872737 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 200927 # number of nop insts executed
-system.cpu.iew.exec_refs 46682620 # number of memory reference insts executed
-system.cpu.iew.exec_branches 26544157 # Number of branches executed
-system.cpu.iew.exec_stores 20882594 # Number of stores executed
+system.cpu.iew.exec_refs 46682549 # number of memory reference insts executed
+system.cpu.iew.exec_branches 26544085 # Number of branches executed
+system.cpu.iew.exec_stores 20882571 # Number of stores executed
system.cpu.iew.exec_rate 0.546668 # Inst execution rate
-system.cpu.iew.wb_sent 142046877 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 140272260 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 63301722 # num instructions producing a value
-system.cpu.iew.wb_consumers 95887432 # num instructions consuming a value
+system.cpu.iew.wb_sent 142046516 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 140271910 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 63301578 # num instructions producing a value
+system.cpu.iew.wb_consumers 95887209 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 0.538371 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.660167 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 7592023 # The number of squashed insts skipped by commit
+system.cpu.commit.commitSquashedInsts 7591975 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1995578 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 755013 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 251649482 # Number of insts commited each cycle
+system.cpu.commit.branchMispredicts 755003 # The number of times a branch was mispredicted
+system.cpu.commit.committed_per_cycle::samples 251649065 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 0.546262 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.145558 # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::stdev 1.145555 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 178084591 70.77% 70.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 43398091 17.25% 88.01% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 15481937 6.15% 94.16% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 4357709 1.73% 95.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 178084267 70.77% 70.77% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 43398054 17.25% 88.01% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 15481884 6.15% 94.16% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 4357721 1.73% 95.90% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 6462022 2.57% 98.46% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1589348 0.63% 99.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 777595 0.31% 99.40% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 414354 0.16% 99.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 1083835 0.43% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1589357 0.63% 99.10% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 777637 0.31% 99.40% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 414343 0.16% 99.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 1083780 0.43% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 251649482 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 113359982 # Number of instructions committed
-system.cpu.commit.committedOps 137466648 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 251649065 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 113359701 # Number of instructions committed
+system.cpu.commit.committedOps 137466321 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 45531388 # Number of memory references committed
-system.cpu.commit.loads 24928306 # Number of loads committed
+system.cpu.commit.refs 45531319 # Number of memory references committed
+system.cpu.commit.loads 24928258 # Number of loads committed
system.cpu.commit.membars 814674 # Number of memory barriers committed
-system.cpu.commit.branches 26060542 # Number of branches committed
+system.cpu.commit.branches 26060472 # Number of branches committed
system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 120282409 # Number of committed integer instructions.
-system.cpu.commit.function_calls 4896404 # Number of function calls committed.
+system.cpu.commit.int_insts 120282111 # Number of committed integer instructions.
+system.cpu.commit.function_calls 4896381 # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 91813673 66.79% 66.79% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 112998 0.08% 66.87% # Class of committed instruction
+system.cpu.commit.op_class_0::IntAlu 91813423 66.79% 66.79% # Class of committed instruction
+system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 24928306 18.13% 85.01% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 20603082 14.99% 100.00% # Class of committed instruction
+system.cpu.commit.op_class_0::MemRead 24928258 18.13% 85.01% # Class of committed instruction
+system.cpu.commit.op_class_0::MemWrite 20603061 14.99% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 137466648 # Class of committed instruction
-system.cpu.commit.bw_lim_events 1083835 # number cycles where commit BW limit reached
+system.cpu.commit.op_class_0::total 137466321 # Class of committed instruction
+system.cpu.commit.bw_lim_events 1083780 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 373371044 # The number of ROB reads
-system.cpu.rob.rob_writes 293051212 # The number of ROB writes
-system.cpu.timesIdled 892832 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 5963427 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 5393139488 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 113205077 # Number of Instructions Simulated
-system.cpu.committedOps 137311743 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi 2.301568 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.301568 # CPI: Total CPI of All Threads
+system.cpu.rob.rob_reads 373370450 # The number of ROB reads
+system.cpu.rob.rob_writes 293050441 # The number of ROB writes
+system.cpu.timesIdled 892831 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 5963517 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 5393139836 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 113204796 # Number of Instructions Simulated
+system.cpu.committedOps 137311416 # Number of Ops (including micro ops) Simulated
+system.cpu.cpi 2.301571 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 2.301571 # CPI: Total CPI of All Threads
system.cpu.ipc 0.434486 # IPC: Instructions Per Cycle
system.cpu.ipc_total 0.434486 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 155870959 # number of integer regfile reads
-system.cpu.int_regfile_writes 88663005 # number of integer regfile writes
+system.cpu.int_regfile_reads 155870535 # number of integer regfile reads
+system.cpu.int_regfile_writes 88662743 # number of integer regfile writes
system.cpu.fp_regfile_reads 9591 # number of floating regfile reads
system.cpu.fp_regfile_writes 2716 # number of floating regfile writes
-system.cpu.cc_regfile_reads 503160195 # number of cc regfile reads
-system.cpu.cc_regfile_writes 53196607 # number of cc regfile writes
-system.cpu.misc_regfile_reads 444137179 # number of misc regfile reads
+system.cpu.cc_regfile_reads 503158959 # number of cc regfile reads
+system.cpu.cc_regfile_writes 53196475 # number of cc regfile writes
+system.cpu.misc_regfile_reads 444136009 # number of misc regfile reads
system.cpu.misc_regfile_writes 1521560 # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq 2564960 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2564895 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 695414 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795107 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495169 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128721 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 6450177 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121298256 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349665 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215436 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 219910025 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 65488 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3561861 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 3525412 98.98% 98.98% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3561861 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 2502933529 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2849443906 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1334434109 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 74884707 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 1894038 # number of replacements
-system.cpu.icache.tags.tagsinuse 511.373814 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 64256715 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1894550 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 33.916611 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 13186180250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 511.373814 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.998777 # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements 837744 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 40170152 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 838256 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 47.921103 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 179419983 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 179419983 # Number of data accesses
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+system.cpu.dcache.ReadReq_hits::total 23329792 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 15588565 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 15588565 # number of WriteReq hits
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+system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits
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+system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits
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+system.cpu.dcache.demand_hits::total 38918357 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 39265000 # number of overall hits
+system.cpu.dcache.overall_hits::total 39265000 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 700458 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 700458 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 3573865 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 3573865 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 4274323 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 4274323 # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total 4451395 # number of overall misses
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+system.cpu.dcache.ReadReq_miss_latency::total 9897569146 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 135184782788 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 135184782788 # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357043749 # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total 357043749 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 145082351934 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 145082351934 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 145082351934 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 145082351934 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 24030250 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 24030250 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 19162430 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 19162430 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 43192680 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 43192680 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 43716395 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 43716395 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.186504 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.101824 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.139346 # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.139346 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37825.934328 # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::total 37825.934328 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.918609 # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.918609 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33942.767529 # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::total 33942.767529 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32592.558498 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::total 32592.558498 # average overall miss latency
+system.cpu.dcache.blocked_cycles::no_mshrs 504099 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.762558 # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 695413 # number of writebacks
+system.cpu.dcache.writebacks::total 695413 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286304 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 286304 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274603 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 3274603 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3560907 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3560907 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3560907 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3560907 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414154 # number of ReadReq MSHR misses
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59949.508241 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59949.508241 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59954.587219 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59954.587219 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 64394.736842 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 64464.285714 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62595.130635 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60568.605205 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60806.328545 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62575.460107 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60573.515637 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60808.361852 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 837746 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.958486 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 40170226 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 838258 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 47.921077 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.958486 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 179420309 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 179420309 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 23329838 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23329838 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 15588593 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 15588593 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 346643 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 346643 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 441991 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 441991 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460300 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460300 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 38918431 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 38918431 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 39265074 # number of overall hits
-system.cpu.dcache.overall_hits::total 39265074 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 700462 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 700462 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 3573868 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 3573868 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 177072 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 177072 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 26735 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 26735 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 4274330 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 4274330 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 4451402 # number of overall misses
-system.cpu.dcache.overall_misses::total 4451402 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 9897949646 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 9897949646 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 135180567288 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 135180567288 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 357044249 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 357044249 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 91502 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 91502 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 145078516934 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 145078516934 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 145078516934 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 145078516934 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 24030300 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 24030300 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19162461 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19162461 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 523715 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 523715 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468726 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 468726 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 460305 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 460305 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 43192761 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 43192761 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 43716476 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 43716476 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029149 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.029149 # miss rate for ReadReq accesses
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-system.cpu.dcache.WriteReq_miss_rate::total 0.186504 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.338108 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.338108 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057038 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057038 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.098959 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.098959 # miss rate for demand accesses
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-system.cpu.dcache.overall_miss_rate::total 0.101824 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14130.601868 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14130.601868 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37824.723042 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 37824.723042 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13354.937311 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13354.937311 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 18300.400000 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 18300.400000 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 33941.814725 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 33941.814725 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 32591.645718 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 32591.645718 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 503676 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 6928 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 72.701501 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 695414 # number of writebacks
-system.cpu.dcache.writebacks::total 695414 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 286306 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 286306 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3274606 # number of WriteReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::total 3274606 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18411 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 18411 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 3560912 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 3560912 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 3560912 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 3560912 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414156 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 414156 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299262 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 299262 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119306 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 119306 # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8324 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses::total 832724 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5342017166 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5342017166 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11883030705 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 11883030705 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1479647251 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1479647251 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 110184750 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 110184750 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 81498 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 81498 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17225047871 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 17225047871 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18704695122 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 18704695122 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792723750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792723750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440457953 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440457953 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233181703 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233181703 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017235 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017235 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015617 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015617 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227807 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227807 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017759 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017759 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016517 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.016517 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019048 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.019048 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12898.562778 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12898.562778 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39707.783497 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39707.783497 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12402.119349 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12402.119349 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13236.995435 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13236.995435 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 16299.600000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 16299.600000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24144.397634 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 24144.397634 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22462.058404 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 22462.058404 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 2564949 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2564884 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 695413 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36229 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2767 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2772 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 296625 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 296625 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795093 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495164 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31180 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128717 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 6450154 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121297808 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98349473 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 46668 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 215428 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 219909377 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 65488 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 3561849 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 5.010233 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.100640 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 3525400 98.98% 98.98% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::6 36449 1.02% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 3561849 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2502926529 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 235500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 2849434655 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 1334430859 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 19518240 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 74882707 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 30181 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30181 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326556349 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36779263 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36410 # number of replacements
system.iocache.tags.tagsinuse 0.999676 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.overall_avg_mshr_miss_latency::realview.ide 68024.440909 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 68024.440909 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 67834 # Transaction distribution
+system.membus.trans_dist::ReadResp 67833 # Transaction distribution
+system.membus.trans_dist::WriteReq 27608 # Transaction distribution
+system.membus.trans_dist::WriteResp 27608 # Transaction distribution
+system.membus.trans_dist::Writeback 90626 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4543 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4545 # Transaction distribution
+system.membus.trans_dist::ReadExReq 135127 # Transaction distribution
+system.membus.trans_dist::ReadExResp 135127 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452777 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560413 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72683 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72683 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 633096 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16658216 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16821681 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19140977 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 205 # Total snoops (count)
+system.membus.snoop_fanout::samples 300222 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 300222 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 300222 # Request fanout histogram
+system.membus.reqLayer0.occupancy 94200000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 1697000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1357984749 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1678025205 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38219737 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 2.817969 # Number of seconds simulated
-sim_ticks 2817968959500 # Number of ticks simulated
-final_tick 2817968959500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.817967 # Number of seconds simulated
+sim_ticks 2817967230500 # Number of ticks simulated
+final_tick 2817967230500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 311387 # Simulator instruction rate (inst/s)
-host_op_rate 378101 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 6951332904 # Simulator tick rate (ticks/s)
-host_mem_usage 560824 # Number of bytes of host memory used
-host_seconds 405.39 # Real time elapsed on the host
-sim_insts 126231916 # Number of instructions simulated
-sim_ops 153276567 # Number of ops (including micro ops) simulated
+host_inst_rate 295085 # Simulator instruction rate (inst/s)
+host_op_rate 358305 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6587585543 # Simulator tick rate (ticks/s)
+host_mem_usage 567284 # Number of bytes of host memory used
+host_seconds 427.77 # Real time elapsed on the host
+sim_insts 126228232 # Number of instructions simulated
+sim_ops 153272049 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 652900 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4386464 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 652964 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4386528 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 130944 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 1051396 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 6080 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.inst 516160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu2.data 4232384 # Number of bytes read from this memory
-system.physmem.bytes_read::total 10977672 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 652900 # Number of instructions bytes read from this memory
+system.physmem.bytes_read::cpu2.inst 516736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2.data 4232960 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 10978952 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 652964 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 130944 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu2.inst 516160 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1300004 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 5945344 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_inst_read::cpu2.inst 516736 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1300644 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 5946048 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8281204 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8281908 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 18655 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 69057 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 18656 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 69058 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 2046 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 16429 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 95 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.inst 8065 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu2.data 66131 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 180499 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 92896 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu2.inst 8074 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2.data 66140 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 180519 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 92907 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 133501 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 133512 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 231692 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1556605 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 231715 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1556628 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 46468 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 373104 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 2158 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.inst 183167 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu2.data 1501927 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 3895597 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 231692 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.inst 183372 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2.data 1502132 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 3896054 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 231715 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 46468 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu2.inst 183167 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 461327 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2109798 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 822697 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu2.inst 183372 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 461554 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2110049 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2938714 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2109798 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 823038 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 822698 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2938965 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2110049 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 231692 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1562821 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 231715 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1562844 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 46468 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 373107 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 2158 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.inst 183167 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu2.data 1501927 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 6834311 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 92768 # Number of read requests accepted
-system.physmem.writeReqs 67796 # Number of write requests accepted
-system.physmem.readBursts 92768 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 67796 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 5932800 # Total number of bytes read from DRAM
+system.physmem.bw_total::cpu2.inst 183372 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2.data 1502132 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 823039 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 6835019 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 92786 # Number of read requests accepted
+system.physmem.writeReqs 67811 # Number of write requests accepted
+system.physmem.readBursts 92786 # Number of DRAM read bursts, including those serviced by the write queue
+system.physmem.writeBursts 67811 # Number of DRAM write bursts, including those merged in the write queue
+system.physmem.bytesReadDRAM 5933952 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 4352 # Total number of bytes read from write queue
-system.physmem.bytesWritten 4337152 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 5937092 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 4338824 # Total written bytes from the system interface side
+system.physmem.bytesWritten 4338688 # Total number of bytes written to DRAM
+system.physmem.bytesReadSys 5938244 # Total read bytes from the system interface side
+system.physmem.bytesWrittenSys 4339784 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 68 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 2466 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 6044 # Per bank write bursts
-system.physmem.perBankRdBursts::1 5813 # Per bank write bursts
-system.physmem.perBankRdBursts::2 5577 # Per bank write bursts
-system.physmem.perBankRdBursts::3 6085 # Per bank write bursts
-system.physmem.perBankRdBursts::4 5556 # Per bank write bursts
-system.physmem.perBankRdBursts::5 5466 # Per bank write bursts
-system.physmem.perBankRdBursts::6 6173 # Per bank write bursts
-system.physmem.perBankRdBursts::7 6793 # Per bank write bursts
-system.physmem.perBankRdBursts::8 6458 # Per bank write bursts
-system.physmem.perBankRdBursts::9 6393 # Per bank write bursts
+system.physmem.neitherReadNorWriteReqs 2462 # Number of requests that are neither read nor write
+system.physmem.perBankRdBursts::0 6041 # Per bank write bursts
+system.physmem.perBankRdBursts::1 5815 # Per bank write bursts
+system.physmem.perBankRdBursts::2 5576 # Per bank write bursts
+system.physmem.perBankRdBursts::3 6089 # Per bank write bursts
+system.physmem.perBankRdBursts::4 5555 # Per bank write bursts
+system.physmem.perBankRdBursts::5 5469 # Per bank write bursts
+system.physmem.perBankRdBursts::6 6176 # Per bank write bursts
+system.physmem.perBankRdBursts::7 6795 # Per bank write bursts
+system.physmem.perBankRdBursts::8 6466 # Per bank write bursts
+system.physmem.perBankRdBursts::9 6395 # Per bank write bursts
system.physmem.perBankRdBursts::10 5737 # Per bank write bursts
-system.physmem.perBankRdBursts::11 5119 # Per bank write bursts
-system.physmem.perBankRdBursts::12 5308 # Per bank write bursts
+system.physmem.perBankRdBursts::11 5121 # Per bank write bursts
+system.physmem.perBankRdBursts::12 5306 # Per bank write bursts
system.physmem.perBankRdBursts::13 5463 # Per bank write bursts
-system.physmem.perBankRdBursts::14 5329 # Per bank write bursts
-system.physmem.perBankRdBursts::15 5386 # Per bank write bursts
-system.physmem.perBankWrBursts::0 4258 # Per bank write bursts
-system.physmem.perBankWrBursts::1 3939 # Per bank write bursts
-system.physmem.perBankWrBursts::2 4228 # Per bank write bursts
-system.physmem.perBankWrBursts::3 4685 # Per bank write bursts
-system.physmem.perBankWrBursts::4 4137 # Per bank write bursts
+system.physmem.perBankRdBursts::14 5326 # Per bank write bursts
+system.physmem.perBankRdBursts::15 5388 # Per bank write bursts
+system.physmem.perBankWrBursts::0 4259 # Per bank write bursts
+system.physmem.perBankWrBursts::1 3941 # Per bank write bursts
+system.physmem.perBankWrBursts::2 4227 # Per bank write bursts
+system.physmem.perBankWrBursts::3 4690 # Per bank write bursts
+system.physmem.perBankWrBursts::4 4139 # Per bank write bursts
system.physmem.perBankWrBursts::5 4140 # Per bank write bursts
-system.physmem.perBankWrBursts::6 4393 # Per bank write bursts
-system.physmem.perBankWrBursts::7 4905 # Per bank write bursts
-system.physmem.perBankWrBursts::8 4554 # Per bank write bursts
-system.physmem.perBankWrBursts::9 4640 # Per bank write bursts
-system.physmem.perBankWrBursts::10 4209 # Per bank write bursts
-system.physmem.perBankWrBursts::11 3550 # Per bank write bursts
-system.physmem.perBankWrBursts::12 4025 # Per bank write bursts
+system.physmem.perBankWrBursts::6 4396 # Per bank write bursts
+system.physmem.perBankWrBursts::7 4907 # Per bank write bursts
+system.physmem.perBankWrBursts::8 4559 # Per bank write bursts
+system.physmem.perBankWrBursts::9 4641 # Per bank write bursts
+system.physmem.perBankWrBursts::10 4210 # Per bank write bursts
+system.physmem.perBankWrBursts::11 3556 # Per bank write bursts
+system.physmem.perBankWrBursts::12 4023 # Per bank write bursts
system.physmem.perBankWrBursts::13 4273 # Per bank write bursts
-system.physmem.perBankWrBursts::14 3934 # Per bank write bursts
-system.physmem.perBankWrBursts::15 3898 # Per bank write bursts
+system.physmem.perBankWrBursts::14 3931 # Per bank write bursts
+system.physmem.perBankWrBursts::15 3900 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
-system.physmem.totGap 2816402817000 # Total gap between requests
+system.physmem.totGap 2816401088000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 1 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 92767 # Read request sizes (log2)
+system.physmem.readPktSize::6 92785 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 67794 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 61106 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 28126 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 2948 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 515 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 67809 # Write request sizes (log2)
+system.physmem.rdQLenPdf::0 61124 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 28127 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 2946 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 516 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 1103 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 1433 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 1108 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 1440 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 2578 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 3235 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 3367 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 3811 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 3969 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 4287 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 4633 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 5129 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 4765 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 4457 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 4164 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 4227 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 3503 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 3412 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 3490 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 3324 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 3366 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 3812 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 3970 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 4286 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::26 4458 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 4166 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 4221 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 3504 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 3413 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 3495 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::32 3325 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 138 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 132 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 32855 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 312.580247 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 179.443796 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 339.847473 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 12759 38.83% 38.83% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 7721 23.50% 62.33% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 2992 9.11% 71.44% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 1702 5.18% 76.62% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 1346 4.10% 80.72% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 768 2.34% 83.06% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 529 1.61% 84.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 557 1.70% 86.36% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 4481 13.64% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 32855 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 3254 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 28.483712 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 540.107069 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-1023 3253 99.97% 99.97% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 32876 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 312.458450 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 179.413676 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 339.664106 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 12770 38.84% 38.84% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 7721 23.49% 62.33% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 2991 9.10% 71.43% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 1712 5.21% 76.63% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 1344 4.09% 80.72% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 774 2.35% 83.08% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 537 1.63% 84.71% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 552 1.68% 86.39% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 4475 13.61% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 32876 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 3255 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 28.482642 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 540.024143 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-1023 3254 99.97% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 3254 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 3254 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 20.826060 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.875262 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 13.591008 # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 3255 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 3255 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.827035 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.877074 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 13.588559 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::4-7 2 0.06% 0.18% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 2712 83.34% 83.65% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 41 1.26% 84.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 34 1.04% 85.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 139 4.27% 90.23% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 131 4.03% 94.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 2714 83.38% 83.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 41 1.26% 84.95% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 32 0.98% 85.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 140 4.30% 90.23% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 131 4.02% 94.25% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::36-39 8 0.25% 94.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::40-43 4 0.12% 94.62% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::44-47 9 0.28% 94.90% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::48-51 18 0.55% 95.45% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 3 0.09% 95.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 3 0.09% 95.55% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::56-59 7 0.22% 95.76% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::60-63 4 0.12% 95.88% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::64-67 99 3.04% 98.92% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 3254 # Writes before turning the bus around for reads
-system.physmem.totQLat 1185318250 # Total ticks spent queuing
-system.physmem.totMemAccLat 2923443250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 463500000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 12786.60 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 3255 # Writes before turning the bus around for reads
+system.physmem.totQLat 1187084500 # Total ticks spent queuing
+system.physmem.totMemAccLat 2925547000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 463590000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 12803.17 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 31536.60 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 31553.17 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 8.01 # Average write queue length when enqueuing
-system.physmem.readRowHits 76736 # Number of row buffer hits during reads
-system.physmem.writeRowHits 50876 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.78 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 75.04 # Row buffer hit rate for writes
-system.physmem.avgGap 17540686.69 # Average gap between requests
+system.physmem.readRowHits 76742 # Number of row buffer hits during reads
+system.physmem.writeRowHits 50891 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.77 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes
+system.physmem.avgGap 17537071.60 # Average gap between requests
system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2704844337250 # Time in different power states
-system.physmem.memoryStateTime::REF 94098160000 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2704795503250 # Time in different power states
+system.physmem.memoryStateTime::REF 94097900000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 19026368250 # Time in different power states
+system.physmem.memoryStateTime::ACT 19068171250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 129865680 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 118518120 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 70859250 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 64667625 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 370554600 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 352489800 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 224758800 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 214377840 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 184056000960 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 184056000960 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 70810447635 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 69981022395 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1628666801250 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1629394367250 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1884329288175 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1884181443990 # Total energy per rank (pJ)
-system.physmem.averagePower::0 668.683537 # Core power per rank (mW)
-system.physmem.averagePower::1 668.631072 # Core power per rank (mW)
+system.physmem.actEnergy::0 130016880 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 118525680 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 70941750 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 64671750 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 370624800 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 352544400 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 224849520 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 214442640 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 184055492400 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 184055492400 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 70844118390 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 70005569445 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1628632585500 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1629368154750 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1884328629240 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1884179401065 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.685154 # Core power per rank (mW)
+system.physmem.averagePower::1 668.632198 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 74236 # Transaction distribution
-system.membus.trans_dist::ReadResp 74235 # Transaction distribution
-system.membus.trans_dist::WriteReq 27571 # Transaction distribution
-system.membus.trans_dist::WriteResp 27571 # Transaction distribution
-system.membus.trans_dist::Writeback 92896 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4548 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4551 # Transaction distribution
-system.membus.trans_dist::ReadExReq 137042 # Transaction distribution
-system.membus.trans_dist::ReadExResp 137042 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471729 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 579191 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 652018 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16939580 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 17102699 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19429163 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 125 # Total snoops (count)
-system.membus.snoop_fanout::samples 304844 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 304844 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 304844 # Request fanout histogram
-system.membus.reqLayer0.occupancy 40698500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 463500 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 735391250 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 906935534 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 23918727 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 100821 # number of replacements
-system.l2c.tags.tagsinuse 65118.790980 # Cycle average of tags in use
-system.l2c.tags.total_refs 2895106 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 166061 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 17.433991 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 49797.187018 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939323 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 5291.837037 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 2854.503750 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969196 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 1121.421966 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 949.242692 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.966166 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst 3505.210474 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data 1537.513263 # Average occupied blocks per requestor
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-system.l2c.Writeback_hits::writebacks 692569 # number of Writeback hits
-system.l2c.Writeback_hits::total 692569 # number of Writeback hits
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-system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.035036 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000688 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008179 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.146403 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003451 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011817 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu2.data 0.204977 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.035036 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62166.504854 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67896.710660 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 64160.635671 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.159475 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.840782 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57672.973994 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62404.844551 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 61531.793832 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58366.378558 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 62017.036557 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59968.597263 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58366.378558 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63753.657327 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62776.769599 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 62017.036557 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 2443720 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2443717 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 692569 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2771 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2786 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 296449 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 296449 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3616607 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484136 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29317 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88397 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 6218457 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115187256 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97908723 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49396 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 156136 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 213301511 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 51755 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3431770 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 5.010631 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.102558 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 3395286 98.94% 98.94% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3431770 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 2368040184 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 4200557665 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 2014921824 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 11880425 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 39622630 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 30188 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30188 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
-system.iobus.trans_dist::WriteResp 45563 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 14476225 # DTB read hits
-system.cpu0.dtb.read_misses 4878 # DTB read misses
-system.cpu0.dtb.write_hits 11074159 # DTB write hits
-system.cpu0.dtb.write_misses 931 # DTB write misses
+system.cpu0.dtb.read_hits 14476193 # DTB read hits
+system.cpu0.dtb.read_misses 4879 # DTB read misses
+system.cpu0.dtb.write_hits 11073999 # DTB write hits
+system.cpu0.dtb.write_misses 930 # DTB write misses
system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 3272 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 947 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 946 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 215 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 14481103 # DTB read accesses
-system.cpu0.dtb.write_accesses 11075090 # DTB write accesses
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system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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system.cpu0.dtb.misses 5809 # DTB misses
-system.cpu0.dtb.accesses 25556193 # DTB accesses
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system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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-system.cpu0.itb.inst_misses 2810 # ITB inst misses
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system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 67957442 # ITB inst accesses
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-system.cpu0.itb.accesses 67957442 # DTB accesses
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.num_fp_alu_accesses 5582 # Number of float alu accesses
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system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read
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-system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.508688 # Average occupied blocks per requestor
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-system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13727.065401 # average ReadReq miss latency
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-system.cpu0.icache.overall_avg_miss_latency::total 7271.922440 # average overall miss latency
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+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
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system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11923 # average StoreCondReq mshr miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
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system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
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system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
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system.cpu1.dtb.inst_misses 0 # ITB inst misses
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system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
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system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
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system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
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system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
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system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
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system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
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system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written
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-system.cpu1.num_cc_register_writes 9370916 # number of times the CC registers were written
-system.cpu1.num_mem_refs 8126078 # number of memory refs
-system.cpu1.num_load_insts 4682102 # Number of load instructions
-system.cpu1.num_store_insts 3443976 # Number of store instructions
-system.cpu1.num_idle_cycles 151526719.153884 # Number of idle cycles
-system.cpu1.num_busy_cycles 6485898.846116 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.041047 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.958953 # Percentage of idle cycles
-system.cpu1.Branches 5257577 # Number of branches fetched
+system.cpu1.num_cc_register_reads 92377254 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 9370530 # number of times the CC registers were written
+system.cpu1.num_mem_refs 8126107 # number of memory refs
+system.cpu1.num_load_insts 4682037 # Number of load instructions
+system.cpu1.num_store_insts 3444070 # Number of store instructions
+system.cpu1.num_idle_cycles 151526887.882406 # Number of idle cycles
+system.cpu1.num_busy_cycles 6485809.117594 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.041046 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.958954 # Percentage of idle cycles
+system.cpu1.Branches 5257446 # Number of branches fetched
system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 17988055 68.83% 68.83% # Class of executed instruction
-system.cpu1.op_class::IntMult 19009 0.07% 68.90% # Class of executed instruction
+system.cpu1.op_class::IntAlu 17987711 68.83% 68.83% # Class of executed instruction
+system.cpu1.op_class::IntMult 19014 0.07% 68.90% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 1153 0.00% 68.91% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 1154 0.00% 68.91% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.91% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.91% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.91% # Class of executed instruction
-system.cpu1.op_class::MemRead 4682102 17.92% 86.82% # Class of executed instruction
-system.cpu1.op_class::MemWrite 3443976 13.18% 100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead 4682037 17.92% 86.82% # Class of executed instruction
+system.cpu1.op_class::MemWrite 3444070 13.18% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 26134331 # Class of executed instruction
+system.cpu1.op_class::total 26134022 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu2.branchPred.lookups 17411527 # Number of BP lookups
-system.cpu2.branchPred.condPredicted 9465637 # Number of conditional branches predicted
-system.cpu2.branchPred.condIncorrect 400782 # Number of conditional branches incorrect
-system.cpu2.branchPred.BTBLookups 10870560 # Number of BTB lookups
-system.cpu2.branchPred.BTBHits 8144126 # Number of BTB hits
+system.cpu2.branchPred.lookups 17408373 # Number of BP lookups
+system.cpu2.branchPred.condPredicted 9463731 # Number of conditional branches predicted
+system.cpu2.branchPred.condIncorrect 400017 # Number of conditional branches incorrect
+system.cpu2.branchPred.BTBLookups 10864152 # Number of BTB lookups
+system.cpu2.branchPred.BTBHits 8142904 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu2.branchPred.BTBHitPct 74.919103 # BTB Hit Percentage
-system.cpu2.branchPred.usedRAS 4071344 # Number of times the RAS was used to get a target.
-system.cpu2.branchPred.RASInCorrect 21284 # Number of incorrect RAS predictions.
+system.cpu2.branchPred.BTBHitPct 74.952044 # BTB Hit Percentage
+system.cpu2.branchPred.usedRAS 4071247 # Number of times the RAS was used to get a target.
+system.cpu2.branchPred.RASInCorrect 21277 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
-system.cpu2.dtb.read_hits 9691496 # DTB read hits
-system.cpu2.dtb.read_misses 37543 # DTB read misses
-system.cpu2.dtb.write_hits 7160478 # DTB write hits
-system.cpu2.dtb.write_misses 5658 # DTB write misses
+system.cpu2.dtb.read_hits 9689518 # DTB read hits
+system.cpu2.dtb.read_misses 37575 # DTB read misses
+system.cpu2.dtb.write_hits 7159699 # DTB write hits
+system.cpu2.dtb.write_misses 5670 # DTB write misses
system.cpu2.dtb.flush_tlb 181 # Number of times complete TLB was flushed
-system.cpu2.dtb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA
+system.cpu2.dtb.flush_tlb_mva 370 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 2438 # Number of entries that have been flushed from TLB
-system.cpu2.dtb.align_faults 429 # Number of TLB faults due to alignment restrictions
-system.cpu2.dtb.prefetch_faults 958 # Number of TLB faults due to prefetch
+system.cpu2.dtb.align_faults 439 # Number of TLB faults due to alignment restrictions
+system.cpu2.dtb.prefetch_faults 968 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.dtb.perms_faults 432 # Number of TLB faults due to permissions restrictions
-system.cpu2.dtb.read_accesses 9729039 # DTB read accesses
-system.cpu2.dtb.write_accesses 7166136 # DTB write accesses
+system.cpu2.dtb.perms_faults 417 # Number of TLB faults due to permissions restrictions
+system.cpu2.dtb.read_accesses 9727093 # DTB read accesses
+system.cpu2.dtb.write_accesses 7165369 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu2.dtb.hits 16851974 # DTB hits
-system.cpu2.dtb.misses 43201 # DTB misses
-system.cpu2.dtb.accesses 16895175 # DTB accesses
+system.cpu2.dtb.hits 16849217 # DTB hits
+system.cpu2.dtb.misses 43245 # DTB misses
+system.cpu2.dtb.accesses 16892462 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu2.itb.inst_hits 12855360 # ITB inst hits
-system.cpu2.itb.inst_misses 6344 # ITB inst misses
+system.cpu2.itb.inst_hits 12852348 # ITB inst hits
+system.cpu2.itb.inst_misses 6327 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 181 # Number of times complete TLB was flushed
-system.cpu2.itb.flush_tlb_mva 371 # Number of times TLB was flushed by MVA
+system.cpu2.itb.flush_tlb_mva 370 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu2.itb.flush_entries 1760 # Number of entries that have been flushed from TLB
+system.cpu2.itb.flush_entries 1763 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu2.itb.perms_faults 1117 # Number of TLB faults due to permissions restrictions
+system.cpu2.itb.perms_faults 1147 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
-system.cpu2.itb.inst_accesses 12861704 # ITB inst accesses
-system.cpu2.itb.hits 12855360 # DTB hits
-system.cpu2.itb.misses 6344 # DTB misses
-system.cpu2.itb.accesses 12861704 # DTB accesses
-system.cpu2.numCycles 69831868 # number of cpu cycles simulated
+system.cpu2.itb.inst_accesses 12858675 # ITB inst accesses
+system.cpu2.itb.hits 12852348 # DTB hits
+system.cpu2.itb.misses 6327 # DTB misses
+system.cpu2.itb.accesses 12858675 # DTB accesses
+system.cpu2.numCycles 69828422 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu2.fetch.icacheStallCycles 26744179 # Number of cycles fetch is stalled on an Icache miss
-system.cpu2.fetch.Insts 69131561 # Number of instructions fetch has processed
-system.cpu2.fetch.Branches 17411527 # Number of branches that fetch encountered
-system.cpu2.fetch.predictedBranches 12215470 # Number of branches that fetch has predicted taken
-system.cpu2.fetch.Cycles 39628211 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu2.fetch.SquashCycles 2071717 # Number of cycles fetch has spent squashing
-system.cpu2.fetch.TlbCycles 92420 # Number of cycles fetch has spent waiting for tlb
-system.cpu2.fetch.MiscStallCycles 879 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu2.fetch.PendingDrainCycles 271 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu2.fetch.PendingTrapStallCycles 329715 # Number of stall cycles due to pending traps
-system.cpu2.fetch.PendingQuiesceStallCycles 101746 # Number of stall cycles due to pending quiesce instructions
-system.cpu2.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR
-system.cpu2.fetch.CacheLines 12853833 # Number of cache lines fetched
-system.cpu2.fetch.IcacheSquashes 270796 # Number of outstanding Icache misses that were squashed
-system.cpu2.fetch.ItlbSquashes 2796 # Number of outstanding ITLB misses that were squashed
-system.cpu2.fetch.rateDist::samples 67933721 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::mean 1.223102 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::stdev 2.347801 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.icacheStallCycles 26736882 # Number of cycles fetch is stalled on an Icache miss
+system.cpu2.fetch.Insts 69116574 # Number of instructions fetch has processed
+system.cpu2.fetch.Branches 17408373 # Number of branches that fetch encountered
+system.cpu2.fetch.predictedBranches 12214151 # Number of branches that fetch has predicted taken
+system.cpu2.fetch.Cycles 39634943 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu2.fetch.SquashCycles 2070237 # Number of cycles fetch has spent squashing
+system.cpu2.fetch.TlbCycles 91943 # Number of cycles fetch has spent waiting for tlb
+system.cpu2.fetch.MiscStallCycles 882 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu2.fetch.PendingDrainCycles 273 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu2.fetch.PendingTrapStallCycles 329325 # Number of stall cycles due to pending traps
+system.cpu2.fetch.PendingQuiesceStallCycles 101475 # Number of stall cycles due to pending quiesce instructions
+system.cpu2.fetch.IcacheWaitRetryStallCycles 454 # Number of stall cycles due to full MSHR
+system.cpu2.fetch.CacheLines 12850788 # Number of cache lines fetched
+system.cpu2.fetch.IcacheSquashes 270289 # Number of outstanding Icache misses that were squashed
+system.cpu2.fetch.ItlbSquashes 2773 # Number of outstanding ITLB misses that were squashed
+system.cpu2.fetch.rateDist::samples 67931271 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::mean 1.222867 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::stdev 2.347613 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::0 49353657 72.65% 72.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::1 2396253 3.53% 76.18% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::2 1562027 2.30% 78.48% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::3 4874890 7.18% 85.65% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::4 1103608 1.62% 87.28% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::5 705498 1.04% 88.32% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::6 3873607 5.70% 94.02% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::7 752096 1.11% 95.12% # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::8 3312085 4.88% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::0 49354668 72.65% 72.65% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::1 2396025 3.53% 76.18% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::2 1561758 2.30% 78.48% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::3 4875455 7.18% 85.66% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::4 1102436 1.62% 87.28% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::5 704861 1.04% 88.32% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::6 3873045 5.70% 94.02% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::7 751493 1.11% 95.13% # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.rateDist::8 3311530 4.87% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.rateDist::total 67933721 # Number of instructions fetched each cycle (Total)
-system.cpu2.fetch.branchRate 0.249335 # Number of branch fetches per cycle
-system.cpu2.fetch.rate 0.989972 # Number of inst fetches per cycle
-system.cpu2.decode.IdleCycles 18652988 # Number of cycles decode is idle
-system.cpu2.decode.BlockedCycles 36886196 # Number of cycles decode is blocked
-system.cpu2.decode.RunCycles 10385899 # Number of cycles decode is running
-system.cpu2.decode.UnblockCycles 1080677 # Number of cycles decode is unblocking
-system.cpu2.decode.SquashCycles 927745 # Number of cycles decode is squashing
-system.cpu2.decode.BranchResolved 1311847 # Number of times decode resolved a branch
-system.cpu2.decode.BranchMispred 109670 # Number of times decode detected a branch misprediction
-system.cpu2.decode.DecodedInsts 59354899 # Number of instructions handled by decode
-system.cpu2.decode.SquashedInsts 355527 # Number of squashed instructions handled by decode
-system.cpu2.rename.SquashCycles 927745 # Number of cycles rename is squashing
-system.cpu2.rename.IdleCycles 19278335 # Number of cycles rename is idle
-system.cpu2.rename.BlockCycles 4338170 # Number of cycles rename is blocking
-system.cpu2.rename.serializeStallCycles 27085326 # count of cycles rename stalled for serializing inst
-system.cpu2.rename.RunCycles 10827974 # Number of cycles rename is running
-system.cpu2.rename.UnblockCycles 5475942 # Number of cycles rename is unblocking
-system.cpu2.rename.RenamedInsts 56886251 # Number of instructions processed by rename
-system.cpu2.rename.ROBFullEvents 2445 # Number of times rename has blocked due to ROB full
-system.cpu2.rename.IQFullEvents 940623 # Number of times rename has blocked due to IQ full
-system.cpu2.rename.LQFullEvents 160571 # Number of times rename has blocked due to LQ full
-system.cpu2.rename.SQFullEvents 3871890 # Number of times rename has blocked due to SQ full
-system.cpu2.rename.RenamedOperands 58826776 # Number of destination operands rename has renamed
-system.cpu2.rename.RenameLookups 261240527 # Number of register rename lookups that rename has made
-system.cpu2.rename.int_rename_lookups 63795075 # Number of integer rename lookups
-system.cpu2.rename.fp_rename_lookups 4266 # Number of floating rename lookups
-system.cpu2.rename.CommittedMaps 48699577 # Number of HB maps that are committed
-system.cpu2.rename.UndoneMaps 10127183 # Number of HB maps that are undone due to squashing
-system.cpu2.rename.serializingInsts 954335 # count of serializing insts renamed
-system.cpu2.rename.tempSerializingInsts 890664 # count of temporary serializing insts renamed
-system.cpu2.rename.skidInsts 6273875 # count of insts added to the skid buffer
-system.cpu2.memDep0.insertedLoads 10281967 # Number of loads inserted to the mem dependence unit.
-system.cpu2.memDep0.insertedStores 7932177 # Number of stores inserted to the mem dependence unit.
-system.cpu2.memDep0.conflictingLoads 1385446 # Number of conflicting loads.
-system.cpu2.memDep0.conflictingStores 1932065 # Number of conflicting stores.
-system.cpu2.iq.iqInstsAdded 54651944 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu2.iq.iqNonSpecInstsAdded 672234 # Number of non-speculative instructions added to the IQ
-system.cpu2.iq.iqInstsIssued 52014227 # Number of instructions issued
-system.cpu2.iq.iqSquashedInstsIssued 68047 # Number of squashed instructions issued
-system.cpu2.iq.iqSquashedInstsExamined 7311472 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu2.iq.iqSquashedOperandsExamined 18464419 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu2.iq.iqSquashedNonSpecRemoved 69301 # Number of squashed non-spec instructions that were removed
-system.cpu2.iq.issued_per_cycle::samples 67933721 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::mean 0.765661 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::stdev 1.467889 # Number of insts issued each cycle
+system.cpu2.fetch.rateDist::total 67931271 # Number of instructions fetched each cycle (Total)
+system.cpu2.fetch.branchRate 0.249302 # Number of branch fetches per cycle
+system.cpu2.fetch.rate 0.989806 # Number of inst fetches per cycle
+system.cpu2.decode.IdleCycles 18645308 # Number of cycles decode is idle
+system.cpu2.decode.BlockedCycles 36894831 # Number of cycles decode is blocked
+system.cpu2.decode.RunCycles 10382963 # Number of cycles decode is running
+system.cpu2.decode.UnblockCycles 1080745 # Number of cycles decode is unblocking
+system.cpu2.decode.SquashCycles 927203 # Number of cycles decode is squashing
+system.cpu2.decode.BranchResolved 1311099 # Number of times decode resolved a branch
+system.cpu2.decode.BranchMispred 109436 # Number of times decode detected a branch misprediction
+system.cpu2.decode.DecodedInsts 59339671 # Number of instructions handled by decode
+system.cpu2.decode.SquashedInsts 354865 # Number of squashed instructions handled by decode
+system.cpu2.rename.SquashCycles 927203 # Number of cycles rename is squashing
+system.cpu2.rename.IdleCycles 19270411 # Number of cycles rename is idle
+system.cpu2.rename.BlockCycles 4356096 # Number of cycles rename is blocking
+system.cpu2.rename.serializeStallCycles 27085706 # count of cycles rename stalled for serializing inst
+system.cpu2.rename.RunCycles 10825258 # Number of cycles rename is running
+system.cpu2.rename.UnblockCycles 5466363 # Number of cycles rename is unblocking
+system.cpu2.rename.RenamedInsts 56871138 # Number of instructions processed by rename
+system.cpu2.rename.ROBFullEvents 2407 # Number of times rename has blocked due to ROB full
+system.cpu2.rename.IQFullEvents 944494 # Number of times rename has blocked due to IQ full
+system.cpu2.rename.LQFullEvents 157128 # Number of times rename has blocked due to LQ full
+system.cpu2.rename.SQFullEvents 3862497 # Number of times rename has blocked due to SQ full
+system.cpu2.rename.RenamedOperands 58808456 # Number of destination operands rename has renamed
+system.cpu2.rename.RenameLookups 261172418 # Number of register rename lookups that rename has made
+system.cpu2.rename.int_rename_lookups 63777133 # Number of integer rename lookups
+system.cpu2.rename.fp_rename_lookups 4183 # Number of floating rename lookups
+system.cpu2.rename.CommittedMaps 48694532 # Number of HB maps that are committed
+system.cpu2.rename.UndoneMaps 10113908 # Number of HB maps that are undone due to squashing
+system.cpu2.rename.serializingInsts 954202 # count of serializing insts renamed
+system.cpu2.rename.tempSerializingInsts 890607 # count of temporary serializing insts renamed
+system.cpu2.rename.skidInsts 6274956 # count of insts added to the skid buffer
+system.cpu2.memDep0.insertedLoads 10279229 # Number of loads inserted to the mem dependence unit.
+system.cpu2.memDep0.insertedStores 7930666 # Number of stores inserted to the mem dependence unit.
+system.cpu2.memDep0.conflictingLoads 1385426 # Number of conflicting loads.
+system.cpu2.memDep0.conflictingStores 1931872 # Number of conflicting stores.
+system.cpu2.iq.iqInstsAdded 54639620 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu2.iq.iqNonSpecInstsAdded 672070 # Number of non-speculative instructions added to the IQ
+system.cpu2.iq.iqInstsIssued 52007794 # Number of instructions issued
+system.cpu2.iq.iqSquashedInstsIssued 68359 # Number of squashed instructions issued
+system.cpu2.iq.iqSquashedInstsExamined 7304876 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu2.iq.iqSquashedOperandsExamined 18433205 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu2.iq.iqSquashedNonSpecRemoved 69298 # Number of squashed non-spec instructions that were removed
+system.cpu2.iq.issued_per_cycle::samples 67931271 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::mean 0.765594 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::stdev 1.467899 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::0 47467313 69.87% 69.87% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::1 6842474 10.07% 79.95% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::2 5093799 7.50% 87.44% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::3 4189990 6.17% 93.61% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::4 1618046 2.38% 95.99% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::5 1073354 1.58% 97.57% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::6 1126537 1.66% 99.23% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::7 361655 0.53% 99.76% # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::8 160553 0.24% 100.00% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::0 47467453 69.88% 69.88% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::1 6844404 10.08% 79.95% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::2 5089744 7.49% 87.44% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::3 4188713 6.17% 93.61% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::4 1618102 2.38% 95.99% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::5 1074322 1.58% 97.57% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::6 1126267 1.66% 99.23% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::7 361985 0.53% 99.76% # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::8 160281 0.24% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu2.iq.issued_per_cycle::total 67933721 # Number of insts issued each cycle
+system.cpu2.iq.issued_per_cycle::total 67931271 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntAlu 78426 9.72% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntMult 1 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.72% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemRead 375416 46.53% 56.25% # attempts to use FU when none available
-system.cpu2.iq.fu_full::MemWrite 353014 43.75% 100.00% # attempts to use FU when none available
+system.cpu2.iq.fu_full::IntAlu 78971 9.77% 9.77% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.77% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.77% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.77% # attempts to use FU when none available
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+system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.77% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemRead 376071 46.54% 56.32% # attempts to use FU when none available
+system.cpu2.iq.fu_full::MemWrite 352950 43.68% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 108 0.00% 0.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntAlu 34458488 66.25% 66.25% # Type of FU issued
-system.cpu2.iq.FU_type_0::IntMult 39234 0.08% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntAlu 34454774 66.25% 66.25% # Type of FU issued
+system.cpu2.iq.FU_type_0::IntMult 39220 0.08% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 66.32% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.32% # Type of FU issued
-system.cpu2.iq.FU_type_0::SimdFloatMisc 2870 0.01% 66.33% # Type of FU issued
+system.cpu2.iq.FU_type_0::SimdFloatMisc 2865 0.01% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemRead 9974787 19.18% 85.51% # Type of FU issued
-system.cpu2.iq.FU_type_0::MemWrite 7538730 14.49% 100.00% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemRead 9972711 19.18% 85.51% # Type of FU issued
+system.cpu2.iq.FU_type_0::MemWrite 7538110 14.49% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu2.iq.FU_type_0::total 52014227 # Type of FU issued
-system.cpu2.iq.rate 0.744849 # Inst issue rate
-system.cpu2.iq.fu_busy_cnt 806857 # FU busy when requested
-system.cpu2.iq.fu_busy_rate 0.015512 # FU busy rate (busy events/executed inst)
-system.cpu2.iq.int_inst_queue_reads 172827620 # Number of integer instruction queue reads
-system.cpu2.iq.int_inst_queue_writes 62668492 # Number of integer instruction queue writes
-system.cpu2.iq.int_inst_queue_wakeup_accesses 50413992 # Number of integer instruction queue wakeup accesses
-system.cpu2.iq.fp_inst_queue_reads 9459 # Number of floating instruction queue reads
-system.cpu2.iq.fp_inst_queue_writes 4970 # Number of floating instruction queue writes
-system.cpu2.iq.fp_inst_queue_wakeup_accesses 4171 # Number of floating instruction queue wakeup accesses
-system.cpu2.iq.int_alu_accesses 52815881 # Number of integer alu accesses
-system.cpu2.iq.fp_alu_accesses 5095 # Number of floating point alu accesses
-system.cpu2.iew.lsq.thread0.forwLoads 266821 # Number of loads that had data forwarded from stores
+system.cpu2.iq.FU_type_0::total 52007794 # Type of FU issued
+system.cpu2.iq.rate 0.744794 # Inst issue rate
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+system.cpu2.iq.fu_busy_rate 0.015536 # FU busy rate (busy events/executed inst)
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+system.cpu2.iq.int_inst_queue_writes 62649489 # Number of integer instruction queue writes
+system.cpu2.iq.int_inst_queue_wakeup_accesses 50408450 # Number of integer instruction queue wakeup accesses
+system.cpu2.iq.fp_inst_queue_reads 9401 # Number of floating instruction queue reads
+system.cpu2.iq.fp_inst_queue_writes 4928 # Number of floating instruction queue writes
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+system.cpu2.iq.int_alu_accesses 52810613 # Number of integer alu accesses
+system.cpu2.iq.fp_alu_accesses 5066 # Number of floating point alu accesses
+system.cpu2.iew.lsq.thread0.forwLoads 267388 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu2.iew.lsq.thread0.squashedLoads 1614154 # Number of loads squashed
-system.cpu2.iew.lsq.thread0.ignoredResponses 1912 # Number of memory responses ignored because the instruction is squashed
-system.cpu2.iew.lsq.thread0.memOrderViolation 38579 # Number of memory ordering violations
-system.cpu2.iew.lsq.thread0.squashedStores 795080 # Number of stores squashed
+system.cpu2.iew.lsq.thread0.squashedLoads 1612297 # Number of loads squashed
+system.cpu2.iew.lsq.thread0.ignoredResponses 1915 # Number of memory responses ignored because the instruction is squashed
+system.cpu2.iew.lsq.thread0.memOrderViolation 38614 # Number of memory ordering violations
+system.cpu2.iew.lsq.thread0.squashedStores 794248 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu2.iew.lsq.thread0.rescheduledLoads 131168 # Number of loads that were rescheduled
-system.cpu2.iew.lsq.thread0.cacheBlocked 122536 # Number of times an access to memory failed due to the cache being blocked
+system.cpu2.iew.lsq.thread0.rescheduledLoads 131416 # Number of loads that were rescheduled
+system.cpu2.iew.lsq.thread0.cacheBlocked 121570 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu2.iew.iewSquashCycles 927745 # Number of cycles IEW is squashing
-system.cpu2.iew.iewBlockCycles 3243473 # Number of cycles IEW is blocking
-system.cpu2.iew.iewUnblockCycles 928988 # Number of cycles IEW is unblocking
-system.cpu2.iew.iewDispatchedInsts 55431586 # Number of instructions dispatched to IQ
-system.cpu2.iew.iewDispSquashedInsts 93653 # Number of squashed instructions skipped by dispatch
-system.cpu2.iew.iewDispLoadInsts 10281967 # Number of dispatched load instructions
-system.cpu2.iew.iewDispStoreInsts 7932177 # Number of dispatched store instructions
-system.cpu2.iew.iewDispNonSpecInsts 359829 # Number of dispatched non-speculative instructions
-system.cpu2.iew.iewIQFullEvents 34343 # Number of times the IQ has become full, causing a stall
-system.cpu2.iew.iewLSQFullEvents 885724 # Number of times the LSQ has become full, causing a stall
-system.cpu2.iew.memOrderViolationEvents 38579 # Number of memory order violations
-system.cpu2.iew.predictedTakenIncorrect 184691 # Number of branches that were predicted taken incorrectly
-system.cpu2.iew.predictedNotTakenIncorrect 163240 # Number of branches that were predicted not taken incorrectly
-system.cpu2.iew.branchMispredicts 347931 # Number of branch mispredicts detected at execute
-system.cpu2.iew.iewExecutedInsts 51578613 # Number of executed instructions
-system.cpu2.iew.iewExecLoadInsts 9798052 # Number of load instructions executed
-system.cpu2.iew.iewExecSquashedInsts 392517 # Number of squashed instructions skipped in execute
+system.cpu2.iew.iewSquashCycles 927203 # Number of cycles IEW is squashing
+system.cpu2.iew.iewBlockCycles 3248790 # Number of cycles IEW is blocking
+system.cpu2.iew.iewUnblockCycles 940039 # Number of cycles IEW is unblocking
+system.cpu2.iew.iewDispatchedInsts 55419045 # Number of instructions dispatched to IQ
+system.cpu2.iew.iewDispSquashedInsts 93730 # Number of squashed instructions skipped by dispatch
+system.cpu2.iew.iewDispLoadInsts 10279229 # Number of dispatched load instructions
+system.cpu2.iew.iewDispStoreInsts 7930666 # Number of dispatched store instructions
+system.cpu2.iew.iewDispNonSpecInsts 359745 # Number of dispatched non-speculative instructions
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+system.cpu2.iew.iewLSQFullEvents 896292 # Number of times the LSQ has become full, causing a stall
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+system.cpu2.iew.predictedTakenIncorrect 184316 # Number of branches that were predicted taken incorrectly
+system.cpu2.iew.predictedNotTakenIncorrect 163000 # Number of branches that were predicted not taken incorrectly
+system.cpu2.iew.branchMispredicts 347316 # Number of branch mispredicts detected at execute
+system.cpu2.iew.iewExecutedInsts 51571999 # Number of executed instructions
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+system.cpu2.iew.iewExecSquashedInsts 392652 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
-system.cpu2.iew.exec_nop 107408 # number of nop insts executed
-system.cpu2.iew.exec_refs 17263080 # number of memory reference insts executed
-system.cpu2.iew.exec_branches 9489180 # Number of branches executed
-system.cpu2.iew.exec_stores 7465028 # Number of stores executed
-system.cpu2.iew.exec_rate 0.738611 # Inst execution rate
-system.cpu2.iew.wb_sent 51120326 # cumulative count of insts sent to commit
-system.cpu2.iew.wb_count 50418163 # cumulative count of insts written-back
-system.cpu2.iew.wb_producers 26486298 # num instructions producing a value
-system.cpu2.iew.wb_consumers 46021805 # num instructions consuming a value
+system.cpu2.iew.exec_nop 107355 # number of nop insts executed
+system.cpu2.iew.exec_refs 17260233 # number of memory reference insts executed
+system.cpu2.iew.exec_branches 9488063 # Number of branches executed
+system.cpu2.iew.exec_stores 7464201 # Number of stores executed
+system.cpu2.iew.exec_rate 0.738553 # Inst execution rate
+system.cpu2.iew.wb_sent 51114762 # cumulative count of insts sent to commit
+system.cpu2.iew.wb_count 50412593 # cumulative count of insts written-back
+system.cpu2.iew.wb_producers 26484469 # num instructions producing a value
+system.cpu2.iew.wb_consumers 46017701 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu2.iew.wb_rate 0.721994 # insts written-back per cycle
-system.cpu2.iew.wb_fanout 0.575516 # average fanout of values written-back
+system.cpu2.iew.wb_rate 0.721949 # insts written-back per cycle
+system.cpu2.iew.wb_fanout 0.575528 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu2.commit.commitSquashedInsts 8152826 # The number of squashed insts skipped by commit
-system.cpu2.commit.commitNonSpecStalls 602933 # The number of times commit has been forced to stall to communicate backwards
-system.cpu2.commit.branchMispredicts 292644 # The number of times a branch was mispredicted
-system.cpu2.commit.committed_per_cycle::samples 66207639 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::mean 0.713967 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::stdev 1.618930 # Number of insts commited each cycle
+system.cpu2.commit.commitSquashedInsts 8145270 # The number of squashed insts skipped by commit
+system.cpu2.commit.commitNonSpecStalls 602772 # The number of times commit has been forced to stall to communicate backwards
+system.cpu2.commit.branchMispredicts 292077 # The number of times a branch was mispredicted
+system.cpu2.commit.committed_per_cycle::samples 66207003 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::mean 0.713906 # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::stdev 1.618708 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::0 48127363 72.69% 72.69% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::1 8089014 12.22% 84.91% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::2 3990999 6.03% 90.94% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::3 1725382 2.61% 93.54% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::4 875466 1.32% 94.87% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::5 621285 0.94% 95.80% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::6 1255109 1.90% 97.70% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::7 300211 0.45% 98.15% # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::8 1222810 1.85% 100.00% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::0 48127722 72.69% 72.69% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::1 8087932 12.22% 84.91% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::2 3990373 6.03% 90.94% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::3 1725495 2.61% 93.54% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::4 876020 1.32% 94.87% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::5 623327 0.94% 95.81% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::6 1254839 1.90% 97.70% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::7 299711 0.45% 98.15% # Number of insts commited each cycle
+system.cpu2.commit.committed_per_cycle::8 1221584 1.85% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu2.commit.committed_per_cycle::total 66207639 # Number of insts commited each cycle
-system.cpu2.commit.committedInsts 38915831 # Number of instructions committed
-system.cpu2.commit.committedOps 47270058 # Number of ops (including micro ops) committed
+system.cpu2.commit.committed_per_cycle::total 66207003 # Number of insts commited each cycle
+system.cpu2.commit.committedInsts 38912247 # Number of instructions committed
+system.cpu2.commit.committedOps 47265561 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu2.commit.refs 15804910 # Number of memory references committed
-system.cpu2.commit.loads 8667813 # Number of loads committed
-system.cpu2.commit.membars 226604 # Number of memory barriers committed
-system.cpu2.commit.branches 8912074 # Number of branches committed
-system.cpu2.commit.fp_insts 4128 # Number of committed floating point instructions.
-system.cpu2.commit.int_insts 41368724 # Number of committed integer instructions.
-system.cpu2.commit.function_calls 1635579 # Number of function calls committed.
+system.cpu2.commit.refs 15803350 # Number of memory references committed
+system.cpu2.commit.loads 8666932 # Number of loads committed
+system.cpu2.commit.membars 226535 # Number of memory barriers committed
+system.cpu2.commit.branches 8911403 # Number of branches committed
+system.cpu2.commit.fp_insts 4112 # Number of committed floating point instructions.
+system.cpu2.commit.int_insts 41364475 # Number of committed integer instructions.
+system.cpu2.commit.function_calls 1635441 # Number of function calls committed.
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntAlu 31424362 66.48% 66.48% # Class of committed instruction
-system.cpu2.commit.op_class_0::IntMult 37916 0.08% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntAlu 31421440 66.48% 66.48% # Class of committed instruction
+system.cpu2.commit.op_class_0::IntMult 37906 0.08% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::SimdFloatMisc 2870 0.01% 66.56% # Class of committed instruction
+system.cpu2.commit.op_class_0::SimdFloatMisc 2865 0.01% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemRead 8667813 18.34% 84.90% # Class of committed instruction
-system.cpu2.commit.op_class_0::MemWrite 7137097 15.10% 100.00% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemRead 8666932 18.34% 84.90% # Class of committed instruction
+system.cpu2.commit.op_class_0::MemWrite 7136418 15.10% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu2.commit.op_class_0::total 47270058 # Class of committed instruction
-system.cpu2.commit.bw_lim_events 1222810 # number cycles where commit BW limit reached
+system.cpu2.commit.op_class_0::total 47265561 # Class of committed instruction
+system.cpu2.commit.bw_lim_events 1221584 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu2.rob.rob_reads 113043839 # The number of ROB reads
-system.cpu2.rob.rob_writes 112575250 # The number of ROB writes
-system.cpu2.timesIdled 280666 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu2.idleCycles 1898147 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu2.rob.rob_reads 113032454 # The number of ROB reads
+system.cpu2.rob.rob_writes 112549271 # The number of ROB writes
+system.cpu2.timesIdled 280538 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu2.idleCycles 1897151 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 5250079706 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu2.committedInsts 38852054 # Number of Instructions Simulated
-system.cpu2.committedOps 47206281 # Number of Ops (including micro ops) Simulated
-system.cpu2.cpi 1.797379 # CPI: Cycles Per Instruction
-system.cpu2.cpi_total 1.797379 # CPI: Total CPI of All Threads
-system.cpu2.ipc 0.556366 # IPC: Instructions Per Cycle
-system.cpu2.ipc_total 0.556366 # IPC: Total IPC of All Threads
-system.cpu2.int_regfile_reads 56467494 # number of integer regfile reads
-system.cpu2.int_regfile_writes 31953659 # number of integer regfile writes
-system.cpu2.fp_regfile_reads 15852 # number of floating regfile reads
-system.cpu2.fp_regfile_writes 13698 # number of floating regfile writes
-system.cpu2.cc_regfile_reads 182453688 # number of cc regfile reads
-system.cpu2.cc_regfile_writes 19285573 # number of cc regfile writes
-system.cpu2.misc_regfile_reads 124185765 # number of misc regfile reads
-system.cpu2.misc_regfile_writes 483246 # number of misc regfile writes
+system.cpu2.committedInsts 38848410 # Number of Instructions Simulated
+system.cpu2.committedOps 47201724 # Number of Ops (including micro ops) Simulated
+system.cpu2.cpi 1.797459 # CPI: Cycles Per Instruction
+system.cpu2.cpi_total 1.797459 # CPI: Total CPI of All Threads
+system.cpu2.ipc 0.556341 # IPC: Instructions Per Cycle
+system.cpu2.ipc_total 0.556341 # IPC: Total IPC of All Threads
+system.cpu2.int_regfile_reads 56460891 # number of integer regfile reads
+system.cpu2.int_regfile_writes 31949429 # number of integer regfile writes
+system.cpu2.fp_regfile_reads 15783 # number of floating regfile reads
+system.cpu2.fp_regfile_writes 13692 # number of floating regfile writes
+system.cpu2.cc_regfile_reads 182431289 # number of cc regfile reads
+system.cpu2.cc_regfile_writes 19284860 # number of cc regfile writes
+system.cpu2.misc_regfile_reads 124219174 # number of misc regfile reads
+system.cpu2.misc_regfile_writes 483131 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 30188 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30188 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
+system.iobus.trans_dist::WriteResp 45563 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
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+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
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+system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
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+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
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+system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks)
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+system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks)
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+system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks)
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+system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks)
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+system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36442 # number of replacements
-system.iocache.tags.tagsinuse 0.992778 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 0.992769 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 0.992778 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.062049 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.062049 # Average percentage of cache occupancy
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
system.iocache.overall_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.tags.replacements 100842 # number of replacements
+system.l2c.tags.tagsinuse 65118.786988 # Cycle average of tags in use
+system.l2c.tags.total_refs 2894514 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 166082 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 17.428222 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.l2c.tags.occ_blocks::cpu1.data 949.240769 # Average occupied blocks per requestor
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+system.l2c.tags.occ_blocks::cpu2.inst 3505.217048 # Average occupied blocks per requestor
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+system.l2c.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 3121 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::3 8094 # Occupied blocks per task id
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+system.l2c.ReadReq_hits::total 2346260 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 692581 # number of Writeback hits
+system.l2c.Writeback_hits::total 692581 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
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+system.l2c.demand_hits::cpu1.inst 248185 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 97288 # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu2.inst 674046 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data 259480 # number of demand (read+write) hits
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+system.l2c.ReadReq_mshr_miss_latency::cpu2.data 308547996 # number of ReadReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10646564 # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total 14336933 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
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+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3894067274 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 4708045278 # number of ReadExReq MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu1.data 974422504 # number of demand (read+write) MSHR miss cycles
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+system.l2c.demand_mshr_miss_latency::cpu2.data 4202615270 # number of demand (read+write) MSHR miss cycles
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+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 943135000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1581115000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 2524250000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 723317000 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1233415500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 1956732500 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1666452000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2814530500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 4480982500 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008176 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.032029 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003461 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011838 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021867 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.007283 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989276 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.962896 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.516955 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.076923 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.066667 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420176 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.525318 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.257990 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000687 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008176 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.146372 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003461 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011838 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.204982 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.035049 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000687 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008176 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.146372 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003461 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011838 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.204982 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.035049 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62308.543689 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67932.187583 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 64142.652936 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.169173 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.838102 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57700.290919 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62432.939043 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 61559.974346 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58411.611557 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62806.217981 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 62037.180604 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58411.611557 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62806.217981 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 62037.180604 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 74258 # Transaction distribution
+system.membus.trans_dist::ReadResp 74257 # Transaction distribution
+system.membus.trans_dist::WriteReq 27571 # Transaction distribution
+system.membus.trans_dist::WriteResp 27571 # Transaction distribution
+system.membus.trans_dist::Writeback 92907 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4549 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4552 # Transaction distribution
+system.membus.trans_dist::ReadExReq 137040 # Transaction distribution
+system.membus.trans_dist::ReadExResp 137040 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471782 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 579244 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 652071 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16941564 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 17104683 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 19431147 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 125 # Total snoops (count)
+system.membus.snoop_fanout::samples 304876 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 304876 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 304876 # Request fanout histogram
+system.membus.reqLayer0.occupancy 40704500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 459000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 735607750 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 907107038 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 23918727 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 2443155 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2443152 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 692581 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2772 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 296442 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 296442 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3615657 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484160 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29265 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88229 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 6217311 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115156920 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97909811 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49244 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155812 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 213271787 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 51771 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3431211 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.010633 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.102567 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 3394727 98.94% 98.94% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3431211 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 2367804213 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 4198919632 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 2015022352 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 11862428 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 39524153 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- Begin Simulation Statistics ----------
-sim_seconds 2.804327 # Number of seconds simulated
-sim_ticks 2804326619500 # Number of ticks simulated
-final_tick 2804326619500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.804324 # Number of seconds simulated
+sim_ticks 2804324203000 # Number of ticks simulated
+final_tick 2804324203000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 119116 # Simulator instruction rate (inst/s)
-host_op_rate 144575 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2855979889 # Simulator tick rate (ticks/s)
-host_mem_usage 563896 # Number of bytes of host memory used
-host_seconds 981.91 # Real time elapsed on the host
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+host_tick_rate 2777671240 # Simulator tick rate (ticks/s)
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+host_seconds 1009.60 # Real time elapsed on the host
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system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
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-system.realview.nvmem.bytes_read::total 640 # Number of bytes read from this memory
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-system.realview.nvmem.bw_total::total 228 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.dtb.walker 4416 # Number of bytes read from this memory
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system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
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system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.dtb.walker 1575 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::cpu0.data 6246 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.dtb.walker 1575 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.perBankWrBursts::6 8974 # Per bank write bursts
system.physmem.perBankWrBursts::7 8818 # Per bank write bursts
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-system.physmem.perBankWrBursts::11 7398 # Per bank write bursts
-system.physmem.perBankWrBursts::12 7887 # Per bank write bursts
-system.physmem.perBankWrBursts::13 8744 # Per bank write bursts
-system.physmem.perBankWrBursts::14 8046 # Per bank write bursts
-system.physmem.perBankWrBursts::15 7629 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 14 # Number of times write queue was full causing retry
-system.physmem.totGap 2804326433500 # Total gap between requests
+system.physmem.numWrRetry 3 # Number of times write queue was full causing retry
+system.physmem.totGap 2804324017000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 541 # Read request sizes (log2)
system.physmem.readPktSize::3 14 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 175100 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 4381 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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-system.physmem.wrQLenPdf::3 93 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 92 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 90 # What write queue length does an incoming req see
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-system.physmem.wrQLenPdf::63 31 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 64866 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 303.665033 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 178.572173 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 327.227913 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 24436 37.67% 37.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 15780 24.33% 62.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6593 10.16% 72.16% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3751 5.78% 77.95% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2794 4.31% 82.25% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1520 2.34% 84.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 1090 1.68% 86.28% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1132 1.75% 88.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7770 11.98% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 64866 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 6698 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 26.205584 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 477.627003 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 6695 99.96% 99.96% # Reads before turning the bus around for writes
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+system.physmem.wrQLenPdf::8 88 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::10 86 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::41 126 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see
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+system.physmem.wrQLenPdf::44 129 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::46 121 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::47 120 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::49 112 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::52 82 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::53 66 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::54 55 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::55 47 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::56 51 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::57 51 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::58 42 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::59 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::60 23 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see
+system.physmem.bytesPerActivate::samples 64783 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 303.989874 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 178.723316 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 327.460023 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 24407 37.68% 37.68% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 15776 24.35% 62.03% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 6538 10.09% 72.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3738 5.77% 77.89% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2814 4.34% 82.23% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1507 2.33% 84.56% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 1107 1.71% 86.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1104 1.70% 87.97% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7792 12.03% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 64783 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 6707 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 26.165350 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::stdev 477.307058 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::0-2047 6704 99.96% 99.96% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-8191 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::36864-38911 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6698 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 6698 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.743804 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.225845 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 11.527754 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::0-3 13 0.19% 0.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::4-7 9 0.13% 0.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::8-11 4 0.06% 0.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::12-15 9 0.13% 0.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 5778 86.26% 86.79% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 106 1.58% 88.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 43 0.64% 89.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 223 3.33% 92.34% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 204 3.05% 95.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 17 0.25% 95.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 22 0.33% 95.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 15 0.22% 96.19% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 32 0.48% 96.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 10 0.15% 96.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 8 0.12% 96.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 5 0.07% 97.01% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 143 2.13% 99.15% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 6 0.09% 99.24% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 3 0.04% 99.28% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 6 0.09% 99.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 10 0.15% 99.52% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 5 0.07% 99.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 4 0.06% 99.67% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 1 0.01% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 3 0.04% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 3 0.04% 99.78% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 3 0.04% 99.82% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 2 0.03% 99.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 1 0.01% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6698 # Writes before turning the bus around for reads
-system.physmem.totQLat 2733630250 # Total ticks spent queuing
-system.physmem.totMemAccLat 6024836500 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 877655000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 15573.49 # Average queueing delay per DRAM burst
+system.physmem.rdPerTurnAround::total 6707 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6707 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 19.712092 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.230918 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.181787 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::0-3 16 0.24% 0.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::4-7 7 0.10% 0.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::8-11 4 0.06% 0.40% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::12-15 9 0.13% 0.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5755 85.81% 86.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 109 1.63% 87.97% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 46 0.69% 88.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 238 3.55% 92.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 224 3.34% 95.54% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 22 0.33% 95.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 23 0.34% 96.21% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 7 0.10% 96.32% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 31 0.46% 96.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 2 0.03% 96.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 4 0.06% 96.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 8 0.12% 96.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 152 2.27% 99.25% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 3 0.04% 99.30% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 5 0.07% 99.37% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 12 0.18% 99.55% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.01% 99.57% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 2 0.03% 99.60% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::96-99 13 0.19% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::104-107 1 0.01% 99.81% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 4 0.06% 99.87% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 4 0.06% 99.93% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 5 0.07% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6707 # Writes before turning the bus around for reads
+system.physmem.totQLat 2727699250 # Total ticks spent queuing
+system.physmem.totMemAccLat 6018343000 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 877505000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 15542.36 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 34323.49 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 34292.36 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.01 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.02 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.00 # Average system read bandwidth in MiByte/s
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.63 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 10.73 # Average write queue length when enqueuing
-system.physmem.readRowHits 145110 # Number of row buffer hits during reads
-system.physmem.writeRowHits 97798 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 82.67 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 73.94 # Row buffer hit rate for writes
-system.physmem.avgGap 8994250.74 # Average gap between requests
-system.physmem.pageHitRate 78.92 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2678438745750 # Time in different power states
+system.physmem.avgWrQLen 10.66 # Average write queue length when enqueuing
+system.physmem.readRowHits 145124 # Number of row buffer hits during reads
+system.physmem.writeRowHits 97802 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 82.69 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 73.96 # Row buffer hit rate for writes
+system.physmem.avgGap 8995685.58 # Average gap between requests
+system.physmem.pageHitRate 78.94 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2678459999250 # Time in different power states
system.physmem.memoryStateTime::REF 93642380000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 32245482750 # Time in different power states
+system.physmem.memoryStateTime::ACT 32221812750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 259141680 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 231245280 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 141396750 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 126175500 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 715486200 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 653647800 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 447269040 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 409672080 # Energy for write commands per rank (pJ)
+system.physmem.actEnergy::0 259096320 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 230663160 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 141372000 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 125857875 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 715533000 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 653367000 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 447210720 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 409503600 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 183164495280 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 183164495280 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 77839312860 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 76923425745 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1614311544000 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1615114953750 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1876878645810 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1876623615435 # Total energy per rank (pJ)
-system.physmem.averagePower::0 669.281339 # Core power per rank (mW)
-system.physmem.averagePower::1 669.190397 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 68041 # Transaction distribution
-system.membus.trans_dist::ReadResp 68040 # Transaction distribution
-system.membus.trans_dist::WriteReq 27608 # Transaction distribution
-system.membus.trans_dist::WriteResp 27608 # Transaction distribution
-system.membus.trans_dist::Writeback 95531 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4632 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 26 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4658 # Transaction distribution
-system.membus.trans_dist::ReadExReq 138441 # Transaction distribution
-system.membus.trans_dist::ReadExResp 138441 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 20 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 464888 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 572528 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72712 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72712 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 645240 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 640 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17339160 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 17503137 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 19822433 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 234 # Total snoops (count)
-system.membus.snoop_fanout::samples 311110 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 311110 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 311110 # Request fanout histogram
-system.membus.reqLayer0.occupancy 81518499 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 15812 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1693000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1434327498 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1730433594 # Layer occupancy (ticks)
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system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
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-system.toL2Bus.trans_dist::ReadResp 2655239 # Transaction distribution
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-system.toL2Bus.trans_dist::ReadExResp 296877 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891298 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533043 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42437 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169072 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 6635850 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124513216 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99808865 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 65120 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 293032 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 224680233 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 69343 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3662983 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 5.009961 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.099307 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 3626496 99.00% 99.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 36487 1.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3662983 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 4670881246 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 8762800197 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3909656420 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 26229350 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 96621860 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 30210 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30210 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59030 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq 8 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 326627644 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36841042 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu0.branchPred.lookups 27349422 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 14250256 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 549515 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 17066610 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 12886962 # Number of BTB hits
+system.cpu0.branchPred.lookups 27347795 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 14227638 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 549324 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 17049849 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 12874628 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 75.509794 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 6758521 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 30298 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 75.511683 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 6769747 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 30174 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 14278108 # DTB read hits
-system.cpu0.dtb.read_misses 49273 # DTB read misses
-system.cpu0.dtb.write_hits 10337716 # DTB write hits
-system.cpu0.dtb.write_misses 7471 # DTB write misses
+system.cpu0.dtb.read_hits 14276180 # DTB read hits
+system.cpu0.dtb.read_misses 49315 # DTB read misses
+system.cpu0.dtb.write_hits 10339289 # DTB write hits
+system.cpu0.dtb.write_misses 7532 # DTB write misses
system.cpu0.dtb.flush_tlb 178 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 473 # Number of times TLB was flushed by MVA
+system.cpu0.dtb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3414 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 948 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1297 # Number of TLB faults due to prefetch
+system.cpu0.dtb.flush_entries 3434 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.align_faults 1022 # Number of TLB faults due to alignment restrictions
+system.cpu0.dtb.prefetch_faults 1284 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 559 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 14327381 # DTB read accesses
-system.cpu0.dtb.write_accesses 10345187 # DTB write accesses
+system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 14325495 # DTB read accesses
+system.cpu0.dtb.write_accesses 10346821 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 24615824 # DTB hits
-system.cpu0.dtb.misses 56744 # DTB misses
-system.cpu0.dtb.accesses 24672568 # DTB accesses
+system.cpu0.dtb.hits 24615469 # DTB hits
+system.cpu0.dtb.misses 56847 # DTB misses
+system.cpu0.dtb.accesses 24672316 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 20514368 # ITB inst hits
-system.cpu0.itb.inst_misses 8789 # ITB inst misses
+system.cpu0.itb.inst_hits 20541420 # ITB inst hits
+system.cpu0.itb.inst_misses 9178 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 178 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 473 # Number of times TLB was flushed by MVA
+system.cpu0.itb.flush_tlb_mva 475 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2304 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2315 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 1449 # Number of TLB faults due to permissions restrictions
+system.cpu0.itb.perms_faults 1446 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 20523157 # ITB inst accesses
-system.cpu0.itb.hits 20514368 # DTB hits
-system.cpu0.itb.misses 8789 # DTB misses
-system.cpu0.itb.accesses 20523157 # DTB accesses
-system.cpu0.numCycles 107867607 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 20550598 # ITB inst accesses
+system.cpu0.itb.hits 20541420 # DTB hits
+system.cpu0.itb.misses 9178 # DTB misses
+system.cpu0.itb.accesses 20550598 # DTB accesses
+system.cpu0.numCycles 107861472 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 40554205 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 105662539 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 27349422 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 19645483 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 61985766 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 3245353 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.TlbCycles 132544 # Number of cycles fetch has spent waiting for tlb
-system.cpu0.fetch.MiscStallCycles 7121 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingDrainCycles 440 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu0.fetch.PendingTrapStallCycles 622961 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 144030 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 269 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 20513111 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 376873 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.ItlbSquashes 3476 # Number of outstanding ITLB misses that were squashed
-system.cpu0.fetch.rateDist::samples 105069976 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 1.208080 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.305286 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 40570754 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 105629295 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 27347795 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 19644375 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 61853082 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 3245677 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.TlbCycles 138610 # Number of cycles fetch has spent waiting for tlb
+system.cpu0.fetch.MiscStallCycles 7043 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingDrainCycles 456 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu0.fetch.PendingTrapStallCycles 740654 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 142990 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 184 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 20540168 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 376427 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.ItlbSquashes 3608 # Number of outstanding ITLB misses that were squashed
+system.cpu0.fetch.rateDist::samples 105076575 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 1.207830 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.305137 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 75961238 72.30% 72.30% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 3886755 3.70% 76.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 2398368 2.28% 78.28% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 8188948 7.79% 86.07% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 1668369 1.59% 87.66% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 1057044 1.01% 88.67% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 6240721 5.94% 94.60% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 1068642 1.02% 95.62% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4599891 4.38% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 75967097 72.30% 72.30% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 3896975 3.71% 76.01% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 2393426 2.28% 78.28% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 8192788 7.80% 86.08% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 1656267 1.58% 87.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 1057275 1.01% 88.66% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 6246218 5.94% 94.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 1068490 1.02% 95.62% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4598039 4.38% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 105069976 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::total 105076575 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.branchRate 0.253546 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.979558 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 28001193 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 58307153 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 15793340 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 1494905 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1473111 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 1905219 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 151604 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 87425197 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 489487 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1473111 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 28862922 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 7852670 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 44540857 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 16413726 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 5926414 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 83594857 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 2128 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 1233256 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LQFullEvents 243031 # Number of times rename has blocked due to LQ full
-system.cpu0.rename.SQFullEvents 3726809 # Number of times rename has blocked due to SQ full
-system.cpu0.rename.RenamedOperands 86235184 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 384969647 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 93192750 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 5702 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 72438827 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 13796341 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1547496 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 1453336 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 8912532 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 15029778 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 11466004 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1956224 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 2714292 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 80433839 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1054374 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 77107853 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 91926 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 10053145 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 24795847 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 115089 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 105069976 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.733871 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.427930 # Number of insts issued each cycle
+system.cpu0.fetch.rate 0.979305 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 27994294 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 58319975 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 15794569 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 1493949 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1473513 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 1905038 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 151409 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 87407414 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 488746 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1473513 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 28854924 # Number of cycles rename is idle
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+system.cpu0.rename.RenamedInsts 83576128 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 2157 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 1234281 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LQFullEvents 240945 # Number of times rename has blocked due to LQ full
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+system.cpu0.rename.fp_rename_lookups 5580 # Number of floating rename lookups
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+system.cpu0.rename.UndoneMaps 13773763 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1548068 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 1453832 # count of temporary serializing insts renamed
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+system.cpu0.memDep0.conflictingStores 2709003 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 80419048 # Number of instructions added to the IQ (excludes non-spec)
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
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-system.cpu0.iq.issued_per_cycle::3 6574512 6.26% 94.19% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2321319 2.21% 96.40% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1487177 1.42% 97.82% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 1563743 1.49% 99.31% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 491068 0.47% 99.77% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 239086 0.23% 100.00% # Number of insts issued each cycle
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+system.cpu0.iq.issued_per_cycle::1 10185363 9.69% 80.44% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 7872852 7.49% 87.94% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 6575632 6.26% 94.19% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2323435 2.21% 96.40% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1484934 1.41% 97.82% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 1562160 1.49% 99.30% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 492520 0.47% 99.77% # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 105069976 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 105076575 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 112390 9.87% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 3 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.87% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 534190 46.93% 56.80% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 491756 43.20% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 112989 9.93% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 4 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 9.93% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 531745 46.73% 56.66% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 493078 43.34% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 2199 0.00% 0.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 51438430 66.71% 66.71% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 57761 0.07% 66.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 51434902 66.71% 66.71% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 57707 0.07% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::SimdFloatMisc 4468 0.01% 66.79% # Type of FU issued
+system.cpu0.iq.FU_type_0::SimdFloatMisc 4464 0.01% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 66.79% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.79% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 14680887 19.04% 85.83% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 10924099 14.17% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 14679264 19.04% 85.83% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 10925524 14.17% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 77107853 # Type of FU issued
-system.cpu0.iq.rate 0.714838 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 1138339 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.014763 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 260503389 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 91586031 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 74660496 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 12558 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 6677 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 5497 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 78237256 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 6737 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 345558 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 77104069 # Type of FU issued
+system.cpu0.iq.rate 0.714843 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 1137816 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.014757 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 260501553 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 91556805 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 74656153 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 12379 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 6497 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 5408 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 78233021 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 6665 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 345101 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 2209259 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 2417 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 52309 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 1126312 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 2206473 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 2440 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 52158 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 1126677 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 207644 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 205299 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 207379 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 207346 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1473111 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 5378277 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 2195764 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 81614966 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 130944 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 15029778 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 11466004 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 550994 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 44204 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 2139047 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 52309 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 254090 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 219689 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 473779 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 76503781 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 14445333 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 547436 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1473513 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 5378839 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 2159961 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 81600157 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 131532 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 15025647 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 11465948 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 550941 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 44144 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 2103435 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 52158 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 253800 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 219690 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 473490 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 76500063 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 14443562 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 547275 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 126753 # number of nop insts executed
-system.cpu0.iew.exec_refs 25264055 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 14430009 # Number of branches executed
-system.cpu0.iew.exec_stores 10818722 # Number of stores executed
-system.cpu0.iew.exec_rate 0.709238 # Inst execution rate
-system.cpu0.iew.wb_sent 75844960 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 74665993 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 39001048 # num instructions producing a value
-system.cpu0.iew.wb_consumers 67639279 # num instructions consuming a value
+system.cpu0.iew.exec_nop 126680 # number of nop insts executed
+system.cpu0.iew.exec_refs 25263883 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 14430618 # Number of branches executed
+system.cpu0.iew.exec_stores 10820321 # Number of stores executed
+system.cpu0.iew.exec_rate 0.709244 # Inst execution rate
+system.cpu0.iew.wb_sent 75840899 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 74661561 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 38996929 # num instructions producing a value
+system.cpu0.iew.wb_consumers 67640251 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.692200 # insts written-back per cycle
-system.cpu0.iew.wb_fanout 0.576604 # average fanout of values written-back
+system.cpu0.iew.wb_rate 0.692199 # insts written-back per cycle
+system.cpu0.iew.wb_fanout 0.576534 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 11323076 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 939285 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 399913 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 102514186 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.684864 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.574695 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 11313930 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 939253 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 399962 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 102521377 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.684763 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.574745 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 75189561 73.35% 73.35% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 12242134 11.94% 85.29% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 6265138 6.11% 91.40% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2642512 2.58% 93.98% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1297372 1.27% 95.24% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 836423 0.82% 96.06% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 1889134 1.84% 97.90% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 413413 0.40% 98.30% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1738499 1.70% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 75202228 73.35% 73.35% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 12236708 11.94% 85.29% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 6265954 6.11% 91.40% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2644751 2.58% 93.98% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1294412 1.26% 95.24% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 834681 0.81% 96.06% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 1890114 1.84% 97.90% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 411979 0.40% 98.30% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1740550 1.70% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 102514186 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 57883100 # Number of instructions committed
-system.cpu0.commit.committedOps 70208236 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 102521377 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 57875239 # Number of instructions committed
+system.cpu0.commit.committedOps 70202859 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 23160211 # Number of memory references committed
-system.cpu0.commit.loads 12820519 # Number of loads committed
-system.cpu0.commit.membars 372556 # Number of memory barriers committed
-system.cpu0.commit.branches 13646736 # Number of branches committed
-system.cpu0.commit.fp_insts 5463 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 61470931 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 2656843 # Number of function calls committed.
+system.cpu0.commit.refs 23158445 # Number of memory references committed
+system.cpu0.commit.loads 12819174 # Number of loads committed
+system.cpu0.commit.membars 372518 # Number of memory barriers committed
+system.cpu0.commit.branches 13646130 # Number of branches committed
+system.cpu0.commit.fp_insts 5383 # Number of committed floating point instructions.
+system.cpu0.commit.int_insts 61467682 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 2657552 # Number of function calls committed.
system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntAlu 46987548 66.93% 66.93% # Class of committed instruction
-system.cpu0.commit.op_class_0::IntMult 56009 0.08% 67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntAlu 46983958 66.93% 66.93% # Class of committed instruction
+system.cpu0.commit.op_class_0::IntMult 55992 0.08% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::SimdFloatMisc 4468 0.01% 67.01% # Class of committed instruction
+system.cpu0.commit.op_class_0::SimdFloatMisc 4464 0.01% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.01% # Class of committed instruction
system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.01% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemRead 12820519 18.26% 85.27% # Class of committed instruction
-system.cpu0.commit.op_class_0::MemWrite 10339692 14.73% 100.00% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemRead 12819174 18.26% 85.27% # Class of committed instruction
+system.cpu0.commit.op_class_0::MemWrite 10339271 14.73% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu0.commit.op_class_0::total 70208236 # Class of committed instruction
-system.cpu0.commit.bw_lim_events 1738499 # number cycles where commit BW limit reached
+system.cpu0.commit.op_class_0::total 70202859 # Class of committed instruction
+system.cpu0.commit.bw_lim_events 1740550 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 169645518 # The number of ROB reads
-system.cpu0.rob.rob_writes 165622521 # The number of ROB writes
-system.cpu0.timesIdled 399235 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 2797631 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 2442097834 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 57811199 # Number of Instructions Simulated
-system.cpu0.committedOps 70136335 # Number of Ops (including micro ops) Simulated
-system.cpu0.cpi 1.865860 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 1.865860 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.535946 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.535946 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 83226933 # number of integer regfile reads
-system.cpu0.int_regfile_writes 47573974 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 16207 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 13000 # number of floating regfile writes
-system.cpu0.cc_regfile_reads 270444340 # number of cc regfile reads
-system.cpu0.cc_regfile_writes 28203341 # number of cc regfile writes
-system.cpu0.misc_regfile_reads 191459430 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 720407 # number of misc regfile writes
-system.cpu0.icache.tags.replacements 1944509 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.580286 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 39079293 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1945021 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 20.091965 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 9481344250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 277.092053 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 234.488233 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.541195 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.457985 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999180 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 154 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 43109447 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 43109447 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 19472177 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 19607116 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 39079293 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 19472177 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 19607116 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 39079293 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 19472177 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 19607116 # number of overall hits
-system.cpu0.icache.overall_hits::total 39079293 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 1040272 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 1044765 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 2085037 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 1040272 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 1044765 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 2085037 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 1040272 # number of overall misses
-system.cpu0.icache.overall_misses::cpu1.inst 1044765 # number of overall misses
-system.cpu0.icache.overall_misses::total 2085037 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14234369484 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 14196293397 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 28430662881 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 14234369484 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 14196293397 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 28430662881 # number of demand (read+write) miss cycles
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-system.cpu0.icache.overall_miss_latency::cpu1.inst 14196293397 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 28430662881 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 20512449 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 20651881 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 41164330 # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.demand_accesses::total 41164330 # number of demand (read+write) accesses
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-system.cpu0.icache.overall_accesses::total 41164330 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050714 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.050589 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.050652 # miss rate for ReadReq accesses
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-system.cpu0.icache.overall_miss_rate::total 0.050652 # miss rate for overall accesses
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-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13588.025438 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13635.567561 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13683.315021 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13588.025438 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13635.567561 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13683.315021 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13588.025438 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13635.567561 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 8976 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 503 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.844930 # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 69341 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::cpu1.inst 70578 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 139919 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 69341 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu1.inst 70578 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 139919 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu0.inst 69341 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::cpu1.inst 70578 # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_hits::total 139919 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 970931 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 974187 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::total 1945118 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu0.inst 970931 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::cpu1.inst 974187 # number of demand (read+write) MSHR misses
-system.cpu0.icache.demand_mshr_misses::total 1945118 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu0.inst 970931 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::cpu1.inst 974187 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_misses::total 1945118 # number of overall MSHR misses
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11624310724 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 11588912543 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_latency::total 23213223267 # number of ReadReq MSHR miss cycles
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+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2005307000 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016260 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.016264 # mshr miss rate for ReadReq accesses
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system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.015285 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227771 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.219087 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223521 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017716 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.020520 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.019212 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000136 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000204 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000172 # mshr miss rate for StoreCondReq accesses
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-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13689.935191 # average ReadReq mshr miss latency
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-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43221.693957 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15403.782774 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15501.829301 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15450.819703 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11959.576894 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15349.191641 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13890.760891 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 14568.689655 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 15599.640000 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 15221.189873 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 26391.904416 # average overall mshr miss latency
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-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 23912.260930 # average overall mshr miss latency
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system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.cpu1.branchPred.condPredicted 14236577 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 553412 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 17312116 # Number of BTB lookups
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+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11930.218209 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11967.182981 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11893.442765 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11930.218209 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups 27351704 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 14236490 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 554287 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 17308437 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 12845549 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 74.188464 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 6764103 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 29805 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 74.215534 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 6761805 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 29778 # Number of incorrect RAS predictions.
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 14379922 # DTB read hits
-system.cpu1.dtb.read_misses 49648 # DTB read misses
-system.cpu1.dtb.write_hits 10687800 # DTB write hits
-system.cpu1.dtb.write_misses 9435 # DTB write misses
+system.cpu1.dtb.read_hits 14383095 # DTB read hits
+system.cpu1.dtb.read_misses 49639 # DTB read misses
+system.cpu1.dtb.write_hits 10688826 # DTB write hits
+system.cpu1.dtb.write_misses 9570 # DTB write misses
system.cpu1.dtb.flush_tlb 178 # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva 444 # Number of times TLB was flushed by MVA
+system.cpu1.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults 765 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 1285 # Number of TLB faults due to prefetch
+system.cpu1.dtb.flush_entries 3468 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.align_faults 807 # Number of TLB faults due to alignment restrictions
+system.cpu1.dtb.prefetch_faults 1316 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 14429570 # DTB read accesses
-system.cpu1.dtb.write_accesses 10697235 # DTB write accesses
+system.cpu1.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 14432734 # DTB read accesses
+system.cpu1.dtb.write_accesses 10698396 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 25067722 # DTB hits
-system.cpu1.dtb.misses 59083 # DTB misses
-system.cpu1.dtb.accesses 25126805 # DTB accesses
+system.cpu1.dtb.hits 25071921 # DTB hits
+system.cpu1.dtb.misses 59209 # DTB misses
+system.cpu1.dtb.accesses 25131130 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 20653653 # ITB inst hits
-system.cpu1.itb.inst_misses 7569 # ITB inst misses
+system.cpu1.itb.inst_hits 20651947 # ITB inst hits
+system.cpu1.itb.inst_misses 7444 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 178 # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva 444 # Number of times TLB was flushed by MVA
+system.cpu1.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2278 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 2253 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults 1323 # Number of TLB faults due to permissions restrictions
+system.cpu1.itb.perms_faults 1346 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 20661222 # ITB inst accesses
-system.cpu1.itb.hits 20653653 # DTB hits
-system.cpu1.itb.misses 7569 # DTB misses
-system.cpu1.itb.accesses 20661222 # DTB accesses
-system.cpu1.numCycles 107242523 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 20659391 # ITB inst accesses
+system.cpu1.itb.hits 20651947 # DTB hits
+system.cpu1.itb.misses 7444 # DTB misses
+system.cpu1.itb.accesses 20659391 # DTB accesses
+system.cpu1.numCycles 107242437 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 40712684 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 106782026 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 27353552 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 19607696 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 61803081 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 3231443 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.TlbCycles 109598 # Number of cycles fetch has spent waiting for tlb
-system.cpu1.fetch.MiscStallCycles 4239 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingDrainCycles 431 # Number of cycles fetch has spent waiting on pipes to drain
-system.cpu1.fetch.PendingTrapStallCycles 249521 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 135474 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 174 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 20651884 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 381778 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.ItlbSquashes 3230 # Number of outstanding ITLB misses that were squashed
-system.cpu1.fetch.rateDist::samples 104630887 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 1.228118 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.325936 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 40725111 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 106781914 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 27351704 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 19607354 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 61789362 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 3232365 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.TlbCycles 107163 # Number of cycles fetch has spent waiting for tlb
+system.cpu1.fetch.MiscStallCycles 4234 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingDrainCycles 436 # Number of cycles fetch has spent waiting on pipes to drain
+system.cpu1.fetch.PendingTrapStallCycles 251985 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 137059 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 228 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 20650163 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 382444 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.ItlbSquashes 3144 # Number of outstanding ITLB misses that were squashed
+system.cpu1.fetch.rateDist::samples 104631724 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 1.228100 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.325979 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 75276432 71.94% 71.94% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 3916697 3.74% 75.69% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 2503204 2.39% 78.08% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 8106458 7.75% 85.83% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 1592842 1.52% 87.35% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 1179592 1.13% 88.48% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 6154126 5.88% 94.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 1149786 1.10% 95.46% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 4751750 4.54% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 75276621 71.94% 71.94% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 3919456 3.75% 75.69% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 2502030 2.39% 78.08% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 8106690 7.75% 85.83% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 1591855 1.52% 87.35% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 1179587 1.13% 88.48% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 6153020 5.88% 94.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 1148569 1.10% 95.46% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 4753896 4.54% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 104630887 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.255063 # Number of branch fetches per cycle
+system.cpu1.fetch.rateDist::total 104631724 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.255046 # Number of branch fetches per cycle
system.cpu1.fetch.rate 0.995706 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 27864157 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 57830739 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 15747454 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 1722658 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 1465635 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 1976909 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 152146 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 89229365 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 493204 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 1465635 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 28812184 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 6716141 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 45339545 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 16513270 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 5783839 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 85351560 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 2174 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 1570337 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LQFullEvents 239520 # Number of times rename has blocked due to LQ full
-system.cpu1.rename.SQFullEvents 3169707 # Number of times rename has blocked due to SQ full
-system.cpu1.rename.RenamedOperands 88205068 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 393510505 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 95333289 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 6152 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 74299663 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 13905405 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 1590806 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 1489461 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 10064978 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 15196570 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 11856807 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 2179914 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 2787279 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 82067057 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 1161463 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 78685046 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 94868 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 10122036 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 25487135 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 106552 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 104630887 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.752025 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.430826 # Number of insts issued each cycle
+system.cpu1.decode.IdleCycles 27872686 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 57819434 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 15751164 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 1722324 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 1465861 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 1979467 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 152392 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 89250616 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 494405 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 1465861 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 28821025 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 6714609 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 45327507 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 16516394 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 5786062 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 85371989 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 2599 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 1571177 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LQFullEvents 234219 # Number of times rename has blocked due to LQ full
+system.cpu1.rename.SQFullEvents 3175787 # Number of times rename has blocked due to SQ full
+system.cpu1.rename.RenamedOperands 88221695 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 393591898 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 95352384 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 6204 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 74304877 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 13916818 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 1590220 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 1488950 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 10060689 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 15200897 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 11860337 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 2181365 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 2795831 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 82084086 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 1161665 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 78697860 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 94798 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 10134538 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 25514104 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 106722 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 104631724 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.752141 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.431263 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 72948465 69.72% 69.72% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 10708543 10.23% 79.95% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 8057357 7.70% 87.66% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 6681907 6.39% 94.04% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 2500436 2.39% 96.43% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 1544614 1.48% 97.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 1464658 1.40% 99.31% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 495950 0.47% 99.78% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 228957 0.22% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 72948361 69.72% 69.72% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 10716718 10.24% 79.96% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 8047314 7.69% 87.65% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 6681191 6.39% 94.04% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 2496863 2.39% 96.42% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 1548306 1.48% 97.90% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 1467102 1.40% 99.31% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 495605 0.47% 99.78% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 230264 0.22% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 104630887 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 104631724 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 103296 8.95% 8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 5 0.00% 8.95% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 103418 8.95% 8.95% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 4 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::IntDiv 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.95% # attempts to use FU when none available
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 8.95% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 535211 46.35% 55.30% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 516097 44.70% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 534479 46.25% 55.20% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 517677 44.80% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 138 0.00% 0.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 52538123 66.77% 66.77% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 58820 0.07% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::SimdFloatMisc 4114 0.01% 66.85% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 52546114 66.77% 66.77% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 58878 0.07% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatCvt 1 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.84% # Type of FU issued
+system.cpu1.iq.FU_type_0::SimdFloatMisc 4118 0.01% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 66.85% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.85% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 14784683 18.79% 85.64% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 11299162 14.36% 100.00% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 14788040 18.79% 85.64% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 11300566 14.36% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 78685046 # Type of FU issued
-system.cpu1.iq.rate 0.733711 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 1154609 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.014674 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 263236691 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 93395575 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 76291766 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 13765 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 7276 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 6039 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 79832108 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 7409 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 367192 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 78697860 # Type of FU issued
+system.cpu1.iq.rate 0.733831 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 1155578 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.014684 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 263263981 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 93425233 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 76303202 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 13839 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 7410 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 6119 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 79845879 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 7421 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 368633 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 2204039 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 2671 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 53511 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 1150974 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 2206977 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 2711 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 53558 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 1154048 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 193750 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 155367 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 194646 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 154093 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 1465635 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 4317272 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 2160865 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 83369977 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 136369 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 15196570 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 11856807 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 585220 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 46964 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2101356 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 53511 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 256264 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 221755 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 478019 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 78073190 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 14542904 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 552934 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 1465861 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 4319089 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 2154851 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 83386940 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 137036 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 15200897 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 11860337 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 585271 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 47319 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2094987 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 53558 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 256552 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 222245 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 478797 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 78084459 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 14546039 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 554355 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 141457 # number of nop insts executed
-system.cpu1.iew.exec_refs 25733696 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 14521478 # Number of branches executed
-system.cpu1.iew.exec_stores 11190792 # Number of stores executed
-system.cpu1.iew.exec_rate 0.728006 # Inst execution rate
-system.cpu1.iew.wb_sent 77444186 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 76297805 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 39935797 # num instructions producing a value
-system.cpu1.iew.wb_consumers 69997959 # num instructions consuming a value
+system.cpu1.iew.exec_nop 141189 # number of nop insts executed
+system.cpu1.iew.exec_refs 25737628 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 14524352 # Number of branches executed
+system.cpu1.iew.exec_stores 11191589 # Number of stores executed
+system.cpu1.iew.exec_rate 0.728112 # Inst execution rate
+system.cpu1.iew.wb_sent 77455792 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 76309321 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 39942887 # num instructions producing a value
+system.cpu1.iew.wb_consumers 70003346 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.711451 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.570528 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.711559 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.570585 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 11451015 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 1054911 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 403289 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 102066180 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.704508 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.588054 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 11462178 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 1054943 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 403929 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 102065282 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.704569 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.588134 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 73979517 72.48% 72.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 12597540 12.34% 84.82% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 6450417 6.32% 91.14% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 2677104 2.62% 93.77% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 1410201 1.38% 95.15% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 931945 0.91% 96.06% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 1826334 1.79% 97.85% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 426802 0.42% 98.27% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 1766320 1.73% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 73979562 72.48% 72.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 12596710 12.34% 84.82% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 6446210 6.32% 91.14% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 2677597 2.62% 93.76% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 1413220 1.38% 95.15% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 933927 0.92% 96.06% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 1825426 1.79% 97.85% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 426013 0.42% 98.27% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 1766617 1.73% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 102066180 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 59233366 # Number of instructions committed
-system.cpu1.commit.committedOps 71906393 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 102065282 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 59241455 # Number of instructions committed
+system.cpu1.commit.committedOps 71912019 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 23698364 # Number of memory references committed
-system.cpu1.commit.loads 12992531 # Number of loads committed
-system.cpu1.commit.membars 441834 # Number of memory barriers committed
-system.cpu1.commit.branches 13745002 # Number of branches committed
-system.cpu1.commit.fp_insts 5965 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 63017798 # Number of committed integer instructions.
-system.cpu1.commit.function_calls 2684230 # Number of function calls committed.
+system.cpu1.commit.refs 23700209 # Number of memory references committed
+system.cpu1.commit.loads 12993920 # Number of loads committed
+system.cpu1.commit.membars 441872 # Number of memory barriers committed
+system.cpu1.commit.branches 13745651 # Number of branches committed
+system.cpu1.commit.fp_insts 6045 # Number of committed floating point instructions.
+system.cpu1.commit.int_insts 63021281 # Number of committed integer instructions.
+system.cpu1.commit.function_calls 2683532 # Number of function calls committed.
system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntAlu 48146836 66.96% 66.96% # Class of committed instruction
-system.cpu1.commit.op_class_0::IntMult 57080 0.08% 67.04% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntAlu 48150599 66.96% 66.96% # Class of committed instruction
+system.cpu1.commit.op_class_0::IntMult 57094 0.08% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::SimdFloatMisc 4113 0.01% 67.04% # Class of committed instruction
+system.cpu1.commit.op_class_0::SimdFloatMisc 4117 0.01% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.04% # Class of committed instruction
system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.04% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemRead 12992531 18.07% 85.11% # Class of committed instruction
-system.cpu1.commit.op_class_0::MemWrite 10705833 14.89% 100.00% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemRead 12993920 18.07% 85.11% # Class of committed instruction
+system.cpu1.commit.op_class_0::MemWrite 10706289 14.89% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu1.commit.op_class_0::total 71906393 # Class of committed instruction
-system.cpu1.commit.bw_lim_events 1766320 # number cycles where commit BW limit reached
+system.cpu1.commit.op_class_0::total 71912019 # Class of committed instruction
+system.cpu1.commit.bw_lim_events 1766617 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 171177235 # The number of ROB reads
-system.cpu1.rob.rob_writes 169283950 # The number of ROB writes
-system.cpu1.timesIdled 392418 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 2611636 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 2951410112 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 59150362 # Number of Instructions Simulated
-system.cpu1.committedOps 71823389 # Number of Ops (including micro ops) Simulated
-system.cpu1.cpi 1.813049 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.813049 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.551557 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.551557 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 84951910 # number of integer regfile reads
-system.cpu1.int_regfile_writes 48574213 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 16611 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 13102 # number of floating regfile writes
-system.cpu1.cc_regfile_reads 275725718 # number of cc regfile reads
-system.cpu1.cc_regfile_writes 28996859 # number of cc regfile writes
-system.cpu1.misc_regfile_reads 192674093 # number of misc regfile reads
-system.cpu1.misc_regfile_writes 799402 # number of misc regfile writes
+system.cpu1.rob.rob_reads 171199210 # The number of ROB reads
+system.cpu1.rob.rob_writes 169319306 # The number of ROB writes
+system.cpu1.timesIdled 392561 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 2610713 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 2951410695 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 59158214 # Number of Instructions Simulated
+system.cpu1.committedOps 71828778 # Number of Ops (including micro ops) Simulated
+system.cpu1.cpi 1.812807 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.812807 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.551631 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.551631 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 84962024 # number of integer regfile reads
+system.cpu1.int_regfile_writes 48578648 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 16598 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 13166 # number of floating regfile writes
+system.cpu1.cc_regfile_reads 275767015 # number of cc regfile reads
+system.cpu1.cc_regfile_writes 29005141 # number of cc regfile writes
+system.cpu1.misc_regfile_reads 192510337 # number of misc regfile reads
+system.cpu1.misc_regfile_writes 799392 # number of misc regfile writes
+system.iobus.trans_dist::ReadReq 30210 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30210 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72946 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178496 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321224 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321224 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480421 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326614949 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36834534 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36423 # number of replacements
-system.iocache.tags.tagsinuse 0.982061 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 0.982055 # Cycle average of tags in use
system.iocache.tags.total_refs 16 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 234012764000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 0.982061 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.061379 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.061379 # Average percentage of cache occupancy
+system.iocache.tags.occ_blocks::realview.ide 0.982055 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.061378 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.061378 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328305 # Number of tag accesses
-system.iocache.tags.data_accesses 328305 # Number of data accesses
+system.iocache.tags.tag_accesses 328241 # Number of tag accesses
+system.iocache.tags.data_accesses 328241 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide 249 # number of ReadReq misses
system.iocache.ReadReq_misses::total 249 # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide 8 # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total 8 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 249 # number of demand (read+write) misses
system.iocache.demand_misses::total 249 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 249 # number of overall misses
system.iocache.overall_misses::total 249 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 29662377 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 29662377 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 29662377 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 29662377 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 29662377 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 29662377 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 29659377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 29659377 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 29659377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 29659377 # number of demand (read+write) miss cycles
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+system.iocache.overall_miss_latency::total 29659377 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 249 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::realview.ide 36232 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 36232 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses)
system.iocache.demand_accesses::realview.ide 249 # number of demand (read+write) accesses
system.iocache.demand_accesses::total 249 # number of demand (read+write) accesses
system.iocache.overall_accesses::realview.ide 249 # number of overall (read+write) accesses
system.iocache.overall_accesses::total 249 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000221 # miss rate for WriteInvalidateReq accesses
-system.iocache.WriteInvalidateReq_miss_rate::total 0.000221 # miss rate for WriteInvalidateReq accesses
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::realview.ide 119126.012048 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 119126.012048 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::realview.ide 119126.012048 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 119126.012048 # average overall miss latency
-system.iocache.overall_avg_miss_latency::realview.ide 119126.012048 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 119126.012048 # average overall miss latency
+system.iocache.ReadReq_avg_miss_latency::realview.ide 119113.963855 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 119113.963855 # average ReadReq miss latency
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+system.iocache.demand_avg_miss_latency::total 119113.963855 # average overall miss latency
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+system.iocache.overall_avg_miss_latency::total 119113.963855 # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::realview.ide 249 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 249 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::realview.ide 16713377 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 16713377 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2228741309 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2228741309 # number of WriteInvalidateReq MSHR miss cycles
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+system.iocache.overall_mshr_miss_latency::total 16710377 # number of overall MSHR miss cycles
system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67121.995984 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 67121.995984 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67109.947791 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 67109.947791 # average ReadReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::realview.ide 67121.995984 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 67121.995984 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::realview.ide 67121.995984 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 67121.995984 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::realview.ide 67109.947791 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 67109.947791 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.l2c.tags.replacements 104249 # number of replacements
+system.l2c.tags.tagsinuse 65131.495439 # Cycle average of tags in use
+system.l2c.tags.total_refs 3107593 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 169488 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 18.335180 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 48618.767189 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker 47.674260 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000235 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst 5568.941246 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data 2875.967216 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker 44.339878 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst 4984.136716 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data 2991.668698 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.741864 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000727 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst 0.084975 # Average percentage of cache occupancy
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+system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000677 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst 0.076052 # Average percentage of cache occupancy
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+system.toL2Bus.trans_dist::ReadExResp 296861 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3891199 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2533159 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 43047 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 169738 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 6637143 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 124509952 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 99813985 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 66376 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 294776 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 224685089 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 69111 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3663534 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.009957 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.099284 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 3627058 99.00% 99.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 36476 1.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3663534 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 4671361722 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 738000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 8762587438 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 3909721674 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 26515368 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 96849116 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3039 # number of quiesce instructions executed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
sim_ticks 2904682547500 # Number of ticks simulated
final_tick 2904682547500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 680974 # Simulator instruction rate (inst/s)
-host_op_rate 821042 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17584626781 # Simulator tick rate (ticks/s)
-host_mem_usage 555668 # Number of bytes of host memory used
-host_seconds 165.18 # Real time elapsed on the host
-sim_insts 112485367 # Number of instructions simulated
-sim_ops 135622163 # Number of ops (including micro ops) simulated
+host_inst_rate 744036 # Simulator instruction rate (inst/s)
+host_op_rate 897074 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19213049576 # Simulator tick rate (ticks/s)
+host_mem_usage 562336 # Number of bytes of host memory used
+host_seconds 151.18 # Real time elapsed on the host
+sim_insts 112485415 # Number of instructions simulated
+sim_ops 135622211 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 557732 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 631552 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 4773892 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 10229960 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 557732 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 631552 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1189284 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5300352 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::total 7636212 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 17168 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 9868 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 74593 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 168816 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 82818 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::total 123423 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 22 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 192011 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 217425 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 1643516 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3521886 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 192011 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 217425 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 409437 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1824761 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6030 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 798137 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2628932 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1824761 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 22 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 192011 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 217425 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 1643519 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 798468 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6150817 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 168816 # Number of read requests accepted
system.physmem.writeReqs 123423 # Number of write requests accepted
system.physmem.bytesWrittenSys 7636212 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 146 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 3868 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 4512 # Number of requests that are neither read nor write
+system.physmem.neitherReadNorWriteReqs 4511 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 9768 # Per bank write bursts
system.physmem.perBankRdBursts::1 9653 # Per bank write bursts
system.physmem.perBankRdBursts::2 10324 # Per bank write bursts
system.physmem.bytesPerActivate::samples 58500 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 315.315419 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 184.678002 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 335.865343 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 335.865134 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 21233 36.30% 36.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 14762 25.23% 61.53% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5740 9.81% 71.34% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3179 5.43% 76.78% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2292 3.92% 80.69% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 1563 2.67% 83.37% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5741 9.81% 71.34% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3177 5.43% 76.77% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2294 3.92% 80.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 1562 2.67% 83.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1019 1.74% 85.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1097 1.88% 86.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7615 13.02% 100.00% # Bytes accessed per row activation
system.physmem.wrPerTurnAround::128-131 7 0.12% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::140-143 2 0.03% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5866 # Writes before turning the bus around for reads
-system.physmem.totQLat 1487003250 # Total ticks spent queuing
-system.physmem.totMemAccLat 4649565750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 1486855250 # Total ticks spent queuing
+system.physmem.totMemAccLat 4649417750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 843350000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8816.05 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 8815.17 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27566.05 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 27565.17 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.72 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.63 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.52 # Average system read bandwidth in MiByte/s
system.physmem.writeRowHitRate 75.88 # Row buffer hit rate for writes
system.physmem.avgGap 9939406.38 # Average gap between requests
system.physmem.pageHitRate 79.70 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2756104234500 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2756105768250 # Time in different power states
system.physmem.memoryStateTime::REF 96993520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 51578640500 # Time in different power states
+system.physmem.memoryStateTime::ACT 51577106750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.physmem.actEnergy::0 224736120 # Energy for activate commands per rank (pJ)
system.physmem.actEnergy::1 217523880 # Energy for activate commands per rank (pJ)
system.physmem.writeEnergy::1 386065440 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 189719325120 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 189719325120 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 86947691130 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 86007166335 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1666535924250 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1667360946000 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1944635950455 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1944428294400 # Total energy per rank (pJ)
-system.physmem.averagePower::0 669.484547 # Core power per rank (mW)
-system.physmem.averagePower::1 669.413056 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 70576 # Transaction distribution
-system.membus.trans_dist::ReadResp 70576 # Transaction distribution
-system.membus.trans_dist::WriteReq 27613 # Transaction distribution
-system.membus.trans_dist::WriteResp 27613 # Transaction distribution
-system.membus.trans_dist::Writeback 82818 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4510 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4512 # Transaction distribution
-system.membus.trans_dist::ReadExReq 129059 # Transaction distribution
-system.membus.trans_dist::ReadExResp 129059 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2104 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 438206 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 545870 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 618567 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4208 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 15546876 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 15710301 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 18029597 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 219 # Total snoops (count)
-system.membus.snoop_fanout::samples 283020 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 283020 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 283020 # Request fanout histogram
-system.membus.reqLayer0.occupancy 87171000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1735500 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1336695500 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1640331988 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer3.occupancy 38340241 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.physmem.actBackEnergy::0 86946648885 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 86006740545 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1666536838500 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1667361319500 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1944635822460 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1944428242110 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.484503 # Core power per rank (mW)
+system.physmem.averagePower::1 669.413038 # Core power per rank (mW)
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
+system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
+system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
+system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 631 # Number of DMA write transactions.
system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 89435 # number of replacements
-system.l2c.tags.tagsinuse 64928.071050 # Cycle average of tags in use
-system.l2c.tags.total_refs 2766017 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 154676 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 17.882651 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 50556.019026 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.943993 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000464 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 3889.866505 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 2064.899937 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.768384 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 5760.330467 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 2651.242275 # Average occupied blocks per requestor
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-system.l2c.overall_mshr_misses::cpu1.inst 9868 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::cpu1.data 75523 # number of overall MSHR misses
-system.l2c.overall_mshr_misses::total 161011 # number of overall MSHR misses
-system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 62500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 488618750 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu0.data 327007500 # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 592932000 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::cpu1.data 441364500 # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_latency::total 1850526750 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 12974797 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 14335431 # number of UpgradeReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency::total 27310228 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 20002 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency::total 20002 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3544229101 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3834753681 # number of ReadExReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency::total 7378982782 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.inst 488618750 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu0.data 3871236601 # number of demand (read+write) MSHR miss cycles
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-system.l2c.demand_mshr_miss_latency::cpu1.inst 592932000 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::cpu1.data 4276118181 # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_latency::total 9229509532 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 62500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.inst 488618750 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu0.data 3871236601 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 479000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.inst 592932000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::cpu1.data 4276118181 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_latency::total 9229509532 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 474215000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 2495734500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2890261000 # number of ReadReq MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_uncacheable_latency::total 5860210500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1979887500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2118425500 # number of WriteReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency::total 4098313000 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 474215000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu0.data 4475622000 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::cpu1.data 5008686500 # number of overall MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency::total 9958523500 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.019800 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026104 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.013445 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.991590 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991684 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.991639 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.418687 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.465941 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.442165 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.165496 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.181588 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.063392 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000161 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000296 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.009651 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.165496 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001313 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011554 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.181588 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.063392 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63831.251220 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62881.393361 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 61336.650646 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10003.698535 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10017.771488 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10011.080645 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 56855.945923 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55978.536742 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 56396.563631 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57385.659665 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 57322.229736 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59945.865538 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57385.659665 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68428.571429 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60086.339684 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 56620.078400 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 57322.229736 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 2301460 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2301445 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 27613 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 27613 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 686956 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 36226 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2751 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2753 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 295910 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 295910 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415392 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457263 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34349 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5925126 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750520 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868197 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46148 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 205689597 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 53732 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3283133 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.104795 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 3246673 98.89% 98.89% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3283133 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 4418860748 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 7658490749 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 3782893012 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks)
-system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks)
-system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36804759 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 12289558 # DTB read hits
-system.cpu0.dtb.read_misses 5978 # DTB read misses
-system.cpu0.dtb.write_hits 9834640 # DTB write hits
-system.cpu0.dtb.write_misses 1046 # DTB write misses
+system.cpu0.dtb.read_hits 12289553 # DTB read hits
+system.cpu0.dtb.read_misses 5977 # DTB read misses
+system.cpu0.dtb.write_hits 9834643 # DTB write hits
+system.cpu0.dtb.write_misses 1047 # DTB write misses
system.cpu0.dtb.flush_tlb 2938 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 467 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 4657 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 864 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 865 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 233 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 12295536 # DTB read accesses
-system.cpu0.dtb.write_accesses 9835686 # DTB write accesses
+system.cpu0.dtb.read_accesses 12295530 # DTB read accesses
+system.cpu0.dtb.write_accesses 9835690 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 22124198 # DTB hits
+system.cpu0.dtb.hits 22124196 # DTB hits
system.cpu0.dtb.misses 7024 # DTB misses
-system.cpu0.dtb.accesses 22131222 # DTB accesses
+system.cpu0.dtb.accesses 22131220 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 58032783 # ITB inst hits
+system.cpu0.itb.inst_hits 58032770 # ITB inst hits
system.cpu0.itb.inst_misses 3465 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 58036248 # ITB inst accesses
-system.cpu0.itb.hits 58032783 # DTB hits
+system.cpu0.itb.inst_accesses 58036235 # ITB inst accesses
+system.cpu0.itb.hits 58032770 # DTB hits
system.cpu0.itb.misses 3465 # DTB misses
-system.cpu0.itb.accesses 58036248 # DTB accesses
+system.cpu0.itb.accesses 58036235 # DTB accesses
system.cpu0.numCycles 2905319694 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 56513151 # Number of instructions committed
-system.cpu0.committedOps 68067864 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 60172055 # Number of integer alu accesses
+system.cpu0.committedInsts 56513131 # Number of instructions committed
+system.cpu0.committedOps 68067849 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 60172046 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 6287 # Number of float alu accesses
-system.cpu0.num_func_calls 4924591 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 7649382 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 60172055 # number of integer instructions
+system.cpu0.num_func_calls 4924583 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 7649378 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 60172046 # number of integer instructions
system.cpu0.num_fp_insts 6287 # number of float instructions
-system.cpu0.num_int_register_reads 109432777 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 41532372 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 109432768 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 41532346 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 4990 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1298 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 245794859 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 26123489 # number of times the CC registers were written
-system.cpu0.num_mem_refs 22763355 # number of memory refs
-system.cpu0.num_load_insts 12450624 # Number of load instructions
-system.cpu0.num_store_insts 10312731 # Number of store instructions
+system.cpu0.num_cc_register_reads 245794871 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 26123486 # number of times the CC registers were written
+system.cpu0.num_mem_refs 22763364 # number of memory refs
+system.cpu0.num_load_insts 12450622 # Number of load instructions
+system.cpu0.num_store_insts 10312742 # Number of store instructions
system.cpu0.num_idle_cycles 2685746001.120693 # Number of idle cycles
system.cpu0.num_busy_cycles 219573692.879307 # Number of busy cycles
system.cpu0.not_idle_fraction 0.075576 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.924424 # Percentage of idle cycles
-system.cpu0.Branches 12983474 # Number of branches fetched
+system.cpu0.Branches 12983457 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2204 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 46789639 67.21% 67.21% # Class of executed instruction
-system.cpu0.op_class::IntMult 58624 0.08% 67.30% # Class of executed instruction
+system.cpu0.op_class::IntAlu 46789630 67.21% 67.21% # Class of executed instruction
+system.cpu0.op_class::IntMult 58620 0.08% 67.30% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.30% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.30% # Class of executed instruction
-system.cpu0.op_class::MemRead 12450624 17.88% 85.19% # Class of executed instruction
-system.cpu0.op_class::MemWrite 10312731 14.81% 100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead 12450622 17.88% 85.19% # Class of executed instruction
+system.cpu0.op_class::MemWrite 10312742 14.81% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 69618095 # Class of executed instruction
+system.cpu0.op_class::total 69618091 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3031 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 1698167 # number of replacements
-system.cpu0.icache.tags.tagsinuse 510.774848 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 113885210 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1698679 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 67.043397 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 25359588250 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 419.089770 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 91.685078 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.818535 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.179072 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.997607 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 46 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 197 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 262 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 7 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 117282580 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 117282580 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 57188150 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 56697060 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 113885210 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 57188150 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::cpu1.inst 56697060 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 113885210 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 57188150 # number of overall hits
-system.cpu0.icache.overall_hits::cpu1.inst 56697060 # number of overall hits
-system.cpu0.icache.overall_hits::total 113885210 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 844633 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::cpu1.inst 854052 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 1698685 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 844633 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::cpu1.inst 854052 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 1698685 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 844633 # number of overall misses
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-system.cpu0.icache.overall_misses::total 1698685 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 11522277749 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 11755816000 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 23278093749 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 11522277749 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::cpu1.inst 11755816000 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 23278093749 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 11522277749 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::cpu1.inst 11755816000 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 23278093749 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 58032783 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::cpu1.inst 57551112 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 115583895 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 58032783 # number of demand (read+write) accesses
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-system.cpu0.icache.demand_accesses::total 115583895 # number of demand (read+write) accesses
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-system.cpu0.icache.overall_accesses::total 115583895 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014554 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.014840 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.014697 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014554 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::cpu1.inst 0.014840 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.014697 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014554 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::cpu1.inst 0.014840 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.014697 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13641.756537 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13764.754371 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 13703.596458 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.756537 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13764.754371 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 13703.596458 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.756537 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13764.754371 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 13703.596458 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes 0 # number of fast writes performed
-system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 844633 # number of ReadReq MSHR misses
-system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854052 # number of ReadReq MSHR misses
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system.cpu0.dcache.blocked_cycles::no_mshrs 38 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.writebacks::total 686956 # number of writebacks
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system.cpu0.dcache.ReadReq_mshr_hits::total 615 # number of ReadReq MSHR hits
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system.cpu0.dcache.overall_mshr_hits::total 615 # number of overall MSHR hits
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system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2264487500 # number of WriteReq MSHR uncacheable cycles
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system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.019582 # mshr miss rate for LoadLockedReq accesses
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system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12307.632572 # average SoftPFReq mshr miss latency
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+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13641.719410 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13764.732400 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 13703.567023 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13641.719410 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13764.732400 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 13703.567023 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 844632 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 854053 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 1698685 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 844632 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu1.inst 854053 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 1698685 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 844632 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu1.inst 854053 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 1698685 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 9830027251 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 10044094000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 19874121251 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 9830027251 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 10044094000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 19874121251 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 9830027251 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 10044094000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 19874121251 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 597905000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 597905000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 597905000 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total 597905000 # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014697 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_miss_rate::total 0.014697 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014554 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.014840 # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_miss_rate::total 0.014697 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11699.709629 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11638.236831 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.504325 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::total 11699.709629 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 12236378 # DTB read hits
+system.cpu1.dtb.read_hits 12236392 # DTB read hits
system.cpu1.dtb.read_misses 5657 # DTB read misses
-system.cpu1.dtb.write_hits 9775690 # DTB write hits
+system.cpu1.dtb.write_hits 9775692 # DTB write hits
system.cpu1.dtb.write_misses 790 # DTB write misses
system.cpu1.dtb.flush_tlb 2934 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 450 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 4044 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 917 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 918 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 12242035 # DTB read accesses
-system.cpu1.dtb.write_accesses 9776480 # DTB write accesses
+system.cpu1.dtb.read_accesses 12242049 # DTB read accesses
+system.cpu1.dtb.write_accesses 9776482 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 22012068 # DTB hits
+system.cpu1.dtb.hits 22012084 # DTB hits
system.cpu1.dtb.misses 6447 # DTB misses
-system.cpu1.dtb.accesses 22018515 # DTB accesses
+system.cpu1.dtb.accesses 22018531 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 57551112 # ITB inst hits
+system.cpu1.itb.inst_hits 57551182 # ITB inst hits
system.cpu1.itb.inst_misses 3277 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 57554389 # ITB inst accesses
-system.cpu1.itb.hits 57551112 # DTB hits
+system.cpu1.itb.inst_accesses 57554459 # ITB inst accesses
+system.cpu1.itb.hits 57551182 # DTB hits
system.cpu1.itb.misses 3277 # DTB misses
-system.cpu1.itb.accesses 57554389 # DTB accesses
+system.cpu1.itb.accesses 57554459 # DTB accesses
system.cpu1.numCycles 2904045401 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 55972216 # Number of instructions committed
-system.cpu1.committedOps 67554299 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 59752061 # Number of integer alu accesses
+system.cpu1.committedInsts 55972284 # Number of instructions committed
+system.cpu1.committedOps 67554362 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 59752131 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5003 # Number of float alu accesses
-system.cpu1.num_func_calls 4972349 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 7584517 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 59752061 # number of integer instructions
+system.cpu1.num_func_calls 4972365 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 7584533 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 59752131 # number of integer instructions
system.cpu1.num_fp_insts 5003 # number of float instructions
-system.cpu1.num_int_register_reads 108688873 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 41135339 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 108688988 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 41135378 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 3588 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1418 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 244070995 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 25783519 # number of times the CC registers were written
-system.cpu1.num_mem_refs 22653694 # number of memory refs
-system.cpu1.num_load_insts 12397895 # Number of load instructions
-system.cpu1.num_store_insts 10255799 # Number of store instructions
+system.cpu1.num_cc_register_reads 244071190 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 25783552 # number of times the CC registers were written
+system.cpu1.num_mem_refs 22653716 # number of memory refs
+system.cpu1.num_load_insts 12397911 # Number of load instructions
+system.cpu1.num_store_insts 10255805 # Number of store instructions
system.cpu1.num_idle_cycles 2693922745.089012 # Number of idle cycles
system.cpu1.num_busy_cycles 210122655.910988 # Number of busy cycles
system.cpu1.not_idle_fraction 0.072355 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.927645 # Percentage of idle cycles
-system.cpu1.Branches 12941354 # Number of branches fetched
+system.cpu1.Branches 12941389 # Number of branches fetched
system.cpu1.op_class::No_OpClass 133 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 46411426 67.14% 67.14% # Class of executed instruction
-system.cpu1.op_class::IntMult 56056 0.08% 67.22% # Class of executed instruction
+system.cpu1.op_class::IntAlu 46411475 67.14% 67.14% # Class of executed instruction
+system.cpu1.op_class::IntMult 56055 0.08% 67.22% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 67.22% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.23% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.23% # Class of executed instruction
-system.cpu1.op_class::MemRead 12397895 17.94% 85.16% # Class of executed instruction
-system.cpu1.op_class::MemWrite 10255799 14.84% 100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead 12397911 17.94% 85.16% # Class of executed instruction
+system.cpu1.op_class::MemWrite 10255805 14.84% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 69125473 # Class of executed instruction
+system.cpu1.op_class::total 69125543 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
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+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3415392 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2457281 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 18122 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 34351 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5925146 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108750520 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96868901 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 24732 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 46156 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 205690309 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 53730 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3283144 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.011105 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.104794 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 3246684 98.89% 98.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 36460 1.11% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3283144 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 4418882248 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 985500 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 7658490749 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 3782924511 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 11939000 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 22834207 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 5125902116500 # Number of ticks simulated
final_tick 5125902116500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 134346 # Simulator instruction rate (inst/s)
-host_op_rate 265563 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1687822207 # Simulator tick rate (ticks/s)
-host_mem_usage 793660 # Number of bytes of host memory used
-host_seconds 3036.99 # Real time elapsed on the host
+host_inst_rate 182847 # Simulator instruction rate (inst/s)
+host_op_rate 361437 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2297162464 # Simulator tick rate (ticks/s)
+host_mem_usage 805240 # Number of bytes of host memory used
+host_seconds 2231.41 # Real time elapsed on the host
sim_insts 408006726 # Number of instructions simulated
sim_ops 806511598 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 4800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1043840 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10813760 # Number of bytes read from this memory
+system.physmem.bytes_read::pc.south_bridge.ide 28352 # Number of bytes read from this memory
system.physmem.bytes_read::total 11891200 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1043840 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1043840 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6604544 # Number of bytes written to this memory
system.physmem.bytes_written::pc.south_bridge.ide 2990080 # Number of bytes written to this memory
system.physmem.bytes_written::total 9594624 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 75 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 16310 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168965 # Number of read requests responded to by this memory
+system.physmem.num_reads::pc.south_bridge.ide 443 # Number of read requests responded to by this memory
system.physmem.num_reads::total 185800 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 103196 # Number of write requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46720 # Number of write requests responded to by this memory
system.physmem.num_writes::total 149916 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 936 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 87 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 203640 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 2109631 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::pc.south_bridge.ide 5531 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 2319826 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 203640 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 203640 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::pc.south_bridge.ide 583328 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 1871792 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1288465 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 936 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 87 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 203640 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 2109631 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 588859 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 4191618 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 185800 # Number of read requests accepted
system.physmem.writeReqs 149916 # Number of write requests accepted
system.physmem.totalEnergy::1 3427906972860 # Total energy per rank (pJ)
system.physmem.averagePower::0 668.726542 # Core power per rank (mW)
system.physmem.averagePower::1 668.742609 # Core power per rank (mW)
-system.membus.trans_dist::ReadReq 662592 # Transaction distribution
-system.membus.trans_dist::ReadResp 662582 # Transaction distribution
-system.membus.trans_dist::WriteReq 13889 # Transaction distribution
-system.membus.trans_dist::WriteResp 13889 # Transaction distribution
-system.membus.trans_dist::Writeback 103196 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution
-system.membus.trans_dist::ReadExReq 133104 # Transaction distribution
-system.membus.trans_dist::ReadExResp 133101 # Transaction distribution
-system.membus.trans_dist::MessageReq 1644 # Transaction distribution
-system.membus.trans_dist::MessageResp 1644 # Transaction distribution
-system.membus.trans_dist::BadAddressError 10 # Transaction distribution
-system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 949 # Total snoops (count)
-system.membus.snoop_fanout::samples 338415 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 338415 # Request fanout histogram
-system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks)
-system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
-system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
-system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks)
-system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 47575 # number of replacements
-system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use
-system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy
-system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
-system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
-system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 428670 # Number of tag accesses
-system.iocache.tags.data_accesses 428670 # Number of data accesses
-system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
-system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
-system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses
-system.iocache.demand_misses::total 910 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses
-system.iocache.overall_misses::total 910 # number of overall misses
-system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
-system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
-system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
-system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
-system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
-system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency
-system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency
-system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.iocache.fast_writes 46720 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
-system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
-system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses
-system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses
-system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses
-system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
-system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
-system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
-system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
-system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 225681 # Transaction distribution
-system.iobus.trans_dist::ReadResp 225681 # Transaction distribution
-system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
-system.iobus.trans_dist::WriteResp 57721 # Transaction distribution
-system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
-system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
-system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
-system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
-system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
-system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks)
-system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
-system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 86911006 # Number of BP lookups
system.cpu.branchPred.condPredicted 86911006 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 901724 # Number of conditional branches incorrect
system.cpu.branchPred.BTBHitPct 97.654891 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1556278 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 178526 # Number of incorrect RAS predictions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.apic_clk_domain.clock 8000 # Clock period in ticks
system.cpu.numCycles 449563158 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.iew.iewLSQFullEvents 8107674 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 14518 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 515540 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 536897 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1052437 # Number of branch mispredicts detected at execute
+system.cpu.iew.predictedNotTakenIncorrect 536896 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 1052436 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 822725796 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 18017825 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 1477348 # Number of squashed instructions skipped in execute
system.cpu.cc_regfile_writes 322125902 # number of cc regfile writes
system.cpu.misc_regfile_reads 265627452 # number of misc regfile reads
system.cpu.misc_regfile_writes 402647 # number of misc regfile writes
-system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 58568 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks)
-system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu.icache.tags.replacements 994393 # number of replacements
-system.cpu.icache.tags.tagsinuse 510.035216 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 8125717 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 994905 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 8.167330 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 147627648000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 510.035216 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.996163 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total 0.996163 # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 141 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 10178850 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 10178850 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 8125717 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 8125717 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 8125717 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 8125717 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 8125717 # number of overall hits
-system.cpu.icache.overall_hits::total 8125717 # number of overall hits
-system.cpu.icache.ReadReq_misses::cpu.inst 1058185 # number of ReadReq misses
-system.cpu.icache.ReadReq_misses::total 1058185 # number of ReadReq misses
-system.cpu.icache.demand_misses::cpu.inst 1058185 # number of demand (read+write) misses
-system.cpu.icache.demand_misses::total 1058185 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1058185 # number of overall misses
-system.cpu.icache.overall_misses::total 1058185 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 14693875503 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 14693875503 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::cpu.inst 14693875503 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::total 14693875503 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::cpu.inst 14693875503 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::total 14693875503 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 9183902 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 9183902 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 9183902 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 9183902 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 9183902 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 9183902 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.115222 # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_miss_rate::total 0.115222 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::cpu.inst 0.115222 # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total 0.115222 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::cpu.inst 0.115222 # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total 0.115222 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13885.923069 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13885.923069 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13885.923069 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13885.923069 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13885.923069 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 7023 # number of cycles access was blocked
-system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked
-system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.avg_blocked_cycles::no_mshrs 23.646465 # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.icache.fast_writes 0 # number of fast writes performed
-system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63237 # number of ReadReq MSHR hits
-system.cpu.icache.ReadReq_mshr_hits::total 63237 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::cpu.inst 63237 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::total 63237 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::cpu.inst 63237 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::total 63237 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 994948 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 994948 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 994948 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 994948 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 994948 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 994948 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12059629101 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12059629101 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12059629101 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12059629101 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12059629101 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12059629101 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.108336 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.108336 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.108336 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.108336 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12120.863704 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12120.863704 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12120.863704 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 12120.863704 # average overall mshr miss latency
-system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.itb_walker_cache.tags.replacements 14092 # number of replacements
-system.cpu.itb_walker_cache.tags.tagsinuse 6.014059 # Cycle average of tags in use
-system.cpu.itb_walker_cache.tags.total_refs 26262 # Total number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.sampled_refs 14107 # Sample count of references to valid blocks.
-system.cpu.itb_walker_cache.tags.avg_refs 1.861629 # Average number of references to valid blocks.
-system.cpu.itb_walker_cache.tags.warmup_cycle 5101924515000 # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 6.014059 # Average occupied blocks per requestor
-system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.375879 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_percent::total 0.375879 # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
-system.cpu.itb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
-system.cpu.itb_walker_cache.tags.tag_accesses 97491 # Number of tag accesses
-system.cpu.itb_walker_cache.tags.data_accesses 97491 # Number of data accesses
-system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 26263 # number of ReadReq hits
-system.cpu.itb_walker_cache.ReadReq_hits::total 26263 # number of ReadReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 26265 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::total 26265 # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 26265 # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::total 26265 # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 14987 # number of ReadReq misses
-system.cpu.itb_walker_cache.ReadReq_misses::total 14987 # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 14987 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::total 14987 # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 14987 # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::total 14987 # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 174073497 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.ReadReq_miss_latency::total 174073497 # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 174073497 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency::total 174073497 # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 174073497 # number of overall miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency::total 174073497 # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 41250 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.ReadReq_accesses::total 41250 # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 41252 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::total 41252 # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 41252 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::total 41252 # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.363321 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.363321 # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.363304 # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total 0.363304 # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.363304 # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total 0.363304 # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11614.966104 # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 11614.966104 # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total 11614.966104 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11614.966104 # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total 11614.966104 # average overall miss latency
-system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
-system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks::writebacks 3303 # number of writebacks
-system.cpu.itb_walker_cache.writebacks::total 3303 # number of writebacks
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 14987 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 14987 # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 14987 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses::total 14987 # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 14987 # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses::total 14987 # number of overall MSHR misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 144083525 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 144083525 # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 144083525 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 144083525 # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 144083525 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 144083525 # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.363321 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.363321 # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.363304 # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.363304 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.363304 # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 9613.900380 # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 9613.900380 # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 9613.900380 # average overall mshr miss latency
-system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dtb_walker_cache.tags.replacements 74377 # number of replacements
-system.cpu.dtb_walker_cache.tags.tagsinuse 15.812457 # Cycle average of tags in use
-system.cpu.dtb_walker_cache.tags.total_refs 116780 # Total number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.sampled_refs 74392 # Sample count of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.avg_refs 1.569792 # Average number of references to valid blocks.
-system.cpu.dtb_walker_cache.tags.warmup_cycle 194043074000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 15.812457 # Average occupied blocks per requestor
-system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.988279 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_percent::total 0.988279 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.tags.occ_task_id_blocks::1024 15 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::0 9 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
-system.cpu.dtb_walker_cache.tags.occ_task_id_percent::1024 0.937500 # Percentage of cache occupancy per task id
-system.cpu.dtb_walker_cache.tags.tag_accesses 459926 # Number of tag accesses
-system.cpu.dtb_walker_cache.tags.data_accesses 459926 # Number of data accesses
-system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 116782 # number of ReadReq hits
-system.cpu.dtb_walker_cache.ReadReq_hits::total 116782 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 116782 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::total 116782 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 116782 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::total 116782 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 75454 # number of ReadReq misses
-system.cpu.dtb_walker_cache.ReadReq_misses::total 75454 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 75454 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::total 75454 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 75454 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::total 75454 # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 927232955 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 927232955 # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 927232955 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency::total 927232955 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 927232955 # number of overall miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency::total 927232955 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 192236 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.ReadReq_accesses::total 192236 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 192236 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::total 192236 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 192236 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::total 192236 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.392507 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.392507 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.392507 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total 0.392507 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.392507 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total 0.392507 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 12288.718358 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 12288.718358 # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 12288.718358 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12288.718358 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 12288.718358 # average overall miss latency
-system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
-system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks::writebacks 21876 # number of writebacks
-system.cpu.dtb_walker_cache.writebacks::total 21876 # number of writebacks
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 75454 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 75454 # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 75454 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses::total 75454 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 75454 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses::total 75454 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 776178235 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 776178235 # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 776178235 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 776178235 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 776178235 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 776178235 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.392507 # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.392507 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.392507 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.392507 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 10286.773862 # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 10286.773862 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 10286.773862 # average overall mshr miss latency
-system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 1657683 # number of replacements
system.cpu.dcache.tags.tagsinuse 511.996297 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 19131015 # Total number of references to valid blocks.
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements 113085 # number of replacements
-system.cpu.l2cache.tags.tagsinuse 64818.383323 # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs 3831425 # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs 176970 # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs 21.650138 # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.tags.occ_blocks::writebacks 50432.340696 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 22.760500 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.143343 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 3264.453296 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data 11098.685488 # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_percent::writebacks 0.769536 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000347 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst 0.049812 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.data 0.169353 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total 0.989050 # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_task_id_blocks::1024 63885 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::1 634 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::2 3305 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5793 # Occupied blocks per task id
-system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54091 # Occupied blocks per task id
-system.cpu.l2cache.tags.occ_task_id_percent::1024 0.974808 # Percentage of cache occupancy per task id
-system.cpu.l2cache.tags.tag_accesses 35031209 # Number of tag accesses
-system.cpu.l2cache.tags.data_accesses 35031209 # Number of data accesses
-system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 68532 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12501 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst 978548 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.data 1334624 # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::total 2394205 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits::writebacks 1584468 # number of Writeback hits
-system.cpu.l2cache.Writeback_hits::total 1584468 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.data 309 # number of UpgradeReq hits
-system.cpu.l2cache.UpgradeReq_hits::total 309 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.data 153669 # number of ReadExReq hits
-system.cpu.l2cache.ReadExReq_hits::total 153669 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits::cpu.dtb.walker 68532 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.itb.walker 12501 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst 978548 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.data 1488293 # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::total 2547874 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits::cpu.dtb.walker 68532 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.itb.walker 12501 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst 978548 # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.data 1488293 # number of overall hits
-system.cpu.l2cache.overall_hits::total 2547874 # number of overall hits
-system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 75 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst 16312 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.data 35875 # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::total 52269 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.data 1444 # number of UpgradeReq misses
-system.cpu.l2cache.UpgradeReq_misses::total 1444 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.data 133393 # number of ReadExReq misses
-system.cpu.l2cache.ReadExReq_misses::total 133393 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses::cpu.dtb.walker 75 # number of demand (read+write) misses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 80071.428571 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76865.313879 # average ReadReq miss latency
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+system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11184.770083 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69822.272960 # average ReadExReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69822.272960 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 86780 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 80071.428571 # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72064.512808 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::total 72492.550732 # average overall miss latency
+system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.l2cache.fast_writes 0 # number of fast writes performed
+system.cpu.l2cache.cache_copies 0 # number of cache copies performed
+system.cpu.l2cache.writebacks::writebacks 103196 # number of writebacks
+system.cpu.l2cache.writebacks::total 103196 # number of writebacks
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+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1444 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 1444 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133393 # number of ReadExReq MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 75 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1049198000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2439336749 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 3494586749 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu.toL2Bus.trans_dist::ReadReq 3066870 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 3066328 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteReq 13889 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteResp 13889 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 1584468 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 46724 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeReq 2232 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::UpgradeResp 2232 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExReq 287069 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadExResp 287069 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::BadAddressError 10 # Transaction distribution
+system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1989808 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6126047 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 30798 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 165937 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 8312590 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 63671040 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 207694139 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 1011904 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 5790912 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 278167995 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.snoops 58568 # Total snoops (count)
+system.cpu.toL2Bus.snoop_fanout::samples 4377947 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::mean 3.010880 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::stdev 0.103740 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::3 4330313 98.91% 98.91% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::4 47634 1.09% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::total 4377947 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 4068281890 # Layer occupancy (ticks)
+system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.snoopLayer0.occupancy 567000 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer0.occupancy 1496480643 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer1.occupancy 3139987945 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer2.occupancy 22488486 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.cpu.toL2Bus.respLayer3.occupancy 113254360 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 225681 # Transaction distribution
+system.iobus.trans_dist::ReadResp 225681 # Transaction distribution
+system.iobus.trans_dist::WriteReq 57721 # Transaction distribution
+system.iobus.trans_dist::WriteResp 57721 # Transaction distribution
+system.iobus.trans_dist::MessageReq 1644 # Transaction distribution
+system.iobus.trans_dist::MessageResp 1644 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 78 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 427356 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27696 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 471544 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95260 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95260 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3288 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3288 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 570092 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6738 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 39 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 213678 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.com_1.pio 13848 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 242058 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027824 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.ide.dma::total 3027824 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6576 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.pc.south_bridge.io_apic.int_master::total 6576 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 3276458 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 3917656 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 8889000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
+system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
+system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 70000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
+system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer9.occupancy 213679000 # Layer occupancy (ticks)
+system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
+system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 20719000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 422009356 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 460543000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer1.occupancy 52362257 # Layer occupancy (ticks)
+system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer2.occupancy 1644000 # Layer occupancy (ticks)
+system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.replacements 47575 # number of replacements
+system.iocache.tags.tagsinuse 0.091458 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 47591 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 4992976867000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.091458 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::pc.south_bridge.ide 0.005716 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.005716 # Average percentage of cache occupancy
+system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
+system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
+system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
+system.iocache.tags.tag_accesses 428670 # Number of tag accesses
+system.iocache.tags.data_accesses 428670 # Number of data accesses
+system.iocache.WriteInvalidateReq_hits::pc.south_bridge.ide 46720 # number of WriteInvalidateReq hits
+system.iocache.WriteInvalidateReq_hits::total 46720 # number of WriteInvalidateReq hits
+system.iocache.ReadReq_misses::pc.south_bridge.ide 910 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 910 # number of ReadReq misses
+system.iocache.demand_misses::pc.south_bridge.ide 910 # number of demand (read+write) misses
+system.iocache.demand_misses::total 910 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 910 # number of overall misses
+system.iocache.overall_misses::total 910 # number of overall misses
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 152161446 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 152161446 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide 152161446 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 152161446 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide 152161446 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 152161446 # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 910 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 910 # number of ReadReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::pc.south_bridge.ide 46720 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.WriteInvalidateReq_accesses::total 46720 # number of WriteInvalidateReq accesses(hits+misses)
+system.iocache.demand_accesses::pc.south_bridge.ide 910 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 910 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 910 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 910 # number of overall (read+write) accesses
+system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
+system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
+system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
+system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
+system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
+system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average ReadReq miss latency
+system.iocache.ReadReq_avg_miss_latency::total 167210.380220 # average ReadReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
+system.iocache.demand_avg_miss_latency::total 167210.380220 # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 167210.380220 # average overall miss latency
+system.iocache.overall_avg_miss_latency::total 167210.380220 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked
+system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 26 # number of cycles access was blocked
+system.iocache.blocked::no_targets 0 # number of cycles access was blocked
+system.iocache.avg_blocked_cycles::no_mshrs 11.846154 # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.iocache.fast_writes 46720 # number of fast writes performed
+system.iocache.cache_copies 0 # number of cache copies performed
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 910 # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total 910 # number of ReadReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide 910 # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total 910 # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide 910 # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total 910 # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total 104814946 # number of ReadReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::pc.south_bridge.ide 2846577667 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2846577667 # number of WriteInvalidateReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total 104814946 # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 104814946 # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total 104814946 # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
+system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
+system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 115181.259341 # average ReadReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::pc.south_bridge.ide inf # average WriteInvalidateReq mshr miss latency
+system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 115181.259341 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 115181.259341 # average overall mshr miss latency
+system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 662592 # Transaction distribution
+system.membus.trans_dist::ReadResp 662582 # Transaction distribution
+system.membus.trans_dist::WriteReq 13889 # Transaction distribution
+system.membus.trans_dist::WriteResp 13889 # Transaction distribution
+system.membus.trans_dist::Writeback 103196 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 46720 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 46720 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 2215 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 1736 # Transaction distribution
+system.membus.trans_dist::ReadExReq 133104 # Transaction distribution
+system.membus.trans_dist::ReadExResp 133101 # Transaction distribution
+system.membus.trans_dist::MessageReq 1644 # Transaction distribution
+system.membus.trans_dist::MessageResp 1644 # Transaction distribution
+system.membus.trans_dist::BadAddressError 10 # Transaction distribution
+system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3288 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.apicbridge.master::total 3288 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 471544 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 775066 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 477864 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.membus.badaddr_responder.pio 20 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1724494 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 94793 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 94793 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 1822575 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6576 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.apicbridge.master::total 6576 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 242058 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1550129 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18467392 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 20259579 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 3018432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 3018432 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 23284587 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 949 # Total snoops (count)
+system.membus.snoop_fanout::samples 338415 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 338415 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 338415 # Request fanout histogram
+system.membus.reqLayer0.occupancy 251687000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 583226500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 3288000 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer3.occupancy 1575195000 # Layer occupancy (ticks)
+system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer4.occupancy 13500 # Layer occupancy (ticks)
+system.membus.reqLayer4.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer0.occupancy 1644000 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 3157657266 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer4.occupancy 54931743 # Layer occupancy (ticks)
+system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
+system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
+system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
+system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- Begin Simulation Statistics ----------
sim_seconds 2.802883 # Number of seconds simulated
-sim_ticks 2802882713500 # Number of ticks simulated
-final_tick 2802882713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2802882634000 # Number of ticks simulated
+final_tick 2802882634000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1349319 # Simulator instruction rate (inst/s)
-host_op_rate 1644123 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 25757810314 # Simulator tick rate (ticks/s)
-host_mem_usage 564420 # Number of bytes of host memory used
-host_seconds 108.82 # Real time elapsed on the host
-sim_insts 146828498 # Number of instructions simulated
-sim_ops 178908222 # Number of ops (including micro ops) simulated
+host_inst_rate 1078207 # Simulator instruction rate (inst/s)
+host_op_rate 1313778 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20582448891 # Simulator tick rate (ticks/s)
+host_mem_usage 574132 # Number of bytes of host memory used
+host_seconds 136.18 # Real time elapsed on the host
+sim_insts 146828350 # Number of instructions simulated
+sim_ops 178908035 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 1116900 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 9456508 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 1117092 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 9456444 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 151892 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 1081824 # Number of bytes read from this memory
-system.physmem.bytes_read::total 11808788 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 1116900 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 151892 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1268792 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6072384 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 151956 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 1081888 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 11809044 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 1117092 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 151956 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1269048 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6071744 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8408464 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8407824 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 25905 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 148283 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 25908 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 148282 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 2528 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 16927 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 193669 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 94881 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 2529 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 16928 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 193673 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 94871 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 135541 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 135531 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 160 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 398483 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 3373851 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 398551 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 3373828 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 54191 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 385968 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4213087 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 398483 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 54191 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 452674 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2166478 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 54214 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 385991 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 343 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4213178 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 398551 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 54214 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 452765 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2166250 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6316 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2999934 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2166478 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 827126 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2999706 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2166250 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 160 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 398483 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 3380167 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 398551 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 3380144 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 54191 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 385983 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7213021 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 54214 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 386005 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 827468 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7212884 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 75957 # Transaction distribution
-system.membus.trans_dist::ReadResp 75957 # Transaction distribution
-system.membus.trans_dist::WriteReq 30905 # Transaction distribution
-system.membus.trans_dist::WriteResp 30905 # Transaction distribution
-system.membus.trans_dist::Writeback 94881 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 60384 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 40930 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 15620 # Transaction distribution
-system.membus.trans_dist::ReadExReq 196326 # Transaction distribution
-system.membus.trans_dist::ReadExResp 152193 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652128 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 773554 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 846506 # Packet count per connected master and slave (bytes)
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-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897956 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18087780 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 20422244 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 460689 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 460689 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 460689 # Request fanout histogram
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 107632 # number of replacements
-system.l2c.tags.tagsinuse 62143.934871 # Cycle average of tags in use
-system.l2c.tags.total_refs 207938 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 168025 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 1.237542 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 48688.027343 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.972782 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030392 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 7324.741121 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3758.950125 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.829103 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 1656.363289 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 711.020717 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.742920 # Average percentage of cache occupancy
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-system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 73 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 1906 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 12994 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 45387 # Occupied blocks per task id
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-system.l2c.tags.tag_accesses 4903910 # Number of tag accesses
-system.l2c.tags.data_accesses 4903910 # Number of data accesses
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-system.l2c.ReadReq_hits::cpu0.itb.walker 59 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 28044 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 76113 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 38 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 35 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 11456 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 11379 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 127193 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 225882 # number of Writeback hits
-system.l2c.Writeback_hits::total 225882 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 506 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 65 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 571 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 65 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 6 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 71 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 13825 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 3137 # number of ReadExReq hits
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-system.l2c.demand_hits::cpu0.itb.walker 59 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 28044 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 89938 # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.inst 11456 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 14516 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu0.inst 28044 # number of overall hits
-system.l2c.overall_hits::cpu0.data 89938 # number of overall hits
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-system.l2c.overall_hits::cpu1.itb.walker 35 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 11456 # number of overall hits
-system.l2c.overall_hits::cpu1.data 14516 # number of overall hits
-system.l2c.overall_hits::total 144155 # number of overall hits
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-system.l2c.ReadReq_misses::cpu0.inst 16888 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 11308 # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu1.inst 2363 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 1122 # number of ReadReq misses
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-system.l2c.UpgradeReq_misses::cpu1.data 3290 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 13272 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 756 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 1185 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1941 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 136781 # number of ReadExReq misses
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-system.l2c.ReadReq_accesses::cpu1.inst 13819 # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::total 158885 # number of ReadReq accesses(hits+misses)
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-system.l2c.Writeback_accesses::total 225882 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 10488 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 3355 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 13843 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu0.data 821 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 1191 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 2012 # number of SCUpgradeReq accesses(hits+misses)
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-system.l2c.demand_accesses::cpu0.itb.walker 61 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 44932 # number of demand (read+write) accesses
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-system.l2c.demand_accesses::cpu1.inst 13819 # number of demand (read+write) accesses
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-system.l2c.overall_accesses::cpu0.inst 44932 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 238027 # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu1.inst 13819 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 31457 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 328447 # number of overall (read+write) accesses
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-system.l2c.ReadReq_miss_rate::cpu0.inst 0.375857 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.129351 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.170996 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.089753 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.199465 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.951754 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.980626 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.958752 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.920828 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.994962 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 0.964712 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.908204 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.834512 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.899966 # miss rate for ReadExReq accesses
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-system.l2c.demand_miss_rate::cpu1.inst 0.170996 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.538545 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.561101 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.092105 # miss rate for overall accesses
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-system.l2c.overall_miss_rate::cpu0.inst 0.375857 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.622152 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.050000 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.170996 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.538545 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.561101 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 94881 # number of writebacks
-system.l2c.writebacks::total 94881 # number of writebacks
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 305223 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 305223 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 225882 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 60548 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 41001 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 101549 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 213695 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 213695 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117774 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410852 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1528626 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34664498 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432626 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 45097124 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 36713 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 838812 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.203947 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 802336 95.65% 95.65% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 838812 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 31002 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31002 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59433 # Transaction distribution
-system.iobus.trans_dist::WriteResp 23209 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56624 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107918 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71568 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162808 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2484056 # Cumulative packet size per connected master and slave (bytes)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 20339791 # DTB read hits
+system.cpu0.dtb.read_hits 20339775 # DTB read hits
system.cpu0.dtb.read_misses 6871 # DTB read misses
-system.cpu0.dtb.write_hits 16391007 # DTB write hits
+system.cpu0.dtb.write_hits 16390998 # DTB write hits
system.cpu0.dtb.write_misses 1093 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.prefetch_faults 1788 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 20346662 # DTB read accesses
-system.cpu0.dtb.write_accesses 16392100 # DTB write accesses
+system.cpu0.dtb.read_accesses 20346646 # DTB read accesses
+system.cpu0.dtb.write_accesses 16392091 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 36730798 # DTB hits
+system.cpu0.dtb.hits 36730773 # DTB hits
system.cpu0.dtb.misses 7964 # DTB misses
-system.cpu0.dtb.accesses 36738762 # DTB accesses
+system.cpu0.dtb.accesses 36738737 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 97439560 # ITB inst hits
+system.cpu0.itb.inst_hits 97439484 # ITB inst hits
system.cpu0.itb.inst_misses 3358 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 97442918 # ITB inst accesses
-system.cpu0.itb.hits 97439560 # DTB hits
+system.cpu0.itb.inst_accesses 97442842 # ITB inst accesses
+system.cpu0.itb.hits 97439484 # DTB hits
system.cpu0.itb.misses 3358 # DTB misses
-system.cpu0.itb.accesses 97442918 # DTB accesses
-system.cpu0.numCycles 5605767393 # number of cpu cycles simulated
+system.cpu0.itb.accesses 97442842 # DTB accesses
+system.cpu0.numCycles 5605767234 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 95427097 # Number of instructions committed
-system.cpu0.committedOps 115560530 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 100762762 # Number of integer alu accesses
+system.cpu0.committedInsts 95427026 # Number of instructions committed
+system.cpu0.committedOps 115560441 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 100762684 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
-system.cpu0.num_func_calls 8000275 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 13204265 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 100762762 # number of integer instructions
+system.cpu0.num_func_calls 8000257 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 13204260 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 100762684 # number of integer instructions
system.cpu0.num_fp_insts 9755 # number of float instructions
-system.cpu0.num_int_register_reads 182457576 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 69135597 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 182457418 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 69135520 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 349971872 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 44907557 # number of times the CC registers were written
-system.cpu0.num_mem_refs 37873781 # number of memory refs
-system.cpu0.num_load_insts 20597370 # Number of load instructions
-system.cpu0.num_store_insts 17276411 # Number of store instructions
-system.cpu0.num_idle_cycles 5488182740.223901 # Number of idle cycles
-system.cpu0.num_busy_cycles 117584652.776099 # Number of busy cycles
+system.cpu0.num_cc_register_reads 349971578 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 44907537 # number of times the CC registers were written
+system.cpu0.num_mem_refs 37873766 # number of memory refs
+system.cpu0.num_load_insts 20597356 # Number of load instructions
+system.cpu0.num_store_insts 17276410 # Number of store instructions
+system.cpu0.num_idle_cycles 5488182675.223932 # Number of idle cycles
+system.cpu0.num_busy_cycles 117584558.776067 # Number of busy cycles
system.cpu0.not_idle_fraction 0.020976 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.979024 # Percentage of idle cycles
-system.cpu0.Branches 21941666 # Number of branches fetched
+system.cpu0.Branches 21941641 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2273 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 78887449 67.49% 67.50% # Class of executed instruction
-system.cpu0.op_class::IntMult 110639 0.09% 67.59% # Class of executed instruction
+system.cpu0.op_class::IntAlu 78887374 67.49% 67.50% # Class of executed instruction
+system.cpu0.op_class::IntMult 110635 0.09% 67.59% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 67.59% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 67.60% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 67.60% # Class of executed instruction
-system.cpu0.op_class::MemRead 20597370 17.62% 85.22% # Class of executed instruction
-system.cpu0.op_class::MemWrite 17276411 14.78% 100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead 20597356 17.62% 85.22% # Class of executed instruction
+system.cpu0.op_class::MemWrite 17276410 14.78% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 116882229 # Class of executed instruction
+system.cpu0.op_class::total 116882135 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 1965 # number of quiesce instructions executed
+system.cpu0.dcache.tags.replacements 693468 # number of replacements
+system.cpu0.dcache.tags.tagsinuse 494.853471 # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs 35932329 # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs 51.777182 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853471 # Average occupied blocks per requestor
+system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
+system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
+system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu0.dcache.tags.tag_accesses 74113668 # Number of tag accesses
+system.cpu0.dcache.tags.data_accesses 74113668 # Number of data accesses
+system.cpu0.dcache.ReadReq_hits::cpu0.data 19108613 # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total 19108613 # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data 15690292 # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total 15690292 # number of WriteReq hits
+system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits
+system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363025 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::total 363025 # number of StoreCondReq hits
+system.cpu0.dcache.demand_hits::cpu0.data 34798905 # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total 34798905 # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data 35144985 # number of overall hits
+system.cpu0.dcache.overall_hits::total 35144985 # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data 295766 # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total 295766 # number of WriteReq misses
+system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses
+system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18448 # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::total 18448 # number of StoreCondReq misses
+system.cpu0.dcache.demand_misses::cpu0.data 668860 # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total 668860 # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data 769182 # number of overall misses
+system.cpu0.dcache.overall_misses::total 769182 # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481707 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total 19481707 # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986058 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total 15986058 # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data 35467765 # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total 35467765 # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data 35914167 # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total 35914167 # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses
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-system.cpu0.l2cache.ReadReq_miss_rate::total 0.108301 # miss rate for ReadReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999352 # miss rate for UpgradeReq accesses
-system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999352 # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.overall_accesses::total 1871102 # number of overall (read+write) accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.036219 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040512 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.267030 # miss rate for ReadReq accesses
+system.cpu0.l2cache.ReadReq_miss_rate::total 0.108346 # miss rate for ReadReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.999391 # miss rate for UpgradeReq accesses
+system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.999391 # miss rate for UpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650430 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650430 # miss rate for ReadExReq accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.035364 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040474 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404826 # miss rate for demand accesses
-system.cpu0.l2cache.demand_miss_rate::total 0.186394 # miss rate for demand accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026255 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.035364 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040474 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404826 # miss rate for overall accesses
-system.cpu0.l2cache.overall_miss_rate::total 0.186394 # miss rate for overall accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.650322 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.ReadExReq_miss_rate::total 0.650322 # miss rate for ReadExReq accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.036219 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040512 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.404827 # miss rate for demand accesses
+system.cpu0.l2cache.demand_miss_rate::total 0.186412 # miss rate for demand accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.026763 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.036219 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040512 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.404827 # miss rate for overall accesses
+system.cpu0.l2cache.overall_miss_rate::total 0.186412 # miss rate for overall accesses
system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.l2cache.fast_writes 0 # number of fast writes performed
system.cpu0.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu0.l2cache.writebacks::writebacks 192916 # number of writebacks
-system.cpu0.l2cache.writebacks::total 192916 # number of writebacks
+system.cpu0.l2cache.writebacks::writebacks 192870 # number of writebacks
+system.cpu0.l2cache.writebacks::total 192870 # number of writebacks
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 693468 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 494.853462 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 35932354 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 693980 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 51.777218 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 23661500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.853462 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.966511 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.966511 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 277 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 205 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 74113718 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 74113718 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 19108629 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 19108629 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 15690304 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 15690304 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 346080 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 346080 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 379619 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 379619 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 363029 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 363029 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 34798933 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 34798933 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 35145013 # number of overall hits
-system.cpu0.dcache.overall_hits::total 35145013 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 373094 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 373094 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 295763 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 295763 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 100322 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 100322 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6740 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 6740 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 18444 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 18444 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 668857 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 668857 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 769179 # number of overall misses
-system.cpu0.dcache.overall_misses::total 769179 # number of overall misses
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 19481723 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 19481723 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 15986067 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 15986067 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 446402 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 446402 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386359 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 386359 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381473 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 381473 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 35467790 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 35467790 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 35914192 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 35914192 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.019151 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.019151 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018501 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.018501 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224735 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.224735 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.017445 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.017445 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.048349 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.048349 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.018858 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.018858 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.021417 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.021417 # miss rate for overall accesses
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 511617 # number of writebacks
-system.cpu0.dcache.writebacks::total 511617 # number of writebacks
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.toL2Bus.trans_dist::ReadReq 1651731 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadResp 1651731 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteReq 28400 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteResp 28400 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 511617 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 26249 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18444 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 44693 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 511566 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 26252 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 18448 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 44700 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExReq 269514 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::ReadExResp 269514 # Transaction distribution
system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2238348 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220321 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2220284 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12828 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 28796 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 4500293 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 4500256 # Packet count per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 71085816 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80913146 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80909882 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 25656 # Cumulative packet size per connected master and slave (bytes)
system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 57592 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 152082210 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 322119 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 2656456 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.082633 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.275327 # Request fanout histogram
+system.cpu0.toL2Bus.pkt_size::total 152078946 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 322137 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 2656435 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.082643 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.275341 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 2436944 91.74% 91.74% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 219512 8.26% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 2436900 91.74% 91.74% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 219535 8.26% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 2656456 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::total 2656435 # Request fanout histogram
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 12173926 # DTB read hits
+system.cpu1.dtb.read_hits 12173905 # DTB read hits
system.cpu1.dtb.read_misses 2853 # DTB read misses
-system.cpu1.dtb.write_hits 7587211 # DTB write hits
+system.cpu1.dtb.write_hits 7587201 # DTB write hits
system.cpu1.dtb.write_misses 506 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.prefetch_faults 290 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 12176779 # DTB read accesses
-system.cpu1.dtb.write_accesses 7587717 # DTB write accesses
+system.cpu1.dtb.read_accesses 12176758 # DTB read accesses
+system.cpu1.dtb.write_accesses 7587707 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 19761137 # DTB hits
+system.cpu1.dtb.hits 19761106 # DTB hits
system.cpu1.dtb.misses 3359 # DTB misses
-system.cpu1.dtb.accesses 19764496 # DTB accesses
+system.cpu1.dtb.accesses 19764465 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 53671662 # ITB inst hits
+system.cpu1.itb.inst_hits 53671578 # ITB inst hits
system.cpu1.itb.inst_misses 1734 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 53673396 # ITB inst accesses
-system.cpu1.itb.hits 53671662 # DTB hits
+system.cpu1.itb.inst_accesses 53673312 # ITB inst accesses
+system.cpu1.itb.hits 53671578 # DTB hits
system.cpu1.itb.misses 1734 # DTB misses
-system.cpu1.itb.accesses 53673396 # DTB accesses
-system.cpu1.numCycles 5605296302 # number of cpu cycles simulated
+system.cpu1.itb.accesses 53673312 # DTB accesses
+system.cpu1.numCycles 5605296143 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 51401401 # Number of instructions committed
-system.cpu1.committedOps 63347692 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 56984315 # Number of integer alu accesses
+system.cpu1.committedInsts 51401324 # Number of instructions committed
+system.cpu1.committedOps 63347594 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 56984226 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
-system.cpu1.num_func_calls 9170855 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 5967102 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 56984315 # number of integer instructions
+system.cpu1.num_func_calls 9170833 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 5967095 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 56984226 # number of integer instructions
system.cpu1.num_fp_insts 1792 # number of float instructions
-system.cpu1.num_int_register_reads 110674840 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 41298430 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 110674651 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 41298354 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 196268898 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 18894414 # number of times the CC registers were written
-system.cpu1.num_mem_refs 20026390 # number of memory refs
-system.cpu1.num_load_insts 12289548 # Number of load instructions
-system.cpu1.num_store_insts 7736842 # Number of store instructions
-system.cpu1.num_idle_cycles 5539682707.595543 # Number of idle cycles
-system.cpu1.num_busy_cycles 65613594.404457 # Number of busy cycles
+system.cpu1.num_cc_register_reads 196268580 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 18894392 # number of times the CC registers were written
+system.cpu1.num_mem_refs 20026364 # number of memory refs
+system.cpu1.num_load_insts 12289528 # Number of load instructions
+system.cpu1.num_store_insts 7736836 # Number of store instructions
+system.cpu1.num_idle_cycles 5539682653.586912 # Number of idle cycles
+system.cpu1.num_busy_cycles 65613489.413088 # Number of busy cycles
system.cpu1.not_idle_fraction 0.011706 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.988294 # Percentage of idle cycles
-system.cpu1.Branches 15217497 # Number of branches fetched
+system.cpu1.Branches 15217468 # Number of branches fetched
system.cpu1.op_class::No_OpClass 66 0.00% 0.00% # Class of executed instruction
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system.cpu1.op_class::IntDiv 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 69.40% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.41% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.41% # Class of executed instruction
-system.cpu1.op_class::MemRead 12289548 18.77% 88.18% # Class of executed instruction
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system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 65459543 # Class of executed instruction
+system.cpu1.op_class::total 65459439 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed
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+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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system.cpu1.icache.tags.replacements 523402 # number of replacements
system.cpu1.icache.tags.tagsinuse 499.711076 # Cycle average of tags in use
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system.cpu1.icache.tags.sampled_refs 523914 # Sample count of references to valid blocks.
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system.cpu1.icache.tags.warmup_cycle 76931404500 # Cycle when the warmup percentage was hit.
system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.711076 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975998 # Average percentage of cache occupancy
system.cpu1.icache.tags.age_task_id_blocks_1024::2 477 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::3 35 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
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system.cpu1.icache.ReadReq_miss_rate::total 0.009761 # miss rate for ReadReq accesses
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.009761 # miss rate for demand accesses
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 0 # number of hwpf issued
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.l2cache.Writeback_hits::total 120654 # number of Writeback hits
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system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 7 # number of UpgradeReq hits
system.cpu1.l2cache.UpgradeReq_hits::total 7 # number of UpgradeReq hits
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system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.999757 # miss rate for UpgradeReq accesses
system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.999757 # miss rate for UpgradeReq accesses
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system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu1.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.l2cache.fast_writes 0 # number of fast writes performed
system.cpu1.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu1.dcache.tags.sampled_refs 192301 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 101.421807 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 105851601500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.736016 # Average occupied blocks per requestor
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-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.380089 # miss rate for SoftPFReq accesses
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-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054958 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.237495 # miss rate for StoreCondReq accesses
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-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
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-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.toL2Bus.trans_dist::ReadReq 709339 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadResp 709339 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteReq 2505 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteResp 2505 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 120654 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 28862 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22557 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 51419 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 120692 # Transaction distribution
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+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 22559 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 51422 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExReq 63615 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::ReadExResp 63615 # Transaction distribution
system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1048182 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 707532 # Packet count per connected master and slave (bytes)
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system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6616 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 12080 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 1774410 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 1774454 # Packet count per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 33531204 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22863598 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 22866030 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13232 # Cumulative packet size per connected master and slave (bytes)
system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 24160 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 56432194 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 499552 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1371519 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.313444 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.463893 # Request fanout histogram
+system.cpu1.toL2Bus.pkt_size::total 56434626 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 499621 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1371622 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.313465 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.463902 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 941625 68.66% 68.66% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 429894 31.34% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 941666 68.65% 68.65% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 429956 31.35% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
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system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 246641286009 # Cycle when the warmup percentage was hit.
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system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.l2c.overall_miss_rate::cpu1.inst 0.170391 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.539037 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.560995 # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks::writebacks 94871 # number of writebacks
+system.l2c.writebacks::total 94871 # number of writebacks
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 75959 # Transaction distribution
+system.membus.trans_dist::ReadResp 75959 # Transaction distribution
+system.membus.trans_dist::WriteReq 30905 # Transaction distribution
+system.membus.trans_dist::WriteResp 30905 # Transaction distribution
+system.membus.trans_dist::Writeback 94871 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 60398 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 40937 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 15640 # Transaction distribution
+system.membus.trans_dist::ReadExReq 196324 # Transaction distribution
+system.membus.trans_dist::ReadExResp 152195 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107918 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13474 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 652163 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 773589 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72952 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72952 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 846541 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162808 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 26948 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 17897572 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18087396 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2334464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2334464 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 20421860 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 460700 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 460700 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 460700 # Request fanout histogram
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 305363 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 305363 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 30905 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 30905 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 225809 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 60563 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 41007 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 101570 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 213619 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 213619 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1117852 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 410871 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1528723 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34663730 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 10432818 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 45096548 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 36713 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 838824 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.043485 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.203946 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 802348 95.65% 95.65% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36476 4.35% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 838824 # Request fanout histogram
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 2.783854 # Number of seconds simulated
-sim_ticks 2783854177000 # Number of ticks simulated
-final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2783854461500 # Number of ticks simulated
+final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1378246 # Simulator instruction rate (inst/s)
-host_op_rate 1677793 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 26874016957 # Simulator tick rate (ticks/s)
-host_mem_usage 553624 # Number of bytes of host memory used
-host_seconds 103.59 # Real time elapsed on the host
-sim_insts 142771179 # Number of instructions simulated
-sim_ops 173800939 # Number of ops (including micro ops) simulated
+host_inst_rate 1414038 # Simulator instruction rate (inst/s)
+host_op_rate 1721363 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 27571822204 # Simulator tick rate (ticks/s)
+host_mem_usage 560116 # Number of bytes of host memory used
+host_seconds 100.97 # Real time elapsed on the host
+sim_insts 142771592 # Number of instructions simulated
+sim_ops 173801445 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1210980 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10345892 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 11558408 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1210980 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6521536 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::total 8857396 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 27375 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 162174 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 189573 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 101899 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::total 142504 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 161 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 46 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 435001 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3716391 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 4151944 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 435001 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 2342628 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6295 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3181703 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3181702 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 2342628 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 161 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 46 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 435001 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3722686 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7333647 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7333646 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 74235 # Transaction distribution
-system.membus.trans_dist::ReadResp 74235 # Transaction distribution
-system.membus.trans_dist::WriteReq 27560 # Transaction distribution
-system.membus.trans_dist::WriteResp 27560 # Transaction distribution
-system.membus.trans_dist::Writeback 101899 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
-system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
-system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 322858 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 322858 # Request fanout histogram
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
-system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 31525864 # DTB read hits
+system.cpu.dtb.read_hits 31525959 # DTB read hits
system.cpu.dtb.read_misses 8580 # DTB read misses
-system.cpu.dtb.write_hits 23124034 # DTB write hits
+system.cpu.dtb.write_hits 23124081 # DTB write hits
system.cpu.dtb.write_misses 1448 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.prefetch_faults 1613 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 31534444 # DTB read accesses
-system.cpu.dtb.write_accesses 23125482 # DTB write accesses
+system.cpu.dtb.read_accesses 31534539 # DTB read accesses
+system.cpu.dtb.write_accesses 23125529 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 54649898 # DTB hits
+system.cpu.dtb.hits 54650040 # DTB hits
system.cpu.dtb.misses 10028 # DTB misses
-system.cpu.dtb.accesses 54659926 # DTB accesses
+system.cpu.dtb.accesses 54660068 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 147037671 # ITB inst hits
+system.cpu.itb.inst_hits 147038107 # ITB inst hits
system.cpu.itb.inst_misses 4762 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 147042433 # ITB inst accesses
-system.cpu.itb.hits 147037671 # DTB hits
+system.cpu.itb.inst_accesses 147042869 # ITB inst accesses
+system.cpu.itb.hits 147038107 # DTB hits
system.cpu.itb.misses 4762 # DTB misses
-system.cpu.itb.accesses 147042433 # DTB accesses
-system.cpu.numCycles 5567711435 # number of cpu cycles simulated
+system.cpu.itb.accesses 147042869 # DTB accesses
+system.cpu.numCycles 5567712004 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 142771179 # Number of instructions committed
-system.cpu.committedOps 173800939 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 153160639 # Number of integer alu accesses
+system.cpu.committedInsts 142771592 # Number of instructions committed
+system.cpu.committedOps 173801445 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 153161099 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11484 # Number of float alu accesses
-system.cpu.num_func_calls 16873782 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 18730247 # number of instructions that are conditional controls
-system.cpu.num_int_insts 153160639 # number of integer instructions
+system.cpu.num_func_calls 16873874 # number of times a function call or return occured
+system.cpu.num_conditional_control_insts 18730301 # number of instructions that are conditional controls
+system.cpu.num_int_insts 153161099 # number of integer instructions
system.cpu.num_fp_insts 11484 # number of float instructions
-system.cpu.num_int_register_reads 285056343 # number of times the integer registers were read
-system.cpu.num_int_register_writes 107177999 # number of times the integer registers were written
+system.cpu.num_int_register_reads 285057250 # number of times the integer registers were read
+system.cpu.num_int_register_writes 107178308 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8772 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 530847533 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 62363805 # number of times the CC registers were written
-system.cpu.num_mem_refs 55938446 # number of memory refs
-system.cpu.num_load_insts 31855497 # Number of load instructions
-system.cpu.num_store_insts 24082949 # Number of store instructions
-system.cpu.num_idle_cycles 5389630153.939368 # Number of idle cycles
-system.cpu.num_busy_cycles 178081281.060631 # Number of busy cycles
+system.cpu.num_cc_register_reads 530849099 # number of times the CC registers were read
+system.cpu.num_cc_register_writes 62363961 # number of times the CC registers were written
+system.cpu.num_mem_refs 55938603 # number of memory refs
+system.cpu.num_load_insts 31855595 # Number of load instructions
+system.cpu.num_store_insts 24083008 # Number of store instructions
+system.cpu.num_idle_cycles 5389630193.939086 # Number of idle cycles
+system.cpu.num_busy_cycles 178081810.060914 # Number of busy cycles
system.cpu.not_idle_fraction 0.031985 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.968015 # Percentage of idle cycles
-system.cpu.Branches 36396779 # Number of branches fetched
+system.cpu.Branches 36396923 # Number of branches fetched
system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
-system.cpu.op_class::IntAlu 121151526 68.36% 68.36% # Class of executed instruction
-system.cpu.op_class::IntMult 116878 0.07% 68.43% # Class of executed instruction
+system.cpu.op_class::IntAlu 121151902 68.36% 68.36% # Class of executed instruction
+system.cpu.op_class::IntMult 116873 0.07% 68.43% # Class of executed instruction
system.cpu.op_class::IntDiv 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 68.43% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.44% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.44% # Class of executed instruction
-system.cpu.op_class::MemRead 31855497 17.98% 86.41% # Class of executed instruction
-system.cpu.op_class::MemWrite 24082949 13.59% 100.00% # Class of executed instruction
+system.cpu.op_class::MemRead 31855595 17.98% 86.41% # Class of executed instruction
+system.cpu.op_class::MemWrite 24083008 13.59% 100.00% # Class of executed instruction
system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 177217756 # Class of executed instruction
+system.cpu.op_class::total 177218284 # Class of executed instruction
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3080 # number of quiesce instructions executed
+system.cpu.dcache.tags.replacements 819396 # number of replacements
+system.cpu.dcache.tags.tagsinuse 511.997174 # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs 53783832 # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs 819908 # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs 65.597399 # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data 511.997174 # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1 196 # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2 30 # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses 219234948 # Number of tag accesses
+system.cpu.dcache.tags.data_accesses 219234948 # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data 30128799 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 30128799 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 22339754 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 22339754 # number of WriteReq hits
+system.cpu.dcache.SoftPFReq_hits::cpu.data 395065 # number of SoftPFReq hits
+system.cpu.dcache.SoftPFReq_hits::total 395065 # number of SoftPFReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 457334 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 457334 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 460122 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 460122 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 52468553 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 52468553 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 52863618 # number of overall hits
+system.cpu.dcache.overall_hits::total 52863618 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 396285 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 396285 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 301663 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 301663 # number of WriteReq misses
+system.cpu.dcache.SoftPFReq_misses::cpu.data 116121 # number of SoftPFReq misses
+system.cpu.dcache.SoftPFReq_misses::total 116121 # number of SoftPFReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 8611 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 8611 # number of LoadLockedReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
+system.cpu.dcache.demand_misses::cpu.data 697948 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 697948 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 814069 # number of overall misses
+system.cpu.dcache.overall_misses::total 814069 # number of overall misses
+system.cpu.dcache.ReadReq_accesses::cpu.data 30525084 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 30525084 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 22641417 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 22641417 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::cpu.data 511186 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.SoftPFReq_accesses::total 511186 # number of SoftPFReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 465945 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 465945 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 460124 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total 460124 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 53166501 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 53166501 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 53677687 # number of overall (read+write) accesses
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+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.012982 # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::total 0.012982 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013324 # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::total 0.013324 # miss rate for WriteReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.227160 # miss rate for SoftPFReq accesses
+system.cpu.dcache.SoftPFReq_miss_rate::total 0.227160 # miss rate for SoftPFReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.018481 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.013128 # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::total 0.013128 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.015166 # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::total 0.015166 # miss rate for overall accesses
+system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu.dcache.fast_writes 0 # number of fast writes performed
+system.cpu.dcache.cache_copies 0 # number of cache copies performed
+system.cpu.dcache.writebacks::writebacks 682037 # number of writebacks
+system.cpu.dcache.writebacks::total 682037 # number of writebacks
+system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.icache.tags.replacements 1699006 # number of replacements
system.cpu.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 145341254 # Total number of references to valid blocks.
+system.cpu.icache.tags.total_refs 145341690 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks.
+system.cpu.icache.tags.avg_refs 85.519359 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 511.663679 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.999343 # Average percentage of cache occupancy
system.cpu.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 148740302 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 148740302 # Number of data accesses
-system.cpu.icache.ReadReq_hits::cpu.inst 145341254 # number of ReadReq hits
-system.cpu.icache.ReadReq_hits::total 145341254 # number of ReadReq hits
-system.cpu.icache.demand_hits::cpu.inst 145341254 # number of demand (read+write) hits
-system.cpu.icache.demand_hits::total 145341254 # number of demand (read+write) hits
-system.cpu.icache.overall_hits::cpu.inst 145341254 # number of overall hits
-system.cpu.icache.overall_hits::total 145341254 # number of overall hits
+system.cpu.icache.tags.tag_accesses 148740738 # Number of tag accesses
+system.cpu.icache.tags.data_accesses 148740738 # Number of data accesses
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+system.cpu.icache.ReadReq_hits::total 145341690 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 145341690 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 145341690 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1699524 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1699524 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1699524 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1699524 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1699524 # number of overall misses
system.cpu.icache.overall_misses::total 1699524 # number of overall misses
-system.cpu.icache.ReadReq_accesses::cpu.inst 147040778 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_accesses::total 147040778 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::cpu.inst 147040778 # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::total 147040778 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::cpu.inst 147040778 # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::total 147040778 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_accesses::cpu.inst 147041214 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 147041214 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 147041214 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 147041214 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 147041214 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.011558 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.011558 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.011558 # miss rate for demand accesses
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000552 # miss rate for ReadReq accesses
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system.cpu.l2cache.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.writebacks::writebacks 101899 # number of writebacks
system.cpu.l2cache.writebacks::total 101899 # number of writebacks
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.018481 # miss rate for LoadLockedReq accesses
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-system.cpu.toL2Bus.trans_dist::ReadResp 2288345 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 682036 # Transaction distribution
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system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
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-system.cpu.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution
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+system.cpu.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
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system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18430 # Packet count per connected master and slave (bytes)
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system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 36860 # Cumulative packet size per connected master and slave (bytes)
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system.cpu.toL2Bus.snoops 36632 # Total snoops (count)
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system.cpu.toL2Bus.snoop_fanout::mean 5.011156 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.105033 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 3231951 98.88% 98.88% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 3231956 98.88% 98.88% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 36464 1.12% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3268415 # Request fanout histogram
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+system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
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+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
system.iocache.tags.replacements 36430 # number of replacements
-system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use
+system.iocache.tags.tagsinuse 0.909893 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 0.909891 # Average occupied blocks per requestor
+system.iocache.tags.occ_blocks::realview.ide 0.909893 # Average occupied blocks per requestor
system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 74235 # Transaction distribution
+system.membus.trans_dist::ReadResp 74235 # Transaction distribution
+system.membus.trans_dist::WriteReq 27560 # Transaction distribution
+system.membus.trans_dist::WriteResp 27560 # Transaction distribution
+system.membus.trans_dist::Writeback 101899 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
+system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
+system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 498795 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 606197 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 679125 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 18096508 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 18259523 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 20593219 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 322858 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 322858 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 322858 # Request fanout histogram
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 2.866923 # Number of seconds simulated
-sim_ticks 2866923142000 # Number of ticks simulated
-final_tick 2866923142000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.866913 # Number of seconds simulated
+sim_ticks 2866913114000 # Number of ticks simulated
+final_tick 2866913114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 699616 # Simulator instruction rate (inst/s)
-host_op_rate 846245 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 15203294122 # Simulator tick rate (ticks/s)
-host_mem_usage 599680 # Number of bytes of host memory used
-host_seconds 188.57 # Real time elapsed on the host
-sim_insts 131928295 # Number of instructions simulated
-sim_ops 159578500 # Number of ops (including micro ops) simulated
+host_inst_rate 786450 # Simulator instruction rate (inst/s)
+host_op_rate 951292 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17090693254 # Simulator tick rate (ticks/s)
+host_mem_usage 609256 # Number of bytes of host memory used
+host_seconds 167.75 # Real time elapsed on the host
+sim_insts 131924636 # Number of instructions simulated
+sim_ops 159576421 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 512 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 235364 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 833280 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 9630848 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 236004 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 838784 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.l2cache.prefetcher 9619456 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 49876 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 438560 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 1365696 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12555416 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 235364 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 49876 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 285240 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 6390016 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu1.inst 50964 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 440736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.l2cache.prefetcher 1362944 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
+system.physmem.bytes_read::total 12550680 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 236004 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 50964 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 286968 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 6395008 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8726096 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8731088 # Number of bytes written to this memory
system.physmem.num_reads::cpu0.dtb.walker 8 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 12131 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 13546 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 150482 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 12141 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 13632 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.l2cache.prefetcher 150304 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 934 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 6876 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.l2cache.prefetcher 21339 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 205336 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 99844 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 951 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 6910 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.l2cache.prefetcher 21296 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 205262 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 99922 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 140504 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 140582 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu0.dtb.walker 179 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 82096 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 290653 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.l2cache.prefetcher 3359298 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 82320 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 292574 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.l2cache.prefetcher 3355336 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 67 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 17397 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 152972 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.l2cache.prefetcher 476363 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4379404 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 82096 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 17397 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 99493 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2228876 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 808650 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 17777 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 153732 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.l2cache.prefetcher 475405 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 335 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4377768 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 82320 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 17777 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 100097 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2230625 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6175 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3043715 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2228876 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 808984 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 808652 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3045467 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2230625 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 179 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 82096 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 296828 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.l2cache.prefetcher 3359298 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 82320 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 298749 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.l2cache.prefetcher 3355336 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 67 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 17397 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 152986 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.l2cache.prefetcher 476363 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7423119 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 205337 # Number of read requests accepted
-system.physmem.writeReqs 140504 # Number of write requests accepted
-system.physmem.readBursts 205337 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 140504 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 13124800 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 16768 # Total number of bytes read from write queue
-system.physmem.bytesWritten 8739776 # Total number of bytes written to DRAM
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system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 7 # Number of times write queue was full causing retry
-system.physmem.totGap 2866922767000 # Total gap between requests
+system.physmem.totGap 2866912757000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 9742 # Read request sizes (log2)
system.physmem.readPktSize::3 28 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 4436 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
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-system.physmem.rdPerTurnAround::mean 30.551698 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 6712 # Reads before turning the bus around for writes
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-system.physmem.wrPerTurnAround::mean 20.345501 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.833911 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 11.781170 # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::20-23 369 5.50% 87.71% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 92 1.37% 89.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 214 3.19% 92.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 187 2.79% 95.05% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::44-47 17 0.25% 95.83% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::48-51 32 0.48% 96.31% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::52-55 6 0.09% 96.39% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::56-59 6 0.09% 96.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::60-63 6 0.09% 96.57% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::64-67 162 2.41% 98.99% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::68-71 6 0.09% 99.08% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::72-75 9 0.13% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::76-79 4 0.06% 99.27% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::80-83 13 0.19% 99.46% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::84-87 1 0.01% 99.48% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::88-91 2 0.03% 99.51% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::92-95 2 0.03% 99.54% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 6722 # Reads before turning the bus around for writes
+system.physmem.wrPerTurnAround::samples 6722 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::mean 20.326837 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::gmean 18.830242 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::stdev 11.742760 # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::16-19 5511 81.98% 81.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::20-23 381 5.67% 87.65% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::24-27 92 1.37% 89.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::28-31 211 3.14% 92.16% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::32-35 209 3.11% 95.27% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::36-39 21 0.31% 95.58% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::40-43 13 0.19% 95.78% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::44-47 14 0.21% 95.98% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::48-51 24 0.36% 96.34% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::52-55 8 0.12% 96.46% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::56-59 5 0.07% 96.53% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::60-63 4 0.06% 96.59% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::64-67 163 2.42% 99.02% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::68-71 8 0.12% 99.14% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::72-75 4 0.06% 99.20% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::76-79 3 0.04% 99.24% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::80-83 17 0.25% 99.49% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::84-87 1 0.01% 99.51% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::88-91 1 0.01% 99.52% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::92-95 1 0.01% 99.54% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::96-99 7 0.10% 99.64% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::100-103 3 0.04% 99.69% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::112-115 3 0.04% 99.81% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::116-119 2 0.03% 99.84% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::120-123 1 0.01% 99.85% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::124-127 1 0.01% 99.87% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::128-131 3 0.04% 99.91% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::132-135 2 0.03% 99.94% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::140-143 2 0.03% 99.97% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::144-147 2 0.03% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 6712 # Writes before turning the bus around for reads
-system.physmem.totQLat 6009454502 # Total ticks spent queuing
-system.physmem.totMemAccLat 9854610752 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 1025375000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 29303.69 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::108-111 3 0.04% 99.69% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::112-115 7 0.10% 99.79% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::116-119 2 0.03% 99.82% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::124-127 1 0.01% 99.84% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::128-131 8 0.12% 99.96% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::140-143 2 0.03% 99.99% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::152-155 1 0.01% 100.00% # Writes before turning the bus around for reads
+system.physmem.wrPerTurnAround::total 6722 # Writes before turning the bus around for reads
+system.physmem.totQLat 5976562250 # Total ticks spent queuing
+system.physmem.totMemAccLat 9820537250 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 1025060000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 29152.26 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 48053.69 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 47902.26 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 4.58 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.05 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 4.38 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.04 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.05 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.98 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 22.49 # Average write queue length when enqueuing
+system.physmem.avgRdQLen 2.00 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 23.80 # Average write queue length when enqueuing
system.physmem.readRowHits 175010 # Number of row buffer hits during reads
-system.physmem.writeRowHits 85502 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.34 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 62.60 # Row buffer hit rate for writes
-system.physmem.avgGap 8289713.39 # Average gap between requests
-system.physmem.pageHitRate 76.25 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2731290601750 # Time in different power states
-system.physmem.memoryStateTime::REF 95732780000 # Time in different power states
+system.physmem.writeRowHits 85700 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 85.37 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 62.71 # Row buffer hit rate for writes
+system.physmem.avgGap 8289588.56 # Average gap between requests
+system.physmem.pageHitRate 76.30 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 2731202883250 # Time in different power states
+system.physmem.memoryStateTime::REF 95732520000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 39899739250 # Time in different power states
+system.physmem.memoryStateTime::ACT 39977707750 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 323265600 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 290009160 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 176385000 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 158239125 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 861853200 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 737724000 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 456230880 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 428671440 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 187253317680 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 187253317680 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 82699072155 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 81115825050 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1647609467250 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1648998280500 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1919379591765 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1918982066955 # Total energy per rank (pJ)
-system.physmem.averagePower::0 669.491656 # Core power per rank (mW)
-system.physmem.averagePower::1 669.352997 # Core power per rank (mW)
+system.physmem.actEnergy::0 322237440 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 289653840 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 175824000 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 158045250 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 861650400 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 737435400 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 456399360 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 429008400 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 187252809120 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 187252809120 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 82565899920 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 81397166220 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1647721613250 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1648746818250 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1919356433490 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1919010936480 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.485397 # Core power per rank (mW)
+system.physmem.averagePower::1 669.364885 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.inst 17 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 24 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 228669 # Transaction distribution
-system.membus.trans_dist::ReadResp 228668 # Transaction distribution
-system.membus.trans_dist::WriteReq 31179 # Transaction distribution
-system.membus.trans_dist::WriteResp 31179 # Transaction distribution
-system.membus.trans_dist::Writeback 99844 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 85785 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 41193 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 15133 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution
-system.membus.trans_dist::ReadExReq 28316 # Transaction distribution
-system.membus.trans_dist::ReadExResp 11444 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14564 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678346 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 800908 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 873624 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29128 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962216 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 19154259 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 21473555 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 128959 # Total snoops (count)
-system.membus.snoop_fanout::samples 475734 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 475734 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 475734 # Request fanout histogram
-system.membus.reqLayer0.occupancy 88166499 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 12097497 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1514306999 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1971607923 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer3.occupancy 38585418 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 132855 # number of replacements
-system.l2c.tags.tagsinuse 64219.366353 # Cycle average of tags in use
-system.l2c.tags.total_refs 486769 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 197473 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 2.464990 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 12668.220978 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.836009 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999655 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 1159.806509 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 1415.804508 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 38683.036536 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 1.697637 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 0.007796 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 527.060368 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 909.811701 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 8848.084656 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.193302 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000074 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.017697 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.021603 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.590256 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000026 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.008042 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.013883 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.135011 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.979910 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022 45009 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 19601 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2 202 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3 5222 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4 39585 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 11 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 202 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 1500 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 17888 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1022 0.686783 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000122 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.299088 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 6123027 # Number of tag accesses
-system.l2c.tags.data_accesses 6123027 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 138 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 133 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 10210 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 28863 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 166586 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 49 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 46 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 4197 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 10271 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 47730 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 268223 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 239796 # number of Writeback hits
-system.l2c.Writeback_hits::total 239796 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 9662 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 934 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 10596 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 248 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 151 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 399 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 4158 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 2526 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 6684 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 138 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 133 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 10210 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 33021 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.l2cache.prefetcher 166586 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 49 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 46 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 4197 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 12797 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.l2cache.prefetcher 47730 # number of demand (read+write) hits
-system.l2c.demand_hits::total 274907 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 138 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 133 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 10210 # number of overall hits
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-system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 42794256 # number of UpgradeReq MSHR miss cycles
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-system.l2c.overall_mshr_miss_latency::total 16889566029 # number of overall MSHR miss cycles
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-system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 712688499 # number of WriteReq MSHR uncacheable cycles
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-system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 476661000 # number of overall MSHR uncacheable cycles
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-system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for ReadReq accesses
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-system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.120999 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.407020 # mshr miss rate for ReadReq accesses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.820316 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.546462 # mshr miss rate for UpgradeReq accesses
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-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.896575 # mshr miss rate for SCUpgradeReq accesses
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-system.l2c.ReadExReq_mshr_miss_rate::total 0.634834 # mshr miss rate for ReadExReq accesses
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-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.233714 # mshr miss rate for demand accesses
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-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.057692 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.021277 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308952 # mshr miss rate for demand accesses
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-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.154853 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.350883 # mshr miss rate for overall accesses
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 76250 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74375.353607 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 95272.427902 # average ReadReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10036.176360 # average UpgradeReq mshr miss latency
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-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10035.757830 # average SCUpgradeReq mshr miss latency
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-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74153.741169 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68756.576994 # average overall mshr miss latency
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-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77883.613784 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62546.265828 # average overall mshr miss latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
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-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
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-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
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-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
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-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
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-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 631517 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 631501 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 31179 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 31179 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 239796 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 96205 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 41592 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 137797 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 39833 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 39833 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1252484 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399771 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 1652255 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37452048 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8279747 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 45731795 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 304794 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 1040942 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.035049 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.183904 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 1004458 96.50% 96.50% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 1040942 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 1516413702 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 2125399996 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 850129169 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 31019 # Transaction distribution
-system.iobus.trans_dist::ReadResp 31019 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59414 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq 26 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 326665578 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36844582 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 24351510 # DTB read hits
-system.cpu0.dtb.read_misses 6410 # DTB read misses
-system.cpu0.dtb.write_hits 18124813 # DTB write hits
-system.cpu0.dtb.write_misses 1105 # DTB write misses
+system.cpu0.dtb.read_hits 24351477 # DTB read hits
+system.cpu0.dtb.read_misses 6408 # DTB read misses
+system.cpu0.dtb.write_hits 18124986 # DTB write hits
+system.cpu0.dtb.write_misses 1114 # DTB write misses
system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3401 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 3406 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 1454 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 1440 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 282 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 24357920 # DTB read accesses
-system.cpu0.dtb.write_accesses 18125918 # DTB write accesses
+system.cpu0.dtb.read_accesses 24357885 # DTB read accesses
+system.cpu0.dtb.write_accesses 18126100 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 42476323 # DTB hits
-system.cpu0.dtb.misses 7515 # DTB misses
-system.cpu0.dtb.accesses 42483838 # DTB accesses
+system.cpu0.dtb.hits 42476463 # DTB hits
+system.cpu0.dtb.misses 7522 # DTB misses
+system.cpu0.dtb.accesses 42483985 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 115065468 # ITB inst hits
-system.cpu0.itb.inst_misses 3349 # ITB inst misses
+system.cpu0.itb.inst_hits 115065570 # ITB inst hits
+system.cpu0.itb.inst_misses 3350 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 2151 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 2152 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 115068817 # ITB inst accesses
-system.cpu0.itb.hits 115065468 # DTB hits
-system.cpu0.itb.misses 3349 # DTB misses
-system.cpu0.itb.accesses 115068817 # DTB accesses
-system.cpu0.numCycles 5733846284 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 115068920 # ITB inst accesses
+system.cpu0.itb.hits 115065570 # DTB hits
+system.cpu0.itb.misses 3350 # DTB misses
+system.cpu0.itb.accesses 115068920 # DTB accesses
+system.cpu0.numCycles 5733826228 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 111421342 # Number of instructions committed
-system.cpu0.committedOps 134707084 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 119417138 # Number of integer alu accesses
+system.cpu0.committedInsts 111421445 # Number of instructions committed
+system.cpu0.committedOps 134708041 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 119418221 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 9755 # Number of float alu accesses
-system.cpu0.num_func_calls 12527292 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 14979198 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 119417138 # number of integer instructions
+system.cpu0.num_func_calls 12527454 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 14979151 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 119418221 # number of integer instructions
system.cpu0.num_fp_insts 9755 # number of float instructions
-system.cpu0.num_int_register_reads 220360477 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 83042635 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 220362058 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 83043778 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 7495 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 2264 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 488370374 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 49987740 # number of times the CC registers were written
-system.cpu0.num_mem_refs 43585643 # number of memory refs
-system.cpu0.num_load_insts 24597805 # Number of load instructions
-system.cpu0.num_store_insts 18987838 # Number of store instructions
-system.cpu0.num_idle_cycles 5477706580.128089 # Number of idle cycles
-system.cpu0.num_busy_cycles 256139703.871911 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.044672 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.955328 # Percentage of idle cycles
-system.cpu0.Branches 28215087 # Number of branches fetched
+system.cpu0.num_cc_register_reads 488373650 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 49988627 # number of times the CC registers were written
+system.cpu0.num_mem_refs 43585923 # number of memory refs
+system.cpu0.num_load_insts 24597873 # Number of load instructions
+system.cpu0.num_store_insts 18988050 # Number of store instructions
+system.cpu0.num_idle_cycles 5477680330.504089 # Number of idle cycles
+system.cpu0.num_busy_cycles 256145897.495911 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.044673 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.955327 # Percentage of idle cycles
+system.cpu0.Branches 28215151 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2272 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 94726294 68.43% 68.43% # Class of executed instruction
-system.cpu0.op_class::IntMult 104119 0.08% 68.51% # Class of executed instruction
+system.cpu0.op_class::IntAlu 94727035 68.43% 68.43% # Class of executed instruction
+system.cpu0.op_class::IntMult 104174 0.08% 68.51% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 68.51% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 68.51% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.51% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 7379 0.01% 68.51% # Class of executed instruction
+system.cpu0.op_class::SimdFloatMisc 7381 0.01% 68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.51% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.51% # Class of executed instruction
-system.cpu0.op_class::MemRead 24597805 17.77% 86.28% # Class of executed instruction
-system.cpu0.op_class::MemWrite 18987838 13.72% 100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead 24597873 17.77% 86.28% # Class of executed instruction
+system.cpu0.op_class::MemWrite 18988050 13.72% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 138425707 # Class of executed instruction
+system.cpu0.op_class::total 138426785 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 2071 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 1060721 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.483228 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 114004226 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1061233 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 107.426198 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 12806917500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.483228 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998991 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.998991 # Average percentage of cache occupancy
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10422.506999 # average ReadReq mshr miss latency
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+system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12340.328422 # average SoftPFReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14150.861388 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20115.998269 # average StoreCondReq mshr miss latency
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+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11565.317663 # average overall mshr miss latency
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+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
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-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6973.415804 # average overall mshr miss latency
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+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.038645 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.062665 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.012549 # mshr miss rate for overall accesses
+system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.174697 # mshr miss rate for overall accesses
system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu0.l2cache.overall_mshr_miss_rate::total 0.325471 # mshr miss rate for overall accesses
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20591.659576 # average ReadReq mshr miss latency
-system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22490.347346 # average ReadReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40174.075040 # average HardPFReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16415.278104 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16415.278104 # average UpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13535.634432 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13535.634432 # average SCUpgradeReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 128499.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 128499.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24785.949494 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24785.949494 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23216.042980 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16853.102190 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15176.020408 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34186.600976 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22064.955297 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40174.075040 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36155.723008 # average overall mshr miss latency
+system.cpu0.l2cache.overall_mshr_miss_rate::total 0.326857 # mshr miss rate for overall accesses
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 20559.989704 # average ReadReq mshr miss latency
+system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 22472.362056 # average ReadReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 40042.696701 # average HardPFReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16426.132537 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16426.132537 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13545.556143 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13545.556143 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 120749.375000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 120749.375000 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 24722.257111 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 24722.257111 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 23182.139743 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 16262.323944 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15340.375587 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 34346.150717 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 22018.582298 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 40042.696701 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 36042.262487 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 659666 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 484.509746 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 41678625 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 660178 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 63.132405 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 1015660000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 484.509746 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.946308 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.946308 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 85565275 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 85565275 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 23152761 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 23152761 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 17429713 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 17429713 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 322896 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 322896 # number of SoftPFReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 358209 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 358209 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 353793 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 353793 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 40582474 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 40582474 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 40905370 # number of overall hits
-system.cpu0.dcache.overall_hits::total 40905370 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 360920 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 360920 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 297802 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 297802 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 106369 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 106369 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21424 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 21424 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21331 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 21331 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 658722 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 658722 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 765091 # number of overall misses
-system.cpu0.dcache.overall_misses::total 765091 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 4478152013 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 4478152013 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4451575229 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 4451575229 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336099252 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 336099252 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 472564125 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 472564125 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1408000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1408000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 8929727242 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 8929727242 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 8929727242 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 8929727242 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 23513681 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 23513681 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 17727515 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 17727515 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 429265 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 429265 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379633 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 379633 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 375124 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 375124 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 41241196 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 41241196 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 41670461 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 41670461 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.015349 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.015349 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.016799 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.016799 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.247793 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.247793 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056433 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056433 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056864 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056864 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.015972 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.015972 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.018361 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.018361 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12407.602829 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 12407.602829 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14948.103871 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 14948.103871 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15687.978529 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15687.978529 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22153.866439 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22153.866439 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13556.139376 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 13556.139376 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 11671.457698 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 11671.457698 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 0 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 484431 # number of writebacks
-system.cpu0.dcache.writebacks::total 484431 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 7369 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 7369 # number of ReadReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 15106 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 15106 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 7369 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 7369 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 7369 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 7369 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 353551 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 353551 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 297802 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 297802 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 97063 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 97063 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6318 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6318 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21317 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 21317 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 651353 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 651353 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 748416 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 748416 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 3677967737 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3677967737 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 3845809771 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 3845809771 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1192380739 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1192380739 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 89588750 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 89588750 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 429129875 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 429129875 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1332000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1332000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7523777508 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 7523777508 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8716158247 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 8716158247 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5564560247 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5564560247 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4183952491 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4183952491 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9748512738 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9748512738 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.015036 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.015036 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.016799 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.016799 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226114 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226114 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016642 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016642 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056827 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056827 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.015794 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.015794 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.017960 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.017960 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10402.934052 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10402.934052 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 12913.982347 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 12913.982347 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 12284.606276 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 12284.606276 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14179.922444 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14179.922444 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20130.875592 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20130.875592 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11550.998472 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11550.998472 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11646.140979 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11646.140979 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 1734773 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 1628939 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 26255 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 26255 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 484430 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 593528 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadReq 1734345 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 1628634 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 26254 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 26254 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 483361 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 595652 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 80933 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43635 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 101479 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 80946 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43669 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 101586 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 45 # Transaction distribution
system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 279524 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 269229 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2140528 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2251817 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 10000 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21524 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 4423869 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67955576 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 81003288 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14404 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 31240 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 149004508 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 985271 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 3214597 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.271498 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.444733 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadExReq 279437 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 269063 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2141334 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2249028 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 9800 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 21070 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 4421232 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 67981368 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 80878536 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13596 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 29396 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 148902896 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 988296 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 3215199 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.272128 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.445055 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 2341839 72.85% 72.85% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 872758 27.15% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 2340254 72.79% 72.79% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 874945 27.21% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 3214597 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 1701148418 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 3215199 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 1699304627 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 115449999 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 115610498 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 1603332265 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 1603950497 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 1151834640 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 1150471329 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 6399000 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 6401000 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 13714500 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 13721750 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 4826536 # DTB read hits
-system.cpu1.dtb.read_misses 2746 # DTB read misses
-system.cpu1.dtb.write_hits 4130096 # DTB write hits
-system.cpu1.dtb.write_misses 525 # DTB write misses
+system.cpu1.dtb.read_hits 4826061 # DTB read hits
+system.cpu1.dtb.read_misses 2744 # DTB read misses
+system.cpu1.dtb.write_hits 4130169 # DTB write hits
+system.cpu1.dtb.write_misses 524 # DTB write misses
system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 2012 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 441 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 437 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 163 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 4829282 # DTB read accesses
-system.cpu1.dtb.write_accesses 4130621 # DTB write accesses
+system.cpu1.dtb.read_accesses 4828805 # DTB read accesses
+system.cpu1.dtb.write_accesses 4130693 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 8956632 # DTB hits
-system.cpu1.dtb.misses 3271 # DTB misses
-system.cpu1.dtb.accesses 8959903 # DTB accesses
+system.cpu1.dtb.hits 8956230 # DTB hits
+system.cpu1.dtb.misses 3268 # DTB misses
+system.cpu1.dtb.accesses 8959498 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 20887785 # ITB inst hits
+system.cpu1.itb.inst_hits 20883965 # ITB inst hits
system.cpu1.itb.inst_misses 1747 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 20889532 # ITB inst accesses
-system.cpu1.itb.hits 20887785 # DTB hits
+system.cpu1.itb.inst_accesses 20885712 # ITB inst accesses
+system.cpu1.itb.hits 20883965 # DTB hits
system.cpu1.itb.misses 1747 # DTB misses
-system.cpu1.itb.accesses 20889532 # DTB accesses
-system.cpu1.numCycles 5732937622 # number of cpu cycles simulated
+system.cpu1.itb.accesses 20885712 # DTB accesses
+system.cpu1.numCycles 5732918807 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 20506953 # Number of instructions committed
-system.cpu1.committedOps 24871416 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 22187475 # Number of integer alu accesses
+system.cpu1.committedInsts 20503191 # Number of instructions committed
+system.cpu1.committedOps 24868380 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 22184707 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 1792 # Number of float alu accesses
-system.cpu1.num_func_calls 1209546 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 2572136 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 22187475 # number of integer instructions
+system.cpu1.num_func_calls 1209330 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 2571856 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 22184707 # number of integer instructions
system.cpu1.num_fp_insts 1792 # number of float instructions
-system.cpu1.num_int_register_reads 39849843 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 15447126 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 39845208 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 15444901 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1276 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 90450390 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 8861668 # number of times the CC registers were written
-system.cpu1.num_mem_refs 9246104 # number of memory refs
-system.cpu1.num_load_insts 4945808 # Number of load instructions
-system.cpu1.num_store_insts 4300296 # Number of store instructions
-system.cpu1.num_idle_cycles 5671542273.082585 # Number of idle cycles
-system.cpu1.num_busy_cycles 61395348.917415 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.010709 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.989291 # Percentage of idle cycles
-system.cpu1.Branches 3892449 # Number of branches fetched
+system.cpu1.num_cc_register_reads 90439564 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 8859928 # number of times the CC registers were written
+system.cpu1.num_mem_refs 9245671 # number of memory refs
+system.cpu1.num_load_insts 4945342 # Number of load instructions
+system.cpu1.num_store_insts 4300329 # Number of store instructions
+system.cpu1.num_idle_cycles 5671530100.732908 # Number of idle cycles
+system.cpu1.num_busy_cycles 61388706.267092 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.010708 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.989292 # Percentage of idle cycles
+system.cpu1.Branches 3891928 # Number of branches fetched
system.cpu1.op_class::No_OpClass 67 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 16016240 63.31% 63.31% # Class of executed instruction
-system.cpu1.op_class::IntMult 33559 0.13% 63.44% # Class of executed instruction
+system.cpu1.op_class::IntAlu 16013514 63.30% 63.30% # Class of executed instruction
+system.cpu1.op_class::IntMult 33536 0.13% 63.44% # Class of executed instruction
system.cpu1.op_class::IntDiv 0 0.00% 63.44% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 63.44% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatCmp 0 0.00% 63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatCvt 0 0.00% 63.44% # Class of executed instruction
system.cpu1.op_class::SimdFloatDiv 0 0.00% 63.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 4035 0.02% 63.45% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 4037 0.02% 63.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 63.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 63.45% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 63.45% # Class of executed instruction
-system.cpu1.op_class::MemRead 4945808 19.55% 83.00% # Class of executed instruction
-system.cpu1.op_class::MemWrite 4300296 17.00% 100.00% # Class of executed instruction
+system.cpu1.op_class::MemRead 4945342 19.55% 83.00% # Class of executed instruction
+system.cpu1.op_class::MemWrite 4300329 17.00% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 25300005 # Class of executed instruction
+system.cpu1.op_class::total 25296825 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2718 # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements 565422 # number of replacements
-system.cpu1.icache.tags.tagsinuse 498.690526 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 20321845 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 565934 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 35.908507 # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle 115084597500 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690526 # Average occupied blocks per requestor
+system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements 218952 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 479.963069 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 8650768 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 219309 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 39.445568 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 104113347000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.963069 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937428 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.937428 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 357 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 0.697266 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 18157371 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 18157371 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 4461777 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 4461777 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 3918409 # number of WriteReq hits
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+system.cpu1.dcache.writebacks::total 135060 # number of writebacks
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+system.cpu1.dcache.overall_mshr_hits::total 315 # number of overall MSHR hits
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+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053352 # mshr miss rate for LoadLockedReq accesses
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12264.374178 # average ReadReq mshr miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14984.441869 # average LoadLockedReq mshr miss latency
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+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21140.563629 # average StoreCondReq mshr miss latency
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+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements 565004 # number of replacements
+system.cpu1.icache.tags.tagsinuse 498.690467 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 20318443 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 565516 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 35.929033 # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle 115083689500 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.690467 # Average occupied blocks per requestor
system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974005 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_percent::total 0.974005 # Average percentage of cache occupancy
system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu1.icache.tags.age_task_id_blocks_1024::2 397 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::3 112 # Occupied blocks per task id
-system.cpu1.icache.tags.age_task_id_blocks_1024::4 3 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::3 110 # Occupied blocks per task id
+system.cpu1.icache.tags.age_task_id_blocks_1024::4 5 # Occupied blocks per task id
system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu1.icache.tags.tag_accesses 42341495 # Number of tag accesses
-system.cpu1.icache.tags.data_accesses 42341495 # Number of data accesses
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-system.cpu1.icache.ReadReq_hits::total 20321845 # number of ReadReq hits
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-system.cpu1.icache.ReadReq_misses::total 565935 # number of ReadReq misses
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-system.cpu1.icache.ReadReq_miss_latency::total 4686937020 # number of ReadReq miss cycles
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-system.cpu1.icache.demand_miss_latency::total 4686937020 # number of demand (read+write) miss cycles
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-system.cpu1.icache.overall_miss_latency::total 4686937020 # number of overall miss cycles
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-system.cpu1.icache.ReadReq_accesses::total 20887780 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.overall_accesses::total 20887780 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.027094 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.027094 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.027094 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.027094 # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::total 0.027094 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8281.758541 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 8281.758541 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 8281.758541 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8281.758541 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 8281.758541 # average overall miss latency
+system.cpu1.icache.tags.tag_accesses 42333437 # Number of tag accesses
+system.cpu1.icache.tags.data_accesses 42333437 # Number of data accesses
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+system.cpu1.icache.ReadReq_hits::total 20318443 # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst 20318443 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total 20318443 # number of demand (read+write) hits
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+system.cpu1.icache.overall_hits::total 20318443 # number of overall hits
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-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24439.805130 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18537.105636 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13668.918919 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13100.177305 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28955.894864 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18067.146575 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27353.189044 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23147.093220 # average overall mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.272623 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14997.852188 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15913.654461 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27266.762706 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14641.677914 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14641.677914 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13719.554596 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13719.554596 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 186214.285714 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 186214.285714 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 24561.012513 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 24561.012513 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 18560.562323 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 13568.047337 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13021.660650 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 29355.778254 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 18080.941389 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27266.762706 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23103.708916 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 218971 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 479.931321 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 8650668 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 219324 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 39.442414 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 104113508000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 479.931321 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.937366 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.937366 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::3 58 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 18158178 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 18158178 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 4462217 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 4462217 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 3918401 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 3918401 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 64226 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 64226 # number of SoftPFReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87223 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 87223 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79606 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 79606 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 8380618 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 8380618 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 8444844 # number of overall hits
-system.cpu1.dcache.overall_hits::total 8444844 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 155213 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 155213 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 103694 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 103694 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 34142 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 34142 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17915 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 17915 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23305 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 23305 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 258907 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 258907 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 293049 # number of overall misses
-system.cpu1.dcache.overall_misses::total 293049 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2221366762 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 2221366762 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2262833509 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 2262833509 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 325848251 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 325848251 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 539203701 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 539203701 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1640500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1640500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 4484200271 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 4484200271 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 4484200271 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 4484200271 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 4617430 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 4617430 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 4022095 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 4022095 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 98368 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 98368 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 105138 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 105138 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102911 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 102911 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 8639525 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 8639525 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 8737893 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 8737893 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.033615 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.033615 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.025781 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.025781 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.347084 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.347084 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.170395 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.170395 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.226458 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.226458 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.029968 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.033538 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.033538 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14311.731376 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14311.731376 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21822.222202 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 21822.222202 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18188.571086 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18188.571086 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23136.824759 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23136.824759 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 17319.733615 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 17319.733615 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15301.878768 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 15301.878768 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 134894 # number of writebacks
-system.cpu1.dcache.writebacks::total 134894 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 307 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 307 # number of ReadReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12314 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12314 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 307 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 307 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 307 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 307 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 154906 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 154906 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103694 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 103694 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32987 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 32987 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5601 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5601 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23260 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 23260 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 258600 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 258600 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 291587 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 291587 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1902428238 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1902428238 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2049146491 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2049146491 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 494497248 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 494497248 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 84788249 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 84788249 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 491455299 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 491455299 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1568500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1568500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3951574729 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 3951574729 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4446071977 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 4446071977 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 960995749 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 960995749 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 833535999 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 833535999 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1794531748 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1794531748 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033548 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033548 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025781 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025781 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.335343 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.335343 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053273 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053273 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226021 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226021 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.029932 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.029932 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033370 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.033370 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12281.178508 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12281.178508 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 19761.475987 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 19761.475987 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 14990.670507 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 14990.670507 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15138.055526 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15138.055526 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21128.774678 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21128.774678 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15280.644737 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 15280.644737 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15247.840188 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 15247.840188 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 1203948 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 816897 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 4924 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 4924 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 134894 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 171563 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadReq 1205511 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 816520 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 4921 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 4921 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 135060 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 171236 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 86145 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42520 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 89650 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 86319 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42477 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 89729 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 44 # Transaction distribution
system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 90932 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 78151 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1132224 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880229 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5367 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9390 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 2027210 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36220548 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28766783 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8168 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13868 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 65009367 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 817024 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 1760474 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.414632 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.492658 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadExReq 90979 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 78176 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1131388 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 880635 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 5306 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 9255 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 2026584 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 36193796 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 28781627 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7924 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 13336 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 64996683 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 818999 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 1762052 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.415245 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.492764 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 1030526 58.54% 58.54% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 729948 41.46% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 1030369 58.48% 58.48% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 731683 41.52% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 1760474 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 658123967 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 1762052 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 658210715 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 89509999 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 89516500 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 849202770 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 848574281 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 438590477 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 438678337 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 3325250 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 3325000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 5923750 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 5921000 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 36427 # number of replacements
-system.iocache.tags.tagsinuse 14.452095 # Cycle average of tags in use
-system.iocache.tags.total_refs 16 # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs 36443 # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs 0.000439 # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle 277168075000 # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::realview.ide 14.452095 # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::realview.ide 0.903256 # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total 0.903256 # Average percentage of cache occupancy
+system.iobus.trans_dist::ReadReq 31019 # Transaction distribution
+system.iobus.trans_dist::ReadResp 31019 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59407 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59440 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 844 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 107964 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72954 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 180918 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 446 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 162847 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321256 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2484103 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 503000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326671825 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 84748000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36845580 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iocache.tags.replacements 36443 # number of replacements
+system.iocache.tags.tagsinuse 14.446794 # Cycle average of tags in use
+system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs 36459 # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle 277163106000 # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::realview.ide 14.446794 # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::realview.ide 0.902925 # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total 0.902925 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
-system.iocache.tags.tag_accesses 328485 # Number of tag accesses
-system.iocache.tags.data_accesses 328485 # Number of data accesses
+system.iocache.tags.tag_accesses 328557 # Number of tag accesses
+system.iocache.tags.data_accesses 328557 # Number of data accesses
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
system.iocache.ReadReq_misses::realview.ide 253 # number of ReadReq misses
system.iocache.ReadReq_misses::total 253 # number of ReadReq misses
-system.iocache.WriteInvalidateReq_misses::realview.ide 26 # number of WriteInvalidateReq misses
-system.iocache.WriteInvalidateReq_misses::total 26 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses
+system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses
system.iocache.demand_misses::realview.ide 253 # number of demand (read+write) misses
system.iocache.demand_misses::total 253 # number of demand (read+write) misses
system.iocache.overall_misses::realview.ide 253 # number of overall misses
system.iocache.overall_misses::total 253 # number of overall misses
-system.iocache.ReadReq_miss_latency::realview.ide 31613377 # number of ReadReq miss cycles
-system.iocache.ReadReq_miss_latency::total 31613377 # number of ReadReq miss cycles
-system.iocache.demand_miss_latency::realview.ide 31613377 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 31613377 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::realview.ide 31613377 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 31613377 # number of overall miss cycles
+system.iocache.ReadReq_miss_latency::realview.ide 31609377 # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total 31609377 # number of ReadReq miss cycles
+system.iocache.demand_miss_latency::realview.ide 31609377 # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total 31609377 # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::realview.ide 31609377 # number of overall miss cycles
+system.iocache.overall_miss_latency::total 31609377 # number of overall miss cycles
system.iocache.ReadReq_accesses::realview.ide 253 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 253 # number of ReadReq accesses(hits+misses)
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+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 9143000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1526922000 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 10349710003 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.191902 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.118916 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::total 0.404984 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.470336 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.807359 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.545171 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783333 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.904196 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850584 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.601360 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.683951 # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::total 0.637776 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.414055 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.051948 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.006410 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.234447 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.282119 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.472148 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.053571 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.022222 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.160474 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.349538 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.308866 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.414055 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 69149.263196 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 72675.713571 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 87572.641367 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10086.684475 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10058.382009 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10077.377638 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10042.431131 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10040.054911 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10041.025618 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 66903.547246 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60003.434000 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 63640.917064 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 62343.750000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 74601.631882 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68094.550144 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 87883.803067 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 62500 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 77984.412214 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62555.022005 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 94675.822831 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 86136.192391 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 228475 # Transaction distribution
+system.membus.trans_dist::ReadResp 228474 # Transaction distribution
+system.membus.trans_dist::WriteReq 31175 # Transaction distribution
+system.membus.trans_dist::WriteResp 31175 # Transaction distribution
+system.membus.trans_dist::Writeback 99922 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 85905 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 41202 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 15112 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 5 # Transaction distribution
+system.membus.trans_dist::ReadExReq 28459 # Transaction distribution
+system.membus.trans_dist::ReadExResp 11563 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107964 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 34 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14554 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 678409 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 800961 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72716 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72716 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 873677 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162847 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 68 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29108 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18962472 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 19154495 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 21473791 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 129134 # Total snoops (count)
+system.membus.snoop_fanout::samples 475892 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 475892 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 475892 # Request fanout histogram
+system.membus.reqLayer0.occupancy 88166996 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 18500 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 12082997 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1515063497 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1971064197 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38584420 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 633379 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 633359 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 240423 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 96357 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 41586 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 137943 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 74 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 74 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 39964 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 39964 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1256968 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 399943 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 1656911 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 37604672 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8289023 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 45893695 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 305031 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 1043713 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.034956 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.183668 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 1007229 96.50% 96.50% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 36484 3.50% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 1043713 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1520313197 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 1071000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 2134327544 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 850356790 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
sim_ticks 2902619131000 # Number of ticks simulated
final_tick 2902619131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 756630 # Simulator instruction rate (inst/s)
-host_op_rate 912268 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 19520630002 # Simulator tick rate (ticks/s)
-host_mem_usage 553652 # Number of bytes of host memory used
-host_seconds 148.70 # Real time elapsed on the host
-sim_insts 112506995 # Number of instructions simulated
-sim_ops 135649572 # Number of ops (including micro ops) simulated
+host_inst_rate 783857 # Simulator instruction rate (inst/s)
+host_op_rate 945096 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 20223090080 # Simulator tick rate (ticks/s)
+host_mem_usage 560080 # Number of bytes of host memory used
+host_seconds 143.53 # Real time elapsed on the host
+sim_insts 112507011 # Number of instructions simulated
+sim_ops 135649580 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 448 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 1190564 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9003364 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 10195464 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 1190564 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1190564 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 5259520 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::total 7595380 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 7 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 27056 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 141197 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 168277 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 82180 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::total 122785 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 154 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 44 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 410169 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3101807 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 331 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3512505 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 410169 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 410169 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1811991 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 6037 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 798705 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2616733 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1811991 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 154 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 44 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 410169 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3107844 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 799036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 6129238 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 168277 # Number of read requests accepted
system.physmem.writeReqs 122785 # Number of write requests accepted
system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 58557 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 313.668528 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 183.635625 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 334.571119 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 21469 36.66% 36.66% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 14643 25.01% 61.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 5518 9.42% 71.09% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 3471 5.93% 77.02% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 2279 3.89% 80.91% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::samples 58554 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 313.684599 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 183.640199 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 334.584074 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 21469 36.67% 36.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 14640 25.00% 61.67% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 5516 9.42% 71.09% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 3473 5.93% 77.02% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 2278 3.89% 80.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1576 2.69% 83.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 998 1.70% 85.31% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.13% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 7539 12.87% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 58557 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 999 1.71% 85.31% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 1064 1.82% 87.12% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 7539 12.88% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 58554 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 5863 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 28.669452 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 558.899894 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 5863 # Writes before turning the bus around for reads
-system.physmem.totQLat 1492072500 # Total ticks spent queuing
-system.physmem.totMemAccLat 4643853750 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totQLat 1491102500 # Total ticks spent queuing
+system.physmem.totMemAccLat 4642883750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 840475000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 8876.36 # Average queueing delay per DRAM burst
+system.physmem.avgQLat 8870.59 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 27626.36 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 27620.59 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.71 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 2.62 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.51 # Average system read bandwidth in MiByte/s
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
system.physmem.avgWrQLen 27.72 # Average write queue length when enqueuing
-system.physmem.readRowHits 138435 # Number of row buffer hits during reads
-system.physmem.writeRowHits 90000 # Number of row buffer hits during writes
+system.physmem.readRowHits 138436 # Number of row buffer hits during reads
+system.physmem.writeRowHits 90002 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.36 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 75.68 # Row buffer hit rate for writes
system.physmem.avgGap 9972510.17 # Average gap between requests
system.physmem.pageHitRate 79.59 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 2755208852500 # Time in different power states
+system.physmem.memoryStateTime::IDLE 2755210874500 # Time in different power states
system.physmem.memoryStateTime::REF 96924620000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 50485568000 # Time in different power states
+system.physmem.memoryStateTime::ACT 50483546000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 226739520 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 215951400 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 123717000 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 117830625 # Energy for precharge commands per rank (pJ)
+system.physmem.actEnergy::0 226731960 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 215936280 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 123712875 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 117822375 # Energy for precharge commands per rank (pJ)
system.physmem.readEnergy::0 698794200 # Energy for read commands per rank (pJ)
system.physmem.readEnergy::1 612339000 # Energy for read commands per rank (pJ)
system.physmem.writeEnergy::0 389791440 # Energy for write commands per rank (pJ)
system.physmem.writeEnergy::1 380667600 # Energy for write commands per rank (pJ)
system.physmem.refreshEnergy::0 189584556720 # Energy for refresh commands per rank (pJ)
system.physmem.refreshEnergy::1 189584556720 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 86731424865 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 85566193245 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 1665487617750 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 1666509750750 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 1943242641495 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 1942987289340 # Total energy per rank (pJ)
-system.physmem.averagePower::0 669.480439 # Core power per rank (mW)
-system.physmem.averagePower::1 669.392466 # Core power per rank (mW)
+system.physmem.actBackEnergy::0 86730297120 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 85558991580 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 1665488607000 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 1666516068000 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 1943242491315 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 1942986381555 # Total energy per rank (pJ)
+system.physmem.averagePower::0 669.480387 # Core power per rank (mW)
+system.physmem.averagePower::1 669.392153 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 7 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 70649 # Transaction distribution
-system.membus.trans_dist::ReadResp 70649 # Transaction distribution
-system.membus.trans_dist::WriteReq 27618 # Transaction distribution
-system.membus.trans_dist::WriteResp 27618 # Transaction distribution
-system.membus.trans_dist::Writeback 82180 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution
-system.membus.trans_dist::ReadExReq 128451 # Transaction distribution
-system.membus.trans_dist::ReadExResp 128451 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 219 # Total snoops (count)
-system.membus.snoop_fanout::samples 281834 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 281834 # Request fanout histogram
-system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 1264018000 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 1594857995 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
-system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
-system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
-system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
-system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
-system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 24532668 # DTB read hits
+system.cpu.dtb.read_hits 24532671 # DTB read hits
system.cpu.dtb.read_misses 8148 # DTB read misses
-system.cpu.dtb.write_hits 19614514 # DTB write hits
+system.cpu.dtb.write_hits 19614515 # DTB write hits
system.cpu.dtb.write_misses 1410 # DTB write misses
system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA
system.cpu.dtb.prefetch_faults 1630 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 24540816 # DTB read accesses
-system.cpu.dtb.write_accesses 19615924 # DTB write accesses
+system.cpu.dtb.read_accesses 24540819 # DTB read accesses
+system.cpu.dtb.write_accesses 19615925 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 44147182 # DTB hits
+system.cpu.dtb.hits 44147186 # DTB hits
system.cpu.dtb.misses 9558 # DTB misses
-system.cpu.dtb.accesses 44156740 # DTB accesses
+system.cpu.dtb.accesses 44156744 # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu.itb.inst_hits 115605897 # ITB inst hits
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system.cpu.itb.inst_misses 4762 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 115610659 # ITB inst accesses
-system.cpu.itb.hits 115605897 # DTB hits
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system.cpu.itb.misses 4762 # DTB misses
-system.cpu.itb.accesses 115610659 # DTB accesses
+system.cpu.itb.accesses 115610680 # DTB accesses
system.cpu.numCycles 5805238262 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 112506995 # Number of instructions committed
-system.cpu.committedOps 135649572 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 119948923 # Number of integer alu accesses
+system.cpu.committedInsts 112507011 # Number of instructions committed
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system.cpu.num_fp_alu_accesses 11161 # Number of float alu accesses
system.cpu.num_func_calls 9898964 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 15236398 # number of instructions that are conditional controls
-system.cpu.num_int_insts 119948923 # number of integer instructions
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+system.cpu.num_int_insts 119948946 # number of integer instructions
system.cpu.num_fp_insts 11161 # number of float instructions
-system.cpu.num_int_register_reads 218165441 # number of times the integer registers were read
-system.cpu.num_int_register_writes 82686635 # number of times the integer registers were written
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+system.cpu.num_int_register_writes 82686622 # number of times the integer registers were written
system.cpu.num_fp_register_reads 8449 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2716 # number of times the floating registers were written
-system.cpu.num_cc_register_reads 489970609 # number of times the CC registers were read
-system.cpu.num_cc_register_writes 51914327 # number of times the CC registers were written
-system.cpu.num_mem_refs 45428231 # number of memory refs
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-system.cpu.num_busy_cycles 418782139.975856 # Number of busy cycles
-system.cpu.not_idle_fraction 0.072139 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.927861 # Percentage of idle cycles
-system.cpu.Branches 25929456 # Number of branches fetched
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+system.cpu.num_cc_register_writes 51914345 # number of times the CC registers were written
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system.cpu.op_class::No_OpClass 2337 0.00% 0.00% # Class of executed instruction
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system.cpu.op_class::IntDiv 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatAdd 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::FloatCmp 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMult 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatMultAcc 0 0.00% 67.26% # Class of executed instruction
system.cpu.op_class::SimdFloatSqrt 0 0.00% 67.26% # Class of executed instruction
-system.cpu.op_class::MemRead 24855392 17.91% 85.18% # Class of executed instruction
-system.cpu.op_class::MemWrite 20572839 14.82% 100.00% # Class of executed instruction
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system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu.op_class::total 138771625 # Class of executed instruction
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 3032 # number of quiesce instructions executed
-system.cpu.icache.tags.replacements 1699818 # number of replacements
-system.cpu.icache.tags.tagsinuse 510.781939 # Cycle average of tags in use
-system.cpu.icache.tags.total_refs 113905561 # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs 1700330 # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs 66.990267 # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle 25181626250 # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst 510.781939 # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst 0.997621 # Average percentage of cache occupancy
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-system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
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-system.cpu.icache.tags.age_task_id_blocks_1024::1 195 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::2 264 # Occupied blocks per task id
-system.cpu.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
-system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.icache.tags.tag_accesses 117306233 # Number of tag accesses
-system.cpu.icache.tags.data_accesses 117306233 # Number of data accesses
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-system.cpu.icache.ReadReq_misses::cpu.inst 1700336 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 1700336 # number of demand (read+write) misses
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-system.cpu.icache.overall_misses::total 1700336 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 23243215000 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 23243215000 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_accesses::total 115605897 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.demand_accesses::total 115605897 # number of demand (read+write) accesses
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-system.cpu.icache.overall_accesses::total 115605897 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014708 # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13669.777620 # average ReadReq miss latency
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-system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1700336 # number of ReadReq MSHR misses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11665.924852 # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11665.924852 # average ReadReq mshr miss latency
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-system.cpu.icache.demand_avg_mshr_miss_latency::total 11665.924852 # average overall mshr miss latency
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system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements 822747 # number of replacements
-system.cpu.dcache.tags.tagsinuse 511.850534 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 43252597 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 823259 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 52.538262 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 876905250 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 511.850534 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.999708 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.999708 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 368 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::2 82 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 177194873 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 177194873 # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data 23122385 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 23122385 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 18831357 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 18831357 # number of WriteReq hits
-system.cpu.dcache.SoftPFReq_hits::cpu.data 392121 # number of SoftPFReq hits
-system.cpu.dcache.SoftPFReq_hits::total 392121 # number of SoftPFReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.data 443546 # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_hits::total 443546 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.data 460444 # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_hits::total 460444 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data 41953742 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 41953742 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 42345863 # number of overall hits
-system.cpu.dcache.overall_hits::total 42345863 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 402167 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 402167 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 299026 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 299026 # number of WriteReq misses
-system.cpu.dcache.SoftPFReq_misses::cpu.data 119155 # number of SoftPFReq misses
-system.cpu.dcache.SoftPFReq_misses::total 119155 # number of SoftPFReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.data 22691 # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_misses::total 22691 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.data 701193 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 701193 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 820348 # number of overall misses
-system.cpu.dcache.overall_misses::total 820348 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 5900820250 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 5900820250 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 11658466753 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 11658466753 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 279152000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::total 279152000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 53002 # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::total 53002 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 17559287003 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 17559287003 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 17559287003 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 17559287003 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 23524552 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 23524552 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 19130383 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 19130383 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::cpu.data 511276 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.SoftPFReq_accesses::total 511276 # number of SoftPFReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.data 466237 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::total 466237 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.data 460446 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::total 460446 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 42654935 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 42654935 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 43166211 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total 43166211 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.017096 # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_miss_rate::total 0.017096 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.015631 # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_miss_rate::total 0.015631 # miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.233054 # miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_miss_rate::total 0.233054 # miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.048668 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::total 0.048668 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.data 0.016439 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total 0.016439 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.data 0.019004 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total 0.019004 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14672.562020 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 14672.562020 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38988.137329 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 38988.137329 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 12302.322507 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 12302.322507 # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 26501 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total 26501 # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.data 25042.016967 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 25042.016967 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.data 21404.680700 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 21404.680700 # average overall miss latency
-system.cpu.dcache.blocked_cycles::no_mshrs 58 # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked
-system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_mshrs 1.757576 # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu.dcache.fast_writes 0 # number of fast writes performed
-system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks::writebacks 686231 # number of writebacks
-system.cpu.dcache.writebacks::total 686231 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.data 627 # number of ReadReq MSHR hits
-system.cpu.dcache.ReadReq_mshr_hits::total 627 # number of ReadReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 14222 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits::total 14222 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.data 627 # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::total 627 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.data 627 # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::total 627 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.data 401540 # number of ReadReq MSHR misses
-system.cpu.dcache.ReadReq_mshr_misses::total 401540 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.data 299026 # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::total 299026 # number of WriteReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 117004 # number of SoftPFReq MSHR misses
-system.cpu.dcache.SoftPFReq_mshr_misses::total 117004 # number of SoftPFReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8469 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::total 8469 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.data 700566 # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::total 700566 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.data 817570 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::total 817570 # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5083703250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_latency::total 5083703250 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11002916247 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::total 11002916247 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1411190000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1411190000 # number of SoftPFReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 99471250 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99471250 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 48998 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 48998 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16086619497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::total 16086619497 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17497809497 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::total 17497809497 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5791402750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5791402750 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4429678000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4429678000 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10221080750 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total 10221080750 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017069 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017069 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015631 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015631 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228847 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228847 # mshr miss rate for SoftPFReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.018165 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.018165 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016424 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total 0.016424 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.018940 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total 0.018940 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12660.515142 # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12660.515142 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36795.851354 # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36795.851354 # average WriteReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12061.040648 # average SoftPFReq mshr miss latency
-system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12061.040648 # average SoftPFReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11745.335931 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11745.335931 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 24499 # average StoreCondReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 24499 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22962.318321 # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total 22962.318321 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21402.215709 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total 21402.215709 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu.toL2Bus.trans_dist::ReadReq 2294826 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadResp 2294811 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadReq 2294825 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::ReadResp 2294810 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 27618 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 27618 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::Writeback 686231 # Transaction distribution
+system.cpu.toL2Bus.trans_dist::Writeback 686230 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36225 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2742 # Transaction distribution
system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 296284 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 296284 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3418692 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456076 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2456073 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 12917 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 24956 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 5912641 # Packet count per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_count::total 5912638 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 108856056 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96807049 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 96806921 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14808 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 28416 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 205706329 # Cumulative packet size per connected master and slave (bytes)
+system.cpu.toL2Bus.pkt_size::total 205706201 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops 52963 # Total snoops (count)
-system.cpu.toL2Bus.snoop_fanout::samples 3276134 # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::samples 3276132 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean 5.011129 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev 0.104904 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::5 3239675 98.89% 98.89% # Request fanout histogram
+system.cpu.toL2Bus.snoop_fanout::5 3239673 98.89% 98.89% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::6 36459 1.11% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 3276134 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 2353774500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.snoop_fanout::total 3276132 # Request fanout histogram
+system.cpu.toL2Bus.reqLayer0.occupancy 2353772500 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.snoopLayer0.occupancy 328500 # Layer occupancy (ticks)
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 2564911500 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer0.occupancy 2564911000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 1311853255 # Layer occupancy (ticks)
+system.cpu.toL2Bus.respLayer1.occupancy 1311851755 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 9215000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 17852250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.trans_dist::ReadReq 30195 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30195 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59038 # Transaction distribution
+system.iobus.trans_dist::WriteResp 59038 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks)
+system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks)
+system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks)
+system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks)
+system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks)
+system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks)
+system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks)
+system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks)
+system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
+system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
+system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks)
+system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks)
+system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks)
+system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks)
+system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer27.occupancy 326584349 # Layer occupancy (ticks)
+system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
+system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
+system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks)
+system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.iobus.respLayer3.occupancy 36805009 # Layer occupancy (ticks)
+system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.tags.replacements 36424 # number of replacements
system.iocache.tags.tagsinuse 1.133398 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.overall_avg_mshr_miss_latency::realview.ide 67817.850427 # average overall mshr miss latency
system.iocache.overall_avg_mshr_miss_latency::total 67817.850427 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 70649 # Transaction distribution
+system.membus.trans_dist::ReadResp 70649 # Transaction distribution
+system.membus.trans_dist::WriteReq 27618 # Transaction distribution
+system.membus.trans_dist::WriteResp 27618 # Transaction distribution
+system.membus.trans_dist::Writeback 82180 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4503 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4505 # Transaction distribution
+system.membus.trans_dist::ReadExReq 128451 # Transaction distribution
+system.membus.trans_dist::ReadExResp 128451 # Transaction distribution
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2122 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 436476 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.cpu.l2cache.mem_side::total 544158 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72697 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72697 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 616855 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4244 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 15471548 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.cpu.l2cache.mem_side::total 15635009 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 17954305 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 219 # Total snoops (count)
+system.membus.snoop_fanout::samples 281834 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 281834 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 281834 # Request fanout histogram
+system.membus.reqLayer0.occupancy 86774000 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 1752500 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 1264017500 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 1594856995 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
+system.membus.respLayer3.occupancy 38339991 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
sim_seconds 2.783854 # Number of seconds simulated
-sim_ticks 2783854177000 # Number of ticks simulated
-final_tick 2783854177000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_ticks 2783854461500 # Number of ticks simulated
+final_tick 2783854461500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1241693 # Simulator instruction rate (inst/s)
-host_op_rate 1511561 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 24211403286 # Simulator tick rate (ticks/s)
-host_mem_usage 555676 # Number of bytes of host memory used
-host_seconds 114.98 # Real time elapsed on the host
-sim_insts 142771179 # Number of instructions simulated
-sim_ops 173800939 # Number of ops (including micro ops) simulated
+host_inst_rate 1108552 # Simulator instruction rate (inst/s)
+host_op_rate 1349484 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 21615280295 # Simulator tick rate (ticks/s)
+host_mem_usage 562164 # Number of bytes of host memory used
+host_seconds 128.79 # Real time elapsed on the host
+sim_insts 142771592 # Number of instructions simulated
+sim_ops 173801445 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 726948 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 4668448 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 4668256 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 484032 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 5677124 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 5677316 # Number of bytes read from this memory
+system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
system.physmem.bytes_read::total 11558024 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 726948 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 484032 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 1210980 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 6521152 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
+system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
system.physmem.bytes_written::total 8857012 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 19812 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 73463 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 73460 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 7563 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 88706 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 88709 # Number of read requests responded to by this memory
+system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
system.physmem.num_reads::total 189567 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 101893 # Number of write requests responded to by this memory
-system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
+system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
system.physmem.num_writes::total 142498 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 115 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 261130 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 1676973 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 1676904 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 46 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 173871 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 2039304 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 4151807 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 2039372 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::realview.ide 345 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 4151806 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 261130 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 173871 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 435001 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 2342491 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 2342490 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 6292 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 3181565 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 2342491 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_write::realview.ide 832779 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 3181564 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 2342490 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 115 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 261130 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 1683265 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 1683196 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 46 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 173871 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 2039307 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 7333371 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 74229 # Transaction distribution
-system.membus.trans_dist::ReadResp 74229 # Transaction distribution
-system.membus.trans_dist::WriteReq 27560 # Transaction distribution
-system.membus.trans_dist::WriteResp 27560 # Transaction distribution
-system.membus.trans_dist::Writeback 101893 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
-system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
-system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498777 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 606179 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 679107 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095740 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 18258755 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 20592451 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoop_fanout::samples 322846 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 322846 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 322846 # Request fanout histogram
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 110021 # number of replacements
-system.l2c.tags.tagsinuse 65155.315046 # Cycle average of tags in use
-system.l2c.tags.total_refs 2731069 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 175302 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 15.579223 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 48893.450806 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.924325 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000096 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 5044.246169 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 4729.238625 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.978702 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 4020.301933 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 2464.174390 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.746055 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000045 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.076969 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.072162 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.061345 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.037600 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total 0.994191 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 65277 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 180 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 3716 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 10700 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 50641 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.996048 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 26229699 # Number of tag accesses
-system.l2c.tags.data_accesses 26229699 # Number of data accesses
-system.l2c.ReadReq_hits::cpu0.dtb.walker 4718 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.itb.walker 2285 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.inst 833258 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data 246713 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.dtb.walker 4981 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.itb.walker 2429 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst 847891 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 258771 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 2201046 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 682259 # number of Writeback hits
-system.l2c.Writeback_hits::total 682259 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::cpu0.data 72299 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::cpu1.data 78743 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 151042 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 4718 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 2285 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 833258 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 319012 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.dtb.walker 4981 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.itb.walker 2429 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 847891 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 337514 # number of demand (read+write) hits
-system.l2c.demand_hits::total 2352088 # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.dtb.walker 4718 # number of overall hits
-system.l2c.overall_hits::cpu0.itb.walker 2285 # number of overall hits
-system.l2c.overall_hits::cpu0.inst 833258 # number of overall hits
-system.l2c.overall_hits::cpu0.data 319012 # number of overall hits
-system.l2c.overall_hits::cpu1.dtb.walker 4981 # number of overall hits
-system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits
-system.l2c.overall_hits::cpu1.inst 847891 # number of overall hits
-system.l2c.overall_hits::cpu1.data 337514 # number of overall hits
-system.l2c.overall_hits::total 2352088 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 10795 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 9750 # number of ReadReq misses
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-system.l2c.ReadReq_misses::cpu1.inst 7563 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 5779 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 33895 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data 63973 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data 83891 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 10795 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data 73723 # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.inst 7563 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 89670 # number of demand (read+write) misses
-system.l2c.demand_misses::total 181759 # number of demand (read+write) misses
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-system.l2c.overall_misses::cpu0.inst 10795 # number of overall misses
-system.l2c.overall_misses::cpu0.data 73723 # number of overall misses
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-system.l2c.overall_misses::cpu1.inst 7563 # number of overall misses
-system.l2c.overall_misses::cpu1.data 89670 # number of overall misses
-system.l2c.overall_misses::total 181759 # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.dtb.walker 4723 # number of ReadReq accesses(hits+misses)
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-system.l2c.ReadReq_accesses::cpu0.inst 844053 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data 256463 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.dtb.walker 4983 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst 855454 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data 264550 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 2234941 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks 682259 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 682259 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data 1261 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data 136272 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data 162634 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 298906 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.dtb.walker 4723 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.itb.walker 2286 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.inst 844053 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data 392735 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.dtb.walker 4983 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst 855454 # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data 427184 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 2533847 # number of demand (read+write) accesses
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-system.l2c.overall_accesses::cpu0.inst 844053 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data 392735 # number of overall (read+write) accesses
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-system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst 855454 # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data 427184 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 2533847 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst 0.012789 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data 0.038017 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst 0.008841 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data 0.021845 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.015166 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990484 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989298 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data 0.469451 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data 0.515827 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total 0.494684 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.inst 0.012789 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data 0.187717 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst 0.008841 # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data 0.209910 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.071732 # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001059 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.inst 0.012789 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data 0.187717 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst 0.008841 # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data 0.209910 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.071732 # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks::writebacks 101893 # number of writebacks
-system.l2c.writebacks::total 101893 # number of writebacks
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.physmem.bw_total::cpu1.data 2039375 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.ide 833124 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 7333370 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 2291797 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 2291797 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 682259 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 298906 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 298906 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417092 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444877 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20768 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41564 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 5924301 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96322187 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41536 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83128 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 205252475 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 36632 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 3272090 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 5.011144 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.104975 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::5 3235626 98.89% 98.89% # Request fanout histogram
-system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 3272090 # Request fanout histogram
-system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
-system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
-system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
-system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54158 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 105446 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72928 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 72928 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 178374 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67875 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 159103 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 2321152 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 2480255 # Cumulative packet size per connected master and slave (bytes)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 15997157 # DTB read hits
-system.cpu0.dtb.read_misses 4809 # DTB read misses
-system.cpu0.dtb.write_hits 11281332 # DTB write hits
-system.cpu0.dtb.write_misses 894 # DTB write misses
+system.cpu0.dtb.read_hits 15997075 # DTB read hits
+system.cpu0.dtb.read_misses 4808 # DTB read misses
+system.cpu0.dtb.write_hits 11281657 # DTB write hits
+system.cpu0.dtb.write_misses 898 # DTB write misses
system.cpu0.dtb.flush_tlb 2813 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 3232 # Number of entries that have been flushed from TLB
+system.cpu0.dtb.flush_entries 3234 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 770 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 202 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 16001966 # DTB read accesses
-system.cpu0.dtb.write_accesses 11282226 # DTB write accesses
+system.cpu0.dtb.read_accesses 16001883 # DTB read accesses
+system.cpu0.dtb.write_accesses 11282555 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 27278489 # DTB hits
-system.cpu0.dtb.misses 5703 # DTB misses
-system.cpu0.dtb.accesses 27284192 # DTB accesses
+system.cpu0.dtb.hits 27278732 # DTB hits
+system.cpu0.dtb.misses 5706 # DTB misses
+system.cpu0.dtb.accesses 27284438 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 74798311 # ITB inst hits
-system.cpu0.itb.inst_misses 2590 # ITB inst misses
+system.cpu0.itb.inst_hits 74797961 # ITB inst hits
+system.cpu0.itb.inst_misses 2591 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.flush_tlb_mva 403 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1907 # Number of entries that have been flushed from TLB
+system.cpu0.itb.flush_entries 1908 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 74800901 # ITB inst accesses
-system.cpu0.itb.hits 74798311 # DTB hits
-system.cpu0.itb.misses 2590 # DTB misses
-system.cpu0.itb.accesses 74800901 # DTB accesses
-system.cpu0.numCycles 5536444793 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 74800552 # ITB inst accesses
+system.cpu0.itb.hits 74797961 # DTB hits
+system.cpu0.itb.misses 2591 # DTB misses
+system.cpu0.itb.accesses 74800552 # DTB accesses
+system.cpu0.numCycles 5536444794 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 72639683 # Number of instructions committed
-system.cpu0.committedOps 87981695 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 77491900 # Number of integer alu accesses
+system.cpu0.committedInsts 72639396 # Number of instructions committed
+system.cpu0.committedOps 87981758 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 77492054 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 5289 # Number of float alu accesses
-system.cpu0.num_func_calls 8694354 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 9459791 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 77491900 # number of integer instructions
+system.cpu0.num_func_calls 8694368 # number of times a function call or return occured
+system.cpu0.num_conditional_control_insts 9459714 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 77492054 # number of integer instructions
system.cpu0.num_fp_insts 5289 # number of float instructions
-system.cpu0.num_int_register_reads 144070444 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 54447556 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 144071276 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 54447497 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 4067 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1224 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 268879109 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 31834194 # number of times the CC registers were written
-system.cpu0.num_mem_refs 27909453 # number of memory refs
-system.cpu0.num_load_insts 16164742 # Number of load instructions
-system.cpu0.num_store_insts 11744711 # Number of store instructions
-system.cpu0.num_idle_cycles 5353616970.490369 # Number of idle cycles
-system.cpu0.num_busy_cycles 182827822.509631 # Number of busy cycles
+system.cpu0.num_cc_register_reads 268879516 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 31833951 # number of times the CC registers were written
+system.cpu0.num_mem_refs 27909687 # number of memory refs
+system.cpu0.num_load_insts 16164649 # Number of load instructions
+system.cpu0.num_store_insts 11745038 # Number of store instructions
+system.cpu0.num_idle_cycles 5353616424.336780 # Number of idle cycles
+system.cpu0.num_busy_cycles 182828369.663220 # Number of busy cycles
system.cpu0.not_idle_fraction 0.033023 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.966977 # Percentage of idle cycles
-system.cpu0.Branches 18600859 # Number of branches fetched
+system.cpu0.Branches 18600789 # Number of branches fetched
system.cpu0.op_class::No_OpClass 2188 0.00% 0.00% # Class of executed instruction
-system.cpu0.op_class::IntAlu 61776837 68.83% 68.83% # Class of executed instruction
-system.cpu0.op_class::IntMult 59680 0.07% 68.90% # Class of executed instruction
+system.cpu0.op_class::IntAlu 61776684 68.83% 68.83% # Class of executed instruction
+system.cpu0.op_class::IntMult 59679 0.07% 68.90% # Class of executed instruction
system.cpu0.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction
system.cpu0.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction
system.cpu0.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.90% # Class of executed instruction
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.90% # Class of executed instruction
-system.cpu0.op_class::MemRead 16164742 18.01% 86.91% # Class of executed instruction
-system.cpu0.op_class::MemWrite 11744711 13.09% 100.00% # Class of executed instruction
+system.cpu0.op_class::MemRead 16164649 18.01% 86.91% # Class of executed instruction
+system.cpu0.op_class::MemWrite 11745038 13.09% 100.00% # Class of executed instruction
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu0.op_class::total 89752572 # Class of executed instruction
+system.cpu0.op_class::total 89752652 # Class of executed instruction
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 3080 # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements 1699006 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.663679 # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs 145341254 # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs 1699518 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 85.519102 # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle 7831491500 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 455.121642 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_blocks::cpu1.inst 56.542037 # Average occupied blocks per requestor
-system.cpu0.icache.tags.occ_percent::cpu0.inst 0.888909 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::cpu1.inst 0.110434 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total 0.999343 # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 197 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 233 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id
-system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.icache.tags.tag_accesses 148740302 # Number of tag accesses
-system.cpu0.icache.tags.data_accesses 148740302 # Number of data accesses
-system.cpu0.icache.ReadReq_hits::cpu0.inst 73956125 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::cpu1.inst 71385129 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 145341254 # number of ReadReq hits
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+system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011842 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.011558 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.011284 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011842 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.011558 # miss rate for overall accesses
+system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.icache.fast_writes 0 # number of fast writes performed
+system.cpu0.icache.cache_copies 0 # number of cache copies performed
+system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 15527003 # DTB read hits
-system.cpu1.dtb.read_misses 5395 # DTB read misses
-system.cpu1.dtb.write_hits 11842462 # DTB write hits
+system.cpu1.dtb.read_hits 15527184 # DTB read hits
+system.cpu1.dtb.read_misses 5393 # DTB read misses
+system.cpu1.dtb.write_hits 11842180 # DTB write hits
system.cpu1.dtb.write_misses 794 # DTB write misses
system.cpu1.dtb.flush_tlb 2817 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 3188 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_entries 3187 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 923 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 922 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 243 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 15532398 # DTB read accesses
-system.cpu1.dtb.write_accesses 11843256 # DTB write accesses
+system.cpu1.dtb.read_accesses 15532577 # DTB read accesses
+system.cpu1.dtb.write_accesses 11842974 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 27369465 # DTB hits
-system.cpu1.dtb.misses 6189 # DTB misses
-system.cpu1.dtb.accesses 27375654 # DTB accesses
+system.cpu1.dtb.hits 27369364 # DTB hits
+system.cpu1.dtb.misses 6187 # DTB misses
+system.cpu1.dtb.accesses 27375551 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 72238481 # ITB inst hits
-system.cpu1.itb.inst_misses 3051 # ITB inst misses
+system.cpu1.itb.inst_hits 72239267 # ITB inst hits
+system.cpu1.itb.inst_misses 3050 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.flush_tlb_mva 514 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 2021 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_entries 2020 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 72241532 # ITB inst accesses
-system.cpu1.itb.hits 72238481 # DTB hits
-system.cpu1.itb.misses 3051 # DTB misses
-system.cpu1.itb.accesses 72241532 # DTB accesses
-system.cpu1.numCycles 88014935 # number of cpu cycles simulated
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+system.cpu1.itb.misses 3050 # DTB misses
+system.cpu1.itb.accesses 72242317 # DTB accesses
+system.cpu1.numCycles 88015463 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 70131496 # Number of instructions committed
-system.cpu1.committedOps 85819244 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 75668739 # Number of integer alu accesses
+system.cpu1.committedInsts 70132196 # Number of instructions committed
+system.cpu1.committedOps 85819687 # Number of ops (including micro ops) committed
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system.cpu1.num_fp_alu_accesses 6195 # Number of float alu accesses
-system.cpu1.num_func_calls 8179428 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 9270456 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 75668739 # number of integer instructions
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system.cpu1.num_fp_insts 6195 # number of float instructions
-system.cpu1.num_int_register_reads 140985899 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 52730443 # number of times the integer registers were written
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system.cpu1.num_fp_register_reads 4705 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 1492 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 261968424 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 30529611 # number of times the CC registers were written
-system.cpu1.num_mem_refs 28028993 # number of memory refs
-system.cpu1.num_load_insts 15690755 # Number of load instructions
-system.cpu1.num_store_insts 12338238 # Number of store instructions
-system.cpu1.num_idle_cycles 85360290.427990 # Number of idle cycles
-system.cpu1.num_busy_cycles 2654644.572010 # Number of busy cycles
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system.cpu1.not_idle_fraction 0.030161 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.969839 # Percentage of idle cycles
-system.cpu1.Branches 17795920 # Number of branches fetched
+system.cpu1.Branches 17796134 # Number of branches fetched
system.cpu1.op_class::No_OpClass 149 0.00% 0.00% # Class of executed instruction
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system.cpu1.op_class::IntDiv 0 0.00% 67.95% # Class of executed instruction
system.cpu1.op_class::FloatAdd 0 0.00% 67.95% # Class of executed instruction
system.cpu1.op_class::FloatCmp 0 0.00% 67.95% # Class of executed instruction
system.cpu1.op_class::SimdFloatMult 0 0.00% 67.95% # Class of executed instruction
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 67.95% # Class of executed instruction
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 67.95% # Class of executed instruction
-system.cpu1.op_class::MemRead 15690755 17.94% 85.89% # Class of executed instruction
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system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 87465184 # Class of executed instruction
+system.cpu1.op_class::total 87465632 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
+system.iobus.trans_dist::ReadReq 30171 # Transaction distribution
+system.iobus.trans_dist::ReadResp 30171 # Transaction distribution
+system.iobus.trans_dist::WriteReq 59016 # Transaction distribution
+system.iobus.trans_dist::WriteResp 22792 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
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system.iocache.tags.replacements 36430 # number of replacements
-system.iocache.tags.tagsinuse 0.909891 # Cycle average of tags in use
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system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 36446 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 227409731009 # Cycle when the warmup percentage was hit.
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system.iocache.tags.occ_percent::realview.ide 0.056868 # Average percentage of cache occupancy
system.iocache.tags.occ_percent::total 0.056868 # Average percentage of cache occupancy
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
system.iocache.fast_writes 36224 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.l2c.Writeback_hits::total 682260 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data 12 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 16 # number of UpgradeReq hits
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+system.l2c.demand_hits::total 2352094 # number of demand (read+write) hits
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+system.l2c.overall_hits::cpu0.itb.walker 2286 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 833265 # number of overall hits
+system.l2c.overall_hits::cpu0.data 319034 # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker 4981 # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker 2429 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 847884 # number of overall hits
+system.l2c.overall_hits::cpu1.data 337496 # number of overall hits
+system.l2c.overall_hits::total 2352094 # number of overall hits
+system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst 10795 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data 9750 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker 2 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst 7563 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data 5779 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 33895 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 1249 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data 1479 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 2728 # number of UpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data 2 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data 63970 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data 83894 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 147864 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst 10795 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data 73720 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker 2 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst 7563 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data 89673 # number of demand (read+write) misses
+system.l2c.demand_misses::total 181759 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
+system.l2c.overall_misses::cpu0.inst 10795 # number of overall misses
+system.l2c.overall_misses::cpu0.data 73720 # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker 2 # number of overall misses
+system.l2c.overall_misses::cpu1.inst 7563 # number of overall misses
+system.l2c.overall_misses::cpu1.data 89673 # number of overall misses
+system.l2c.overall_misses::total 181759 # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.dtb.walker 4724 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker 2287 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst 844060 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data 256459 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker 4983 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker 2429 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst 855447 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data 264557 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total 2234946 # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 682260 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total 682260 # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data 1261 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data 1495 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data 2 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data 136295 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data 162612 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total 298907 # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.dtb.walker 4724 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker 2287 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst 844060 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data 392754 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker 4983 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker 2429 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst 855447 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data 427169 # number of demand (read+write) accesses
+system.l2c.demand_accesses::total 2533853 # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker 4724 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker 2287 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst 844060 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data 392754 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker 4983 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker 2429 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst 855447 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data 427169 # number of overall (read+write) accesses
+system.l2c.overall_accesses::total 2533853 # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.001058 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000437 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst 0.012789 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data 0.038018 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst 0.008841 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data 0.021844 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total 0.015166 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990484 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989298 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total 0.989840 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data 0.469350 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data 0.515915 # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total 0.494682 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker 0.001058 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker 0.000437 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst 0.012789 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data 0.187700 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst 0.008841 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data 0.209924 # miss rate for demand accesses
+system.l2c.demand_miss_rate::total 0.071732 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker 0.001058 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker 0.000437 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst 0.012789 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data 0.187700 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000401 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst 0.008841 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data 0.209924 # miss rate for overall accesses
+system.l2c.overall_miss_rate::total 0.071732 # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
+system.l2c.blocked::no_targets 0 # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.l2c.fast_writes 0 # number of fast writes performed
+system.l2c.cache_copies 0 # number of cache copies performed
+system.l2c.writebacks::writebacks 101893 # number of writebacks
+system.l2c.writebacks::total 101893 # number of writebacks
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 74229 # Transaction distribution
+system.membus.trans_dist::ReadResp 74229 # Transaction distribution
+system.membus.trans_dist::WriteReq 27560 # Transaction distribution
+system.membus.trans_dist::WriteResp 27560 # Transaction distribution
+system.membus.trans_dist::Writeback 101893 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 4507 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 4509 # Transaction distribution
+system.membus.trans_dist::ReadExReq 146085 # Transaction distribution
+system.membus.trans_dist::ReadExResp 146085 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105446 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1946 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 498777 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 606179 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72928 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 72928 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 679107 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159103 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3892 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18095740 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 18258755 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2333696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 2333696 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 20592451 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 0 # Total snoops (count)
+system.membus.snoop_fanout::samples 322846 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 322846 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 322846 # Request fanout histogram
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 2291800 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 2291800 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 27560 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 27560 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 682260 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 2758 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 298907 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 298907 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3417092 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2444886 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 20766 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 41566 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 5924310 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 108805624 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 96322507 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 41532 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 83132 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 205252795 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 36632 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 3272095 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 5.011144 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.104975 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 3235631 98.89% 98.89% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 36464 1.11% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 3272095 # Request fanout histogram
---------- End Simulation Statistics ----------
---------- Begin Simulation Statistics ----------
-sim_seconds 47.438275 # Number of seconds simulated
-sim_ticks 47438274662000 # Number of ticks simulated
-final_tick 47438274662000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 47.566016 # Number of seconds simulated
+sim_ticks 47566015848000 # Number of ticks simulated
+final_tick 47566015848000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 649244 # Simulator instruction rate (inst/s)
-host_op_rate 763603 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 34889420828 # Simulator tick rate (ticks/s)
-host_mem_usage 811016 # Number of bytes of host memory used
-host_seconds 1359.68 # Real time elapsed on the host
-sim_insts 882760938 # Number of instructions simulated
-sim_ops 1038251286 # Number of ops (including micro ops) simulated
+host_inst_rate 675626 # Simulator instruction rate (inst/s)
+host_op_rate 794684 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 35963293075 # Simulator tick rate (ticks/s)
+host_mem_usage 873656 # Number of bytes of host memory used
+host_seconds 1322.63 # Real time elapsed on the host
+sim_insts 893600449 # Number of instructions simulated
+sim_ops 1051070162 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.bytes_read::realview.ide 477376 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 221952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 405952 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 701748 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 13046680 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.l2cache.prefetcher 27196672 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 278976 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 430208 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 568824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 13928160 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.l2cache.prefetcher 27822464 # Number of bytes read from this memory
-system.physmem.bytes_read::total 85079012 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 701748 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 568824 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1270572 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 44376640 # Number of bytes written to this memory
-system.physmem.bytes_written::realview.ide 6830592 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 54965772 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 45117316 # Number of bytes written to this memory
-system.physmem.bytes_written::total 151290320 # Number of bytes written to this memory
-system.physmem.num_reads::realview.ide 7459 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 3468 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 6343 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 51372 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 203876 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.l2cache.prefetcher 424948 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 4359 # Number of read requests responded to by this memory
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 10 # Number of times write queue was full causing retry
-system.physmem.totGap 47438271681000 # Total gap between requests
+system.physmem.numWrRetry 9 # Number of times write queue was full causing retry
+system.physmem.totGap 47566012867000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 43195 # Read request sizes (log2)
system.physmem.readPktSize::3 37 # Read request sizes (log2)
system.physmem.readPktSize::4 5 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 2 # Write request sizes (log2)
system.physmem.writePktSize::3 2601 # Write request sizes (log2)
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system.physmem.wrQLenPdf::63 22 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 831449 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 280.321107 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 152.348246 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 337.173071 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 412387 49.60% 49.60% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 160013 19.25% 68.84% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 57469 6.91% 75.76% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 29190 3.51% 79.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 24961 3.00% 82.27% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 16130 1.94% 84.21% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 12424 1.49% 85.70% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 12438 1.50% 87.20% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 106437 12.80% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 831449 # Bytes accessed per row activation
-system.physmem.rdPerTurnAround::samples 117879 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::mean 11.582360 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::stdev 193.016425 # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::0-2047 117876 100.00% 100.00% # Reads before turning the bus around for writes
+system.physmem.bytesPerActivate::samples 832768 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::mean 280.211728 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::gmean 152.211424 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::stdev 337.275385 # Bytes accessed per row activation
+system.physmem.bytesPerActivate::0-127 413524 49.66% 49.66% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::128-255 160093 19.22% 68.88% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::256-383 57236 6.87% 75.75% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::384-511 29306 3.52% 79.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::512-639 24972 3.00% 82.27% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::640-767 16042 1.93% 84.20% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::768-895 12534 1.51% 85.70% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::896-1023 12228 1.47% 87.17% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::1024-1151 106833 12.83% 100.00% # Bytes accessed per row activation
+system.physmem.bytesPerActivate::total 832768 # Bytes accessed per row activation
+system.physmem.rdPerTurnAround::samples 117976 # Reads before turning the bus around for writes
+system.physmem.rdPerTurnAround::mean 11.586017 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::20480-22527 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::24576-26623 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::57344-59391 1 0.00% 100.00% # Reads before turning the bus around for writes
-system.physmem.rdPerTurnAround::total 117879 # Reads before turning the bus around for writes
-system.physmem.wrPerTurnAround::samples 117879 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::mean 19.311497 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::gmean 18.988433 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::stdev 4.874271 # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::16-19 75351 63.92% 63.92% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::20-23 36700 31.13% 95.06% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::24-27 3007 2.55% 97.61% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::28-31 902 0.77% 98.37% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::32-35 786 0.67% 99.04% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::36-39 199 0.17% 99.21% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::40-43 149 0.13% 99.33% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::44-47 77 0.07% 99.40% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::52-55 16 0.01% 99.48% # Writes before turning the bus around for reads
+system.physmem.rdPerTurnAround::total 117976 # Reads before turning the bus around for writes
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+system.physmem.wrPerTurnAround::mean 19.319548 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::56-59 14 0.01% 99.49% # Writes before turning the bus around for reads
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-system.physmem.wrPerTurnAround::64-67 396 0.34% 99.84% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::76-79 22 0.02% 99.92% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::92-95 4 0.00% 99.96% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::96-99 10 0.01% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::100-103 1 0.00% 99.97% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::112-115 6 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::120-123 1 0.00% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::124-127 1 0.00% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::140-143 4 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::168-171 1 0.00% 100.00% # Writes before turning the bus around for reads
-system.physmem.wrPerTurnAround::total 117879 # Writes before turning the bus around for reads
-system.physmem.totQLat 39355914512 # Total ticks spent queuing
-system.physmem.totMemAccLat 64956395762 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 6826795000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 28824.59 # Average queueing delay per DRAM burst
+system.physmem.wrPerTurnAround::total 117976 # Writes before turning the bus around for reads
+system.physmem.totQLat 39242427762 # Total ticks spent queuing
+system.physmem.totMemAccLat 64871502762 # Total ticks spent from burst creation until serviced by the DRAM
+system.physmem.totBusLat 6834420000 # Total ticks spent in databus transfers
+system.physmem.avgQLat 28709.41 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 47574.59 # Average memory access latency per DRAM burst
+system.physmem.avgMemAccLat 47459.41 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1.84 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 3.07 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1.79 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s
+system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.04 # Data bus utilization in percentage
system.physmem.busUtilRead 0.01 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.35 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 26.79 # Average write queue length when enqueuing
-system.physmem.readRowHits 1064531 # Number of row buffer hits during reads
-system.physmem.writeRowHits 1745793 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 77.97 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 76.69 # Row buffer hit rate for writes
-system.physmem.avgGap 12697338.30 # Average gap between requests
-system.physmem.pageHitRate 77.17 # Row buffer hit rate, read and write combined
-system.physmem.memoryStateTime::IDLE 45390521349500 # Time in different power states
-system.physmem.memoryStateTime::REF 1584068200000 # Time in different power states
+system.physmem.avgRdQLen 1.32 # Average read queue length when enqueuing
+system.physmem.avgWrQLen 22.10 # Average write queue length when enqueuing
+system.physmem.readRowHits 1063781 # Number of row buffer hits during reads
+system.physmem.writeRowHits 1749574 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 77.83 # Row buffer hit rate for reads
+system.physmem.writeRowHitRate 76.76 # Row buffer hit rate for writes
+system.physmem.avgGap 12716335.61 # Average gap between requests
+system.physmem.pageHitRate 77.16 # Row buffer hit rate, read and write combined
+system.physmem.memoryStateTime::IDLE 45509072189751 # Time in different power states
+system.physmem.memoryStateTime::REF 1588333760000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
-system.physmem.memoryStateTime::ACT 463683887500 # Time in different power states
+system.physmem.memoryStateTime::ACT 468608703999 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
-system.physmem.actEnergy::0 3148966800 # Energy for activate commands per rank (pJ)
-system.physmem.actEnergy::1 3136780080 # Energy for activate commands per rank (pJ)
-system.physmem.preEnergy::0 1718186250 # Energy for precharge commands per rank (pJ)
-system.physmem.preEnergy::1 1711536750 # Energy for precharge commands per rank (pJ)
-system.physmem.readEnergy::0 5202085200 # Energy for read commands per rank (pJ)
-system.physmem.readEnergy::1 5447566800 # Energy for read commands per rank (pJ)
-system.physmem.writeEnergy::0 7517817360 # Energy for write commands per rank (pJ)
-system.physmem.writeEnergy::1 7233384240 # Energy for write commands per rank (pJ)
-system.physmem.refreshEnergy::0 3098437399200 # Energy for refresh commands per rank (pJ)
-system.physmem.refreshEnergy::1 3098437399200 # Energy for refresh commands per rank (pJ)
-system.physmem.actBackEnergy::0 1260445205745 # Energy for active background per rank (pJ)
-system.physmem.actBackEnergy::1 1262996298315 # Energy for active background per rank (pJ)
-system.physmem.preBackEnergy::0 27357310364250 # Energy for precharge background per rank (pJ)
-system.physmem.preBackEnergy::1 27355072563750 # Energy for precharge background per rank (pJ)
-system.physmem.totalEnergy::0 31733780024805 # Total energy per rank (pJ)
-system.physmem.totalEnergy::1 31734035529135 # Total energy per rank (pJ)
-system.physmem.averagePower::0 668.948883 # Core power per rank (mW)
-system.physmem.averagePower::1 668.954269 # Core power per rank (mW)
+system.physmem.actEnergy::0 3171472920 # Energy for activate commands per rank (pJ)
+system.physmem.actEnergy::1 3124253160 # Energy for activate commands per rank (pJ)
+system.physmem.preEnergy::0 1730466375 # Energy for precharge commands per rank (pJ)
+system.physmem.preEnergy::1 1704701625 # Energy for precharge commands per rank (pJ)
+system.physmem.readEnergy::0 5218192200 # Energy for read commands per rank (pJ)
+system.physmem.readEnergy::1 5443409400 # Energy for read commands per rank (pJ)
+system.physmem.writeEnergy::0 7613086320 # Energy for write commands per rank (pJ)
+system.physmem.writeEnergy::1 7156408320 # Energy for write commands per rank (pJ)
+system.physmem.refreshEnergy::0 3106780834560 # Energy for refresh commands per rank (pJ)
+system.physmem.refreshEnergy::1 3106780834560 # Energy for refresh commands per rank (pJ)
+system.physmem.actBackEnergy::0 1266482203425 # Energy for active background per rank (pJ)
+system.physmem.actBackEnergy::1 1265693181210 # Energy for active background per rank (pJ)
+system.physmem.preBackEnergy::0 27428659482750 # Energy for precharge background per rank (pJ)
+system.physmem.preBackEnergy::1 27429351607500 # Energy for precharge background per rank (pJ)
+system.physmem.totalEnergy::0 31819655738550 # Total energy per rank (pJ)
+system.physmem.totalEnergy::1 31819254395775 # Total energy per rank (pJ)
+system.physmem.averagePower::0 668.957784 # Core power per rank (mW)
+system.physmem.averagePower::1 668.949346 # Core power per rank (mW)
system.realview.nvmem.bytes_read::cpu0.inst 96 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu0.data 36 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::cpu1.inst 64 # Number of bytes read from this memory
system.realview.nvmem.bw_total::cpu1.inst 1 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu1.data 0 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 4 # Total bandwidth to/from this memory (bytes/s)
-system.membus.trans_dist::ReadReq 1262651 # Transaction distribution
-system.membus.trans_dist::ReadResp 1262651 # Transaction distribution
-system.membus.trans_dist::WriteReq 38160 # Transaction distribution
-system.membus.trans_dist::WriteResp 38160 # Transaction distribution
-system.membus.trans_dist::Writeback 693385 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateReq 1670201 # Transaction distribution
-system.membus.trans_dist::WriteInvalidateResp 1670201 # Transaction distribution
-system.membus.trans_dist::UpgradeReq 307572 # Transaction distribution
-system.membus.trans_dist::SCUpgradeReq 298715 # Transaction distribution
-system.membus.trans_dist::UpgradeResp 95343 # Transaction distribution
-system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution
-system.membus.trans_dist::ReadExReq 162530 # Transaction distribution
-system.membus.trans_dist::ReadExResp 146943 # Transaction distribution
-system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123084 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 24300 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7267614 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.l2c.mem_side::total 7415090 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 229896 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count_system.iocache.mem_side::total 229896 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 7644986 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156191 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 48600 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 229061364 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.l2c.mem_side::total 229266359 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7307968 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size_system.iocache.mem_side::total 7307968 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 236574327 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 528061 # Total snoops (count)
-system.membus.snoop_fanout::samples 4313648 # Request fanout histogram
-system.membus.snoop_fanout::mean 1 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::1 4313648 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 1 # Request fanout histogram
-system.membus.snoop_fanout::max_value 1 # Request fanout histogram
-system.membus.snoop_fanout::total 4313648 # Request fanout histogram
-system.membus.reqLayer0.occupancy 100869991 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
-system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer2.occupancy 21144997 # Layer occupancy (ticks)
-system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.reqLayer5.occupancy 23127462719 # Layer occupancy (ticks)
-system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer2.occupancy 14206266380 # Layer occupancy (ticks)
-system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.membus.respLayer3.occupancy 187834022 # Layer occupancy (ticks)
-system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.l2c.tags.replacements 1088949 # number of replacements
-system.l2c.tags.tagsinuse 64239.358232 # Cycle average of tags in use
-system.l2c.tags.total_refs 6591556 # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs 1149786 # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs 5.732855 # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks 9309.879147 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker 38.225449 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker 41.200627 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst 627.976202 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data 3676.898634 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 16318.952466 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker 311.035795 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.itb.walker 436.956601 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst 693.970644 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data 9626.822610 # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 23157.440058 # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks 0.142057 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000583 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker 0.000629 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst 0.009582 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data 0.056105 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.249007 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker 0.004746 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.itb.walker 0.006667 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst 0.010589 # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data 0.146894 # Average percentage of cache occupancy
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-system.l2c.tags.occ_percent::total 0.980215 # Average percentage of cache occupancy
-system.l2c.tags.occ_task_id_blocks::1022 32295 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1023 314 # Occupied blocks per task id
-system.l2c.tags.occ_task_id_blocks::1024 28228 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::0 21 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::1 137 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::2 836 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::3 1678 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1022::4 29623 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::1 4 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::3 31 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1023::4 268 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::1 194 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::2 1122 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::3 4068 # Occupied blocks per task id
-system.l2c.tags.age_task_id_blocks_1024::4 22816 # Occupied blocks per task id
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-system.l2c.tags.occ_task_id_percent::1023 0.004791 # Percentage of cache occupancy per task id
-system.l2c.tags.occ_task_id_percent::1024 0.430725 # Percentage of cache occupancy per task id
-system.l2c.tags.tag_accesses 79894517 # Number of tag accesses
-system.l2c.tags.data_accesses 79894517 # Number of data accesses
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-system.l2c.ReadReq_hits::cpu0.itb.walker 3906 # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu0.data 569496 # number of ReadReq hits
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-system.l2c.ReadReq_hits::cpu1.inst 144360 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data 647503 # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 1630669 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 4632835 # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks 1982686 # number of Writeback hits
-system.l2c.Writeback_hits::total 1982686 # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data 22177 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::cpu1.data 28734 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 50911 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu0.data 6966 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::cpu1.data 8106 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 15072 # number of SCUpgradeReq hits
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-system.l2c.ReadExReq_hits::cpu1.data 51237 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 99674 # number of ReadExReq hits
-system.l2c.demand_hits::cpu0.dtb.walker 5969 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.itb.walker 3906 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.inst 130836 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data 617933 # number of demand (read+write) hits
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-system.l2c.demand_hits::cpu1.itb.walker 4630 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst 144360 # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data 698740 # number of demand (read+write) hits
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-system.l2c.overall_hits::cpu0.dtb.walker 5969 # number of overall hits
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-system.l2c.overall_hits::cpu0.inst 130836 # number of overall hits
-system.l2c.overall_hits::cpu0.data 617933 # number of overall hits
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-system.l2c.overall_hits::cpu1.inst 144360 # number of overall hits
-system.l2c.overall_hits::cpu1.data 698740 # number of overall hits
-system.l2c.overall_hits::cpu1.l2cache.prefetcher 1630669 # number of overall hits
-system.l2c.overall_hits::total 4732509 # number of overall hits
-system.l2c.ReadReq_misses::cpu0.dtb.walker 3468 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.itb.walker 6343 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.inst 8294 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data 128231 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 425212 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.dtb.walker 4359 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.itb.walker 6722 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst 8893 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data 146336 # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 434855 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 1172713 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data 33912 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data 36287 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 70199 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu0.data 10020 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::cpu1.data 11790 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 21810 # number of SCUpgradeReq misses
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-system.l2c.ReadExReq_misses::total 150274 # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.dtb.walker 3468 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.itb.walker 6343 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.inst 8294 # number of demand (read+write) misses
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-system.l2c.demand_misses::cpu1.inst 8893 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data 219480 # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.l2cache.prefetcher 434855 # number of demand (read+write) misses
-system.l2c.demand_misses::total 1322987 # number of demand (read+write) misses
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-system.l2c.overall_misses::total 1322987 # number of overall misses
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-system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.558081 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 0.579630 # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.589898 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.592581 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.591345 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.614254 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.588064 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 0.601221 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.data 0.249421 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.data 0.239009 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0.218401 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.367490 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.618890 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.inst 0.059448 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.data 0.249421 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.221983 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.407041 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.592142 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.057956 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.239009 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.210468 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.218401 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 68662.169759 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68748.745549 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 86797.091849 # average ReadReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
-system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10155.620990 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10137.957643 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10146.490520 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10189.160479 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10233.726378 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10213.251811 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60820.714391 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60469.605176 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 60649.816349 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65716.855474 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 65989.421912 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 83826.075199 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67475.561419 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67697.618004 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 75401.371781 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65716.855474 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92779.791130 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66479.810507 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66432.719726 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76896.166291 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 65989.421912 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93742.815325 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 83826.075199 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.realview.ethernet.txBytes 966 # Bytes Transmitted
-system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
-system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
-system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
-system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
-system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
-system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
-system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
-system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
-system.realview.ethernet.totBandwidth 163 # Total Bandwidth (bits/s)
-system.realview.ethernet.totPackets 3 # Total Packets
-system.realview.ethernet.totBytes 966 # Total Bytes
-system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
-system.realview.ethernet.txBandwidth 163 # Transmit Bandwidth (bits/s)
-system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
-system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
-system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
-system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
-system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
-system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
-system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
-system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
-system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
-system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
-system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
-system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
-system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
-system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
-system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
-system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
-system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
-system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
-system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
-system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
-system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
-system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
-system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
-system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
-system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
-system.realview.ethernet.droppedPackets 0 # number of packets dropped
system.cf0.dma_read_full_pages 122 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 499712 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 122 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 1667 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 6830592 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 1670 # Number of DMA write transactions.
-system.toL2Bus.trans_dist::ReadReq 6645186 # Transaction distribution
-system.toL2Bus.trans_dist::ReadResp 6637629 # Transaction distribution
-system.toL2Bus.trans_dist::WriteReq 38160 # Transaction distribution
-system.toL2Bus.trans_dist::WriteResp 38160 # Transaction distribution
-system.toL2Bus.trans_dist::Writeback 1982686 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution
-system.toL2Bus.trans_dist::WriteInvalidateResp 1563473 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeReq 355152 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeReq 313787 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeResp 668939 # Transaction distribution
-system.toL2Bus.trans_dist::SCUpgradeFailReq 102 # Transaction distribution
-system.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExReq 297718 # Transaction distribution
-system.toL2Bus.trans_dist::ReadExResp 297718 # Transaction distribution
-system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 9432330 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9652916 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_count::total 19085246 # Packet count per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 302653655 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 312342176 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.pkt_size::total 614995831 # Cumulative packet size per connected master and slave (bytes)
-system.toL2Bus.snoops 1425200 # Total snoops (count)
-system.toL2Bus.snoop_fanout::samples 11183456 # Request fanout histogram
-system.toL2Bus.snoop_fanout::mean 1.010347 # Request fanout histogram
-system.toL2Bus.snoop_fanout::stdev 0.101194 # Request fanout histogram
-system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::1 11067738 98.97% 98.97% # Request fanout histogram
-system.toL2Bus.snoop_fanout::2 115718 1.03% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
-system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
-system.toL2Bus.snoop_fanout::total 11183456 # Request fanout histogram
-system.toL2Bus.reqLayer0.occupancy 19814172733 # Layer occupancy (ticks)
-system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.snoopLayer0.occupancy 6396000 # Layer occupancy (ticks)
-system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer0.occupancy 15605521398 # Layer occupancy (ticks)
-system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.toL2Bus.respLayer1.occupancy 16621378743 # Layer occupancy (ticks)
-system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.trans_dist::ReadReq 40465 # Transaction distribution
-system.iobus.trans_dist::ReadResp 40465 # Transaction distribution
-system.iobus.trans_dist::WriteReq 136732 # Transaction distribution
-system.iobus.trans_dist::WriteResp 136786 # Transaction distribution
-system.iobus.trans_dist::WriteInvalidateReq 54 # Transaction distribution
-system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48150 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29600 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.bridge.master::total 123084 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231338 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ide.dma::total 231338 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_count::total 354502 # Packet count per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48170 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 48 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 17587 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 263 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 89500 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 251 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.bridge.master::total 156191 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 7339368 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ide.dma::total 7339368 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::system.iocache.cpu_side 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size_system.realview.ethernet.dma::total 2086 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.pkt_size::total 7497645 # Cumulative packet size per connected master and slave (bytes)
-system.iobus.reqLayer0.occupancy 36603000 # Layer occupancy (ticks)
-system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer1.occupancy 9000 # Layer occupancy (ticks)
-system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer16.occupancy 12000 # Layer occupancy (ticks)
-system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
-system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer23.occupancy 21986000 # Layer occupancy (ticks)
-system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer24.occupancy 142000 # Layer occupancy (ticks)
-system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer25.occupancy 32658000 # Layer occupancy (ticks)
-system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer26.occupancy 101000 # Layer occupancy (ticks)
-system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer27.occupancy 981958721 # Layer occupancy (ticks)
-system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
-system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks)
-system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer0.occupancy 93029000 # Layer occupancy (ticks)
-system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer3.occupancy 179341978 # Layer occupancy (ticks)
-system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iobus.respLayer4.occupancy 297000 # Layer occupancy (ticks)
-system.iobus.respLayer4.utilization 0.0 # Layer utilization (%)
+system.cf0.dma_write_full_pages 1671 # Number of full page size DMA writes.
+system.cf0.dma_write_bytes 6846976 # Number of bytes transfered via DMA writes.
+system.cf0.dma_write_txs 1674 # Number of DMA write transactions.
+system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 81279666 # DTB read hits
-system.cpu0.dtb.read_misses 78948 # DTB read misses
-system.cpu0.dtb.write_hits 73742535 # DTB write hits
-system.cpu0.dtb.write_misses 27290 # DTB write misses
+system.cpu0.dtb.read_hits 86716512 # DTB read hits
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+system.cpu0.dtb.write_hits 78633728 # DTB write hits
+system.cpu0.dtb.write_misses 28389 # DTB write misses
system.cpu0.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 31886 # Number of entries that have been flushed from TLB
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+system.cpu0.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
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system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 3595 # Number of TLB faults due to prefetch
+system.cpu0.dtb.prefetch_faults 4682 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 8523 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 81358614 # DTB read accesses
-system.cpu0.dtb.write_accesses 73769825 # DTB write accesses
+system.cpu0.dtb.perms_faults 9159 # Number of TLB faults due to permissions restrictions
+system.cpu0.dtb.read_accesses 86799224 # DTB read accesses
+system.cpu0.dtb.write_accesses 78662117 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
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-system.cpu0.dtb.misses 106238 # DTB misses
-system.cpu0.dtb.accesses 155128439 # DTB accesses
+system.cpu0.dtb.hits 165350240 # DTB hits
+system.cpu0.dtb.misses 111101 # DTB misses
+system.cpu0.dtb.accesses 165461341 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu0.itb.inst_hits 432012599 # ITB inst hits
-system.cpu0.itb.inst_misses 54786 # ITB inst misses
+system.cpu0.itb.inst_hits 459685693 # ITB inst hits
+system.cpu0.itb.inst_misses 60045 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID
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+system.cpu0.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
+system.cpu0.itb.flush_entries 24187 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 432067385 # ITB inst accesses
-system.cpu0.itb.hits 432012599 # DTB hits
-system.cpu0.itb.misses 54786 # DTB misses
-system.cpu0.itb.accesses 432067385 # DTB accesses
-system.cpu0.numCycles 94876549324 # number of cpu cycles simulated
+system.cpu0.itb.inst_accesses 459745738 # ITB inst accesses
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+system.cpu0.itb.misses 60045 # DTB misses
+system.cpu0.itb.accesses 459745738 # DTB accesses
+system.cpu0.numCycles 95132031682 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 431769250 # Number of instructions committed
-system.cpu0.committedOps 507110651 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 465722099 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 423380 # Number of float alu accesses
-system.cpu0.num_func_calls 25579239 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 65525116 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 465722099 # number of integer instructions
-system.cpu0.num_fp_insts 423380 # number of float instructions
-system.cpu0.num_int_register_reads 674979358 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 369311745 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 705560 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 308536 # number of times the floating registers were written
-system.cpu0.num_cc_register_reads 112703400 # number of times the CC registers were read
-system.cpu0.num_cc_register_writes 112387692 # number of times the CC registers were written
-system.cpu0.num_mem_refs 155012297 # number of memory refs
-system.cpu0.num_load_insts 81273219 # Number of load instructions
-system.cpu0.num_store_insts 73739078 # Number of store instructions
-system.cpu0.num_idle_cycles 93821929037.552032 # Number of idle cycles
-system.cpu0.num_busy_cycles 1054620286.447978 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.011116 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.988884 # Percentage of idle cycles
-system.cpu0.Branches 96363585 # Number of branches fetched
-system.cpu0.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
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-system.cpu0.op_class::FloatAdd 0 0.00% 69.44% # Class of executed instruction
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-system.cpu0.op_class::FloatSqrt 0 0.00% 69.44% # Class of executed instruction
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-system.cpu0.op_class::SimdAddAcc 0 0.00% 69.44% # Class of executed instruction
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-system.cpu0.op_class::SimdMisc 0 0.00% 69.44% # Class of executed instruction
-system.cpu0.op_class::SimdMult 0 0.00% 69.44% # Class of executed instruction
-system.cpu0.op_class::SimdMultAcc 0 0.00% 69.44% # Class of executed instruction
-system.cpu0.op_class::SimdShift 0 0.00% 69.44% # Class of executed instruction
-system.cpu0.op_class::SimdShiftAcc 0 0.00% 69.44% # Class of executed instruction
-system.cpu0.op_class::SimdSqrt 0 0.00% 69.44% # Class of executed instruction
-system.cpu0.op_class::SimdFloatAdd 0 0.00% 69.44% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatDiv 0 0.00% 69.44% # Class of executed instruction
-system.cpu0.op_class::SimdFloatMisc 43852 0.01% 69.45% # Class of executed instruction
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-system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 69.45% # Class of executed instruction
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+system.cpu0.committedInsts 459439593 # Number of instructions committed
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+system.cpu0.num_fp_register_reads 749199 # number of times the floating registers were read
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+system.cpu0.num_cc_register_reads 119686995 # number of times the CC registers were read
+system.cpu0.num_cc_register_writes 119275623 # number of times the CC registers were written
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+system.cpu0.not_idle_fraction 0.011746 # Percentage of non-idle cycles
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system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
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-system.cpu0.op_class::total 507397124 # Class of executed instruction
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system.cpu0.kern.inst.arm 0 # number of arm instructions executed
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-system.cpu0.icache.tags.replacements 4835795 # number of replacements
-system.cpu0.icache.tags.tagsinuse 511.921057 # Cycle average of tags in use
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-system.cpu0.icache.tags.sampled_refs 4836307 # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs 88.326959 # Average number of references to valid blocks.
+system.cpu0.kern.inst.quiesce 5368 # number of quiesce instructions executed
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+system.cpu0.dcache.tags.avg_refs 28.732325 # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.occ_blocks::cpu0.data 507.463915 # Average occupied blocks per requestor
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+system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 887570 # number of WriteInvalidateReq accesses(hits+misses)
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+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14644.899283 # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_miss_latency::total 14644.899283 # average ReadReq miss latency
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+system.cpu0.dcache.WriteReq_avg_miss_latency::total 17438.281297 # average WriteReq miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14303.470262 # average LoadLockedReq miss latency
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+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21297.810517 # average StoreCondReq miss latency
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+system.cpu0.dcache.overall_avg_miss_latency::total 13535.158750 # average overall miss latency
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+system.cpu0.dcache.writebacks::total 3048439 # number of writebacks
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11626.866562 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu0.icache.tags.warmup_cycle 24248022750 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.921057 # Average occupied blocks per requestor
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system.cpu0.icache.tags.occ_percent::total 0.999846 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::1 288 # Occupied blocks per task id
-system.cpu0.icache.tags.age_task_id_blocks_1024::2 164 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::1 309 # Occupied blocks per task id
+system.cpu0.icache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
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-system.cpu0.icache.ReadReq_hits::total 427176292 # number of ReadReq hits
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-system.cpu0.icache.ReadReq_miss_latency::total 42021880066 # number of ReadReq miss cycles
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-system.cpu0.icache.demand_accesses::total 432012599 # number of demand (read+write) accesses
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-system.cpu0.icache.ReadReq_avg_miss_latency::total 8688.836351 # average ReadReq miss latency
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-system.cpu0.icache.demand_avg_miss_latency::total 8688.836351 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8688.836351 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 8688.836351 # average overall miss latency
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+system.cpu0.icache.ReadReq_avg_miss_latency::total 8707.427163 # average ReadReq miss latency
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+system.cpu0.icache.demand_avg_miss_latency::total 8707.427163 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8707.427163 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 8707.427163 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
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-system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 4836307 # number of ReadReq MSHR misses
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-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38075.734399 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38075.734399 # average ReadExReq mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21046.237669 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27474.499568 # average overall mshr miss latency
-system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 27109.838885 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 34902.553865 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 57572.061950 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21046.237669 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27474.499568 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29835.210040 # average overall mshr miss latency
-system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28862.065867 # average overall mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 16985.050817 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16985.050817 # average UpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13836.770949 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13836.770949 # average SCUpgradeReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 400999.666667 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 400999.666667 # average SCUpgradeFailReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 37095.485130 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 37095.485130 # average ReadExReq mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27376.273319 # average overall mshr miss latency
+system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 26998.409412 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 35343.766601 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 56047.873755 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 21091.262702 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27376.273319 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 29174.283567 # average overall mshr miss latency
+system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 28404.400626 # average overall mshr miss latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements 5282593 # number of replacements
-system.cpu0.dcache.tags.tagsinuse 478.557100 # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs 149517101 # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs 5283105 # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs 28.300990 # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle 3644536500 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.tags.occ_blocks::cpu0.data 478.557100 # Average occupied blocks per requestor
-system.cpu0.dcache.tags.occ_percent::cpu0.data 0.934682 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total 0.934682 # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::1 411 # Occupied blocks per task id
-system.cpu0.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
-system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
-system.cpu0.dcache.tags.tag_accesses 315346998 # Number of tag accesses
-system.cpu0.dcache.tags.data_accesses 315346998 # Number of data accesses
-system.cpu0.dcache.ReadReq_hits::cpu0.data 75666916 # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total 75666916 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::cpu0.data 69634196 # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total 69634196 # number of WriteReq hits
-system.cpu0.dcache.SoftPFReq_hits::cpu0.data 181888 # number of SoftPFReq hits
-system.cpu0.dcache.SoftPFReq_hits::total 181888 # number of SoftPFReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::cpu0.data 858515 # number of WriteInvalidateReq hits
-system.cpu0.dcache.WriteInvalidateReq_hits::total 858515 # number of WriteInvalidateReq hits
-system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 1792597 # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total 1792597 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::cpu0.data 1751129 # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total 1751129 # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::cpu0.data 145301112 # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total 145301112 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::cpu0.data 145483000 # number of overall hits
-system.cpu0.dcache.overall_hits::total 145483000 # number of overall hits
-system.cpu0.dcache.ReadReq_misses::cpu0.data 2868190 # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total 2868190 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::cpu0.data 1290634 # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total 1290634 # number of WriteReq misses
-system.cpu0.dcache.SoftPFReq_misses::cpu0.data 609921 # number of SoftPFReq misses
-system.cpu0.dcache.SoftPFReq_misses::total 609921 # number of SoftPFReq misses
-system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 145533 # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total 145533 # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::cpu0.data 185941 # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total 185941 # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::cpu0.data 4158824 # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total 4158824 # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::cpu0.data 4768745 # number of overall misses
-system.cpu0.dcache.overall_misses::total 4768745 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 41686378389 # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_latency::total 41686378389 # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22767469365 # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency::total 22767469365 # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 2114986821 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency::total 2114986821 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 3970270831 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency::total 3970270831 # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1983000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1983000 # number of StoreCondFailReq miss cycles
-system.cpu0.dcache.demand_miss_latency::cpu0.data 64453847754 # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_latency::total 64453847754 # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency::cpu0.data 64453847754 # number of overall miss cycles
-system.cpu0.dcache.overall_miss_latency::total 64453847754 # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::cpu0.data 78535106 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total 78535106 # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::cpu0.data 70924830 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total 70924830 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 791809 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.SoftPFReq_accesses::total 791809 # number of SoftPFReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::cpu0.data 858515 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.WriteInvalidateReq_accesses::total 858515 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 1938130 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total 1938130 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 1937070 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total 1937070 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::cpu0.data 149459936 # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total 149459936 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::cpu0.data 150251745 # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total 150251745 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.036521 # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_miss_rate::total 0.036521 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.018197 # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::total 0.018197 # miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.770288 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_miss_rate::total 0.770288 # miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.075089 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.075089 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.095991 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::total 0.095991 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027826 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total 0.027826 # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::cpu0.data 0.031738 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total 0.031738 # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14534.036584 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total 14534.036584 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 17640.531216 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total 17640.531216 # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14532.695822 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14532.695822 # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 21352.315148 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21352.315148 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15498.094595 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total 15498.094595 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13515.893124 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total 13515.893124 # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes 858515 # number of fast writes performed
-system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks::writebacks 2894821 # number of writebacks
-system.cpu0.dcache.writebacks::total 2894821 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 28163 # number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_hits::total 28163 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 21327 # number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits::total 21327 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 41518 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits::total 41518 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits::cpu0.data 49490 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_hits::total 49490 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits::cpu0.data 49490 # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_hits::total 49490 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 2840027 # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_misses::total 2840027 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 1269307 # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses::total 1269307 # number of WriteReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 608681 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.SoftPFReq_mshr_misses::total 608681 # number of SoftPFReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 104015 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 104015 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 185850 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 185850 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 4109334 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 4109334 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 4718015 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 4718015 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 34673571058 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 34673571058 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 19854321886 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 19854321886 # number of WriteReq MSHR miss cycles
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-system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 13611528726 # number of SoftPFReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::cpu0.data 38259906745 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.WriteInvalidateReq_mshr_miss_latency::total 38259906745 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 1241876461 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 1241876461 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 3588911169 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 3588911169 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1889000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1889000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 54527892944 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 54527892944 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 68139421670 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 68139421670 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 2380477468 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2380477468 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2403593708 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2403593708 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4784071176 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4784071176 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.036163 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.036163 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017897 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017897 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.768722 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.768722 # mshr miss rate for SoftPFReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053668 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053668 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.095944 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.095944 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.027495 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.027495 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.031401 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.031401 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12208.887823 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12208.887823 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15641.859602 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15641.859602 # average WriteReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 22362.335486 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 22362.335486 # average SoftPFReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11939.397789 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11939.397789 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19310.794560 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19310.794560 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13269.277441 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13269.277441 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14442.391911 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14442.391911 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu0.toL2Bus.trans_dist::ReadReq 12330313 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadResp 9009509 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteReq 16126 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteResp 16126 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::Writeback 2894821 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::HardPFReq 3465295 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 858515 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeReq 371533 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 344881 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeResp 439023 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 61 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExReq 1234519 # Transaction distribution
-system.cpu0.toL2Bus.trans_dist::ReadExResp 1094177 # Transaction distribution
-system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 9758864 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 14862906 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 296442 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 542592 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_count::total 25460804 # Packet count per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 309696148 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 543504195 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1062208 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1873320 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.pkt_size::total 856135871 # Cumulative packet size per connected master and slave (bytes)
-system.cpu0.toL2Bus.snoops 8448176 # Total snoops (count)
-system.cpu0.toL2Bus.snoop_fanout::samples 22253887 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::mean 5.367543 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::stdev 0.482136 # Request fanout histogram
+system.cpu0.toL2Bus.trans_dist::ReadReq 12709886 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadResp 9530898 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteReq 15163 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteResp 15163 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::Writeback 3048439 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::HardPFReq 3732092 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::WriteInvalidateResp 887570 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeReq 380241 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 351950 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeResp 457079 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 47 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExReq 1289201 # Transaction distribution
+system.cpu0.toL2Bus.trans_dist::ReadExResp 1150842 # Transaction distribution
+system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 10359832 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 15601688 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 325277 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 566209 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_count::total 26853006 # Packet count per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 328927124 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 571100341 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 1168576 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 1949568 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.pkt_size::total 903145609 # Cumulative packet size per connected master and slave (bytes)
+system.cpu0.toL2Bus.snoops 8562261 # Total snoops (count)
+system.cpu0.toL2Bus.snoop_fanout::samples 23134597 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::mean 5.358060 # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::stdev 0.479430 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::5 14074632 63.25% 63.25% # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::6 8179255 36.75% 100.00% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::5 14851033 64.19% 64.19% # Request fanout histogram
+system.cpu0.toL2Bus.snoop_fanout::6 8283564 35.81% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu0.toL2Bus.snoop_fanout::total 22253887 # Request fanout histogram
-system.cpu0.toL2Bus.reqLayer0.occupancy 10836211781 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoop_fanout::total 23134597 # Request fanout histogram
+system.cpu0.toL2Bus.reqLayer0.occupancy 11405856452 # Layer occupancy (ticks)
system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.snoopLayer0.occupancy 180026995 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.snoopLayer0.occupancy 183601993 # Layer occupancy (ticks)
system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer0.occupancy 7309068550 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer0.occupancy 7759954717 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer1.occupancy 7654516797 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer1.occupancy 8048372726 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer2.occupancy 164187799 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer2.occupancy 179758799 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu0.toL2Bus.respLayer3.occupancy 308745047 # Layer occupancy (ticks)
+system.cpu0.toL2Bus.respLayer3.occupancy 322845049 # Layer occupancy (ticks)
system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
-system.cpu1.dtb.read_hits 85169560 # DTB read hits
-system.cpu1.dtb.read_misses 81568 # DTB read misses
-system.cpu1.dtb.write_hits 77252621 # DTB write hits
-system.cpu1.dtb.write_misses 28177 # DTB write misses
+system.cpu1.dtb.read_hits 81769828 # DTB read hits
+system.cpu1.dtb.read_misses 79673 # DTB read misses
+system.cpu1.dtb.write_hits 74311746 # DTB write hits
+system.cpu1.dtb.write_misses 27355 # DTB write misses
system.cpu1.dtb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries 42405 # Number of entries that have been flushed from TLB
+system.cpu1.dtb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.dtb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
+system.cpu1.dtb.flush_entries 41105 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults 4822 # Number of TLB faults due to prefetch
+system.cpu1.dtb.prefetch_faults 4547 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults 11145 # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses 85251128 # DTB read accesses
-system.cpu1.dtb.write_accesses 77280798 # DTB write accesses
+system.cpu1.dtb.perms_faults 10770 # Number of TLB faults due to permissions restrictions
+system.cpu1.dtb.read_accesses 81849501 # DTB read accesses
+system.cpu1.dtb.write_accesses 74339101 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu1.dtb.hits 162422181 # DTB hits
-system.cpu1.dtb.misses 109745 # DTB misses
-system.cpu1.dtb.accesses 162531926 # DTB accesses
+system.cpu1.dtb.hits 156081574 # DTB hits
+system.cpu1.dtb.misses 107028 # DTB misses
+system.cpu1.dtb.accesses 156188602 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
-system.cpu1.itb.inst_hits 451299133 # ITB inst hits
-system.cpu1.itb.inst_misses 60868 # ITB inst misses
+system.cpu1.itb.inst_hits 434473512 # ITB inst hits
+system.cpu1.itb.inst_misses 57336 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 14 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid 41415 # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid 1036 # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries 29689 # Number of entries that have been flushed from TLB
+system.cpu1.itb.flush_tlb_mva_asid 41884 # Number of times TLB was flushed by MVA & ASID
+system.cpu1.itb.flush_tlb_asid 1051 # Number of times TLB was flushed by ASID
+system.cpu1.itb.flush_entries 28749 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
-system.cpu1.itb.inst_accesses 451360001 # ITB inst accesses
-system.cpu1.itb.hits 451299133 # DTB hits
-system.cpu1.itb.misses 60868 # DTB misses
-system.cpu1.itb.accesses 451360001 # DTB accesses
-system.cpu1.numCycles 94876549324 # number of cpu cycles simulated
+system.cpu1.itb.inst_accesses 434530848 # ITB inst accesses
+system.cpu1.itb.hits 434473512 # DTB hits
+system.cpu1.itb.misses 57336 # DTB misses
+system.cpu1.itb.accesses 434530848 # DTB accesses
+system.cpu1.numCycles 95132031696 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 450991688 # Number of instructions committed
-system.cpu1.committedOps 531140635 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 488008709 # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses 470535 # Number of float alu accesses
-system.cpu1.num_func_calls 27052635 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 68722135 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 488008709 # number of integer instructions
-system.cpu1.num_fp_insts 470535 # number of float instructions
-system.cpu1.num_int_register_reads 711965253 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 387496587 # number of times the integer registers were written
-system.cpu1.num_fp_register_reads 748074 # number of times the floating registers were read
-system.cpu1.num_fp_register_writes 424948 # number of times the floating registers were written
-system.cpu1.num_cc_register_reads 118082190 # number of times the CC registers were read
-system.cpu1.num_cc_register_writes 117761356 # number of times the CC registers were written
-system.cpu1.num_mem_refs 162414438 # number of memory refs
-system.cpu1.num_load_insts 85168501 # Number of load instructions
-system.cpu1.num_store_insts 77245937 # Number of store instructions
-system.cpu1.num_idle_cycles 93789094629.720032 # Number of idle cycles
-system.cpu1.num_busy_cycles 1087454694.279977 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.011462 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.988538 # Percentage of idle cycles
-system.cpu1.Branches 100614893 # Number of branches fetched
-system.cpu1.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
-system.cpu1.op_class::IntAlu 367777606 69.20% 69.20% # Class of executed instruction
-system.cpu1.op_class::IntMult 1128259 0.21% 69.42% # Class of executed instruction
-system.cpu1.op_class::IntDiv 59926 0.01% 69.43% # Class of executed instruction
-system.cpu1.op_class::FloatAdd 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::FloatCmp 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::FloatCvt 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::FloatMult 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::FloatDiv 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::FloatSqrt 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdAdd 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdAddAcc 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdAlu 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdCmp 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdCvt 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdMisc 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdMult 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdMultAcc 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdShift 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdSqrt 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.43% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMisc 67918 0.01% 69.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMult 0 0.00% 69.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.44% # Class of executed instruction
-system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.44% # Class of executed instruction
-system.cpu1.op_class::MemRead 85168501 16.03% 85.47% # Class of executed instruction
-system.cpu1.op_class::MemWrite 77245937 14.53% 100.00% # Class of executed instruction
+system.cpu1.committedInsts 434160856 # Number of instructions committed
+system.cpu1.committedOps 511722288 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 470175639 # Number of integer alu accesses
+system.cpu1.num_fp_alu_accesses 456535 # Number of float alu accesses
+system.cpu1.num_func_calls 26230713 # number of times a function call or return occured
+system.cpu1.num_conditional_control_insts 66122636 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 470175639 # number of integer instructions
+system.cpu1.num_fp_insts 456535 # number of float instructions
+system.cpu1.num_int_register_reads 688104482 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 373632663 # number of times the integer registers were written
+system.cpu1.num_fp_register_reads 726332 # number of times the floating registers were read
+system.cpu1.num_fp_register_writes 408756 # number of times the floating registers were written
+system.cpu1.num_cc_register_reads 113709240 # number of times the CC registers were read
+system.cpu1.num_cc_register_writes 113476936 # number of times the CC registers were written
+system.cpu1.num_mem_refs 156073929 # number of memory refs
+system.cpu1.num_load_insts 81768358 # Number of load instructions
+system.cpu1.num_store_insts 74305571 # Number of store instructions
+system.cpu1.num_idle_cycles 94082707842.004028 # Number of idle cycles
+system.cpu1.num_busy_cycles 1049323853.995978 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.011030 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.988970 # Percentage of idle cycles
+system.cpu1.Branches 96877428 # Number of branches fetched
+system.cpu1.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction
+system.cpu1.op_class::IntAlu 354755827 69.28% 69.28% # Class of executed instruction
+system.cpu1.op_class::IntMult 1081291 0.21% 69.49% # Class of executed instruction
+system.cpu1.op_class::IntDiv 57437 0.01% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatAdd 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatCmp 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatCvt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatDiv 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::FloatSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAdd 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAddAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdAlu 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdCmp 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdCvt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMisc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMult 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdMultAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdShift 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdShiftAcc 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdSqrt 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAdd 8 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatAlu 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCmp 13 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatCvt 21 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatDiv 0 0.00% 69.51% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMisc 66526 0.01% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMult 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::SimdFloatSqrt 0 0.00% 69.52% # Class of executed instruction
+system.cpu1.op_class::MemRead 81768358 15.97% 85.49% # Class of executed instruction
+system.cpu1.op_class::MemWrite 74305571 14.51% 100.00% # Class of executed instruction
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
-system.cpu1.op_class::total 531448189 # Class of executed instruction
+system.cpu1.op_class::total 512035053 # Class of executed instruction
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 13727 # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements 5018265 # number of replacements
-system.cpu1.icache.tags.tagsinuse 496.292950 # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs 446280351 # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs 5018777 # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs 88.922132 # Average number of references to valid blocks.
+system.cpu1.kern.inst.quiesce 13728 # number of quiesce instructions executed
+system.cpu1.dcache.tags.replacements 5229569 # number of replacements
+system.cpu1.dcache.tags.tagsinuse 446.555743 # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs 150635340 # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs 5230081 # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs 28.801722 # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle 8374220312000 # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.occ_blocks::cpu1.data 446.555743 # Average occupied blocks per requestor
+system.cpu1.dcache.tags.occ_percent::cpu1.data 0.872179 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total 0.872179 # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::1 408 # Occupied blocks per task id
+system.cpu1.dcache.tags.age_task_id_blocks_1024::2 37 # Occupied blocks per task id
+system.cpu1.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
+system.cpu1.dcache.tags.tag_accesses 317363377 # Number of tag accesses
+system.cpu1.dcache.tags.data_accesses 317363377 # Number of data accesses
+system.cpu1.dcache.ReadReq_hits::cpu1.data 76086699 # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total 76086699 # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 70396756 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total 70396756 # number of WriteReq hits
+system.cpu1.dcache.SoftPFReq_hits::cpu1.data 188905 # number of SoftPFReq hits
+system.cpu1.dcache.SoftPFReq_hits::total 188905 # number of SoftPFReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 685307 # number of WriteInvalidateReq hits
+system.cpu1.dcache.WriteInvalidateReq_hits::total 685307 # number of WriteInvalidateReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1701097 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::total 1701097 # number of LoadLockedReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1676869 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::total 1676869 # number of StoreCondReq hits
+system.cpu1.dcache.demand_hits::cpu1.data 146483455 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total 146483455 # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data 146672360 # number of overall hits
+system.cpu1.dcache.overall_hits::total 146672360 # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data 2949268 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total 2949268 # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 1324938 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total 1324938 # number of WriteReq misses
+system.cpu1.dcache.SoftPFReq_misses::cpu1.data 648778 # number of SoftPFReq misses
+system.cpu1.dcache.SoftPFReq_misses::total 648778 # number of SoftPFReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 170596 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::total 170596 # number of LoadLockedReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 193531 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::total 193531 # number of StoreCondReq misses
+system.cpu1.dcache.demand_misses::cpu1.data 4274206 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total 4274206 # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data 4922984 # number of overall misses
+system.cpu1.dcache.overall_misses::total 4922984 # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 43925732439 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 43925732439 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 22816644952 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 22816644952 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2487645065 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 2487645065 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4103865813 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 4103865813 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1896000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1896000 # number of StoreCondFailReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 66742377391 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 66742377391 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 66742377391 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 66742377391 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 79035967 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total 79035967 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 71721694 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total 71721694 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 837683 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.SoftPFReq_accesses::total 837683 # number of SoftPFReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 685307 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.WriteInvalidateReq_accesses::total 685307 # number of WriteInvalidateReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1871693 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::total 1871693 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1870400 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::total 1870400 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data 150757661 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total 150757661 # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 151595344 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total 151595344 # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037316 # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_miss_rate::total 0.037316 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018473 # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::total 0.018473 # miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.774491 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_miss_rate::total 0.774491 # miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.091145 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.091145 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.103470 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::total 0.103470 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028352 # miss rate for demand accesses
+system.cpu1.dcache.demand_miss_rate::total 0.028352 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032475 # miss rate for overall accesses
+system.cpu1.dcache.overall_miss_rate::total 0.032475 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14893.774468 # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_miss_latency::total 14893.774468 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17220.915207 # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::total 17220.915207 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14582.083197 # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14582.083197 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21205.211635 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21205.211635 # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15615.152239 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 15615.152239 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13557.301302 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 13557.301302 # average overall miss latency
+system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
+system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
+system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.dcache.fast_writes 685307 # number of fast writes performed
+system.cpu1.dcache.cache_copies 0 # number of cache copies performed
+system.cpu1.dcache.writebacks::writebacks 2978181 # number of writebacks
+system.cpu1.dcache.writebacks::total 2978181 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 23865 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 23865 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 515 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 515 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45192 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45192 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 24380 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 24380 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 24380 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 24380 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 2925403 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 2925403 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1324423 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 1324423 # number of WriteReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 648778 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.SoftPFReq_mshr_misses::total 648778 # number of SoftPFReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 125404 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 125404 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 193531 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 193531 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 4249826 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 4249826 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 4898604 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 4898604 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 36900792539 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 36900792539 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20082419307 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20082419307 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 13833136236 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 13833136236 # number of SoftPFReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 30583171682 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 30583171682 # number of WriteInvalidateReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1453819204 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1453819204 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3706136187 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3706136187 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1808000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1808000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 56983211846 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 56983211846 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 70816348082 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 70816348082 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 4114514480 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 4114514480 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3994198470 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3994198470 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 8108712950 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 8108712950 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.037014 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.037014 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018466 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018466 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.774491 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.774491 # mshr miss rate for SoftPFReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.067000 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.067000 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.103470 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.103470 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028190 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.028190 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032314 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.032314 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12613.917651 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12613.917651 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15163.145994 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 15163.145994 # average WriteReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21321.833102 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21321.833102 # average SoftPFReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11593.084782 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11593.084782 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19150.090616 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19150.090616 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13408.363506 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13408.363506 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14456.434544 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14456.434544 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
+system.cpu1.icache.tags.replacements 4838786 # number of replacements
+system.cpu1.icache.tags.tagsinuse 496.335132 # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs 429634209 # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs 4839298 # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs 88.780275 # Average number of references to valid blocks.
system.cpu1.icache.tags.warmup_cycle 8374030789000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.tags.occ_blocks::cpu1.inst 496.292950 # Average occupied blocks per requestor
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system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
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system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left
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system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 3918463269 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 3926347769 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 3819021030 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 3819021030 # number of WriteReq MSHR uncacheable cycles
system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7884500 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7407620792 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7415505292 # number of overall MSHR uncacheable cycles
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.265289 # mshr miss rate for ReadReq accesses
-system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.129145 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 7737484299 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 7745368799 # number of overall MSHR uncacheable cycles
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.266099 # mshr miss rate for ReadReq accesses
+system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.129452 # mshr miss rate for ReadReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.565556 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.565556 # mshr miss rate for UpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.811678 # mshr miss rate for SCUpgradeReq accesses
-system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.811678 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.578701 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.578701 # mshr miss rate for UpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.815424 # mshr miss rate for SCUpgradeReq accesses
+system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.815424 # mshr miss rate for SCUpgradeReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses
system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.189407 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.189407 # mshr miss rate for ReadExReq accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.247519 # mshr miss rate for demand accesses
-system.cpu1.l2cache.demand_mshr_miss_rate::total 0.135922 # mshr miss rate for demand accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.053021 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077445 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030514 # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.247519 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.193898 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.193898 # mshr miss rate for ReadExReq accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.249149 # mshr miss rate for demand accesses
+system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136730 # mshr miss rate for demand accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.054068 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.079520 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.030092 # mshr miss rate for overall accesses
+system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.249149 # mshr miss rate for overall accesses
system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses
-system.cpu1.l2cache.overall_mshr_miss_rate::total 0.377310 # mshr miss rate for overall accesses
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25744.677294 # average ReadReq mshr miss latency
-system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25571.323344 # average ReadReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365 # average HardPFReq mshr miss latency
-system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29486.100365 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.overall_mshr_miss_rate::total 0.375030 # mshr miss rate for overall accesses
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 25591.835763 # average ReadReq mshr miss latency
+system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 25462.426584 # average ReadReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721 # average HardPFReq mshr miss latency
+system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 29673.692721 # average HardPFReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
system.cpu1.l2cache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17259.392339 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17259.392339 # average UpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13963.073546 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13963.073546 # average SCUpgradeReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 229562.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 229562.500000 # average SCUpgradeFailReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36178.155824 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36178.155824 # average ReadExReq mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27614.347108 # average overall mshr miss latency
-system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27233.457341 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38969.985947 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 55683.057689 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 21007.174994 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27614.347108 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29486.100365 # average overall mshr miss latency
-system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28674.608848 # average overall mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17297.056375 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17297.056375 # average UpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13909.668705 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13909.668705 # average SCUpgradeReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 242666.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 242666.500000 # average SCUpgradeFailReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36130.949722 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36130.949722 # average ReadExReq mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27517.274791 # average overall mshr miss latency
+system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 27171.053118 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 38635.792578 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 58242.408609 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20916.075530 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27517.274791 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 29673.692721 # average overall mshr miss latency
+system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28761.268269 # average overall mshr miss latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements 5412769 # number of replacements
-system.cpu1.dcache.tags.tagsinuse 455.628997 # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs 156797756 # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs 5413278 # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs 28.965399 # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle 8374220312000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.tags.occ_blocks::cpu1.data 455.628997 # Average occupied blocks per requestor
-system.cpu1.dcache.tags.occ_percent::cpu1.data 0.889900 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total 0.889900 # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_task_id_blocks::1024 509 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::1 353 # Occupied blocks per task id
-system.cpu1.dcache.tags.age_task_id_blocks_1024::2 81 # Occupied blocks per task id
-system.cpu1.dcache.tags.occ_task_id_percent::1024 0.994141 # Percentage of cache occupancy per task id
-system.cpu1.dcache.tags.tag_accesses 330228848 # Number of tag accesses
-system.cpu1.dcache.tags.data_accesses 330228848 # Number of data accesses
-system.cpu1.dcache.ReadReq_hits::cpu1.data 79329783 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 79329783 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::cpu1.data 73242746 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 73242746 # number of WriteReq hits
-system.cpu1.dcache.SoftPFReq_hits::cpu1.data 190572 # number of SoftPFReq hits
-system.cpu1.dcache.SoftPFReq_hits::total 190572 # number of SoftPFReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::cpu1.data 704958 # number of WriteInvalidateReq hits
-system.cpu1.dcache.WriteInvalidateReq_hits::total 704958 # number of WriteInvalidateReq hits
-system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 1728485 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 1728485 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::cpu1.data 1710118 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 1710118 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::cpu1.data 152572529 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 152572529 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::cpu1.data 152763101 # number of overall hits
-system.cpu1.dcache.overall_hits::total 152763101 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::cpu1.data 3054941 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 3054941 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::cpu1.data 1365411 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 1365411 # number of WriteReq misses
-system.cpu1.dcache.SoftPFReq_misses::cpu1.data 663261 # number of SoftPFReq misses
-system.cpu1.dcache.SoftPFReq_misses::total 663261 # number of SoftPFReq misses
-system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 178994 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 178994 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::cpu1.data 196091 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 196091 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::cpu1.data 4420352 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 4420352 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::cpu1.data 5083613 # number of overall misses
-system.cpu1.dcache.overall_misses::total 5083613 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 45633904603 # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_latency::total 45633904603 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 23251947701 # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency::total 23251947701 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 2574333319 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency::total 2574333319 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 4154245626 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency::total 4154245626 # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 2386500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.StoreCondFailReq_miss_latency::total 2386500 # number of StoreCondFailReq miss cycles
-system.cpu1.dcache.demand_miss_latency::cpu1.data 68885852304 # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_latency::total 68885852304 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency::cpu1.data 68885852304 # number of overall miss cycles
-system.cpu1.dcache.overall_miss_latency::total 68885852304 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::cpu1.data 82384724 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 82384724 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::cpu1.data 74608157 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 74608157 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 853833 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.SoftPFReq_accesses::total 853833 # number of SoftPFReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::cpu1.data 704958 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.WriteInvalidateReq_accesses::total 704958 # number of WriteInvalidateReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 1907479 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 1907479 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 1906209 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 1906209 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::cpu1.data 156992881 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 156992881 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::cpu1.data 157846714 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 157846714 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.037081 # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_miss_rate::total 0.037081 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.018301 # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::total 0.018301 # miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.776804 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_miss_rate::total 0.776804 # miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.093838 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.093838 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.102870 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::total 0.102870 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::cpu1.data 0.028156 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total 0.028156 # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::cpu1.data 0.032206 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total 0.032206 # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14937.736802 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total 14937.736802 # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 17029.266427 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total 17029.266427 # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14382.232471 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14382.232471 # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 21185.294715 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 21185.294715 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15583.793396 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total 15583.793396 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13550.569704 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 13550.569704 # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 704958 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks::writebacks 3078594 # number of writebacks
-system.cpu1.dcache.writebacks::total 3078594 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 23839 # number of ReadReq MSHR hits
-system.cpu1.dcache.ReadReq_mshr_hits::total 23839 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 436 # number of WriteReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits::total 436 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 45139 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits::total 45139 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits::cpu1.data 24275 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_hits::total 24275 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits::cpu1.data 24275 # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_hits::total 24275 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 3031102 # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_misses::total 3031102 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 1364975 # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses::total 1364975 # number of WriteReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 663261 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.SoftPFReq_mshr_misses::total 663261 # number of SoftPFReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 133855 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses::total 133855 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 196002 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses::total 196002 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses::cpu1.data 4396077 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.demand_mshr_misses::total 4396077 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses::cpu1.data 5059338 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_misses::total 5059338 # number of overall MSHR misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 38375786357 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_latency::total 38375786357 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 20437608309 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency::total 20437608309 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 14184435008 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 14184435008 # number of SoftPFReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::cpu1.data 31455228300 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.WriteInvalidateReq_mshr_miss_latency::total 31455228300 # number of WriteInvalidateReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 1522508206 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 1522508206 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 3750879374 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 3750879374 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 2276500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 2276500 # number of StoreCondFailReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 58813394666 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency::total 58813394666 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 72997829674 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency::total 72997829674 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3974280487 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3974280487 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 3786981721 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 3786981721 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 7761262208 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency::total 7761262208 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.036792 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.036792 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.018295 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.018295 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.776804 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.776804 # mshr miss rate for SoftPFReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.070174 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.070174 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.102823 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.102823 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.028002 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total 0.028002 # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.032052 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total 0.032052 # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12660.671385 # average ReadReq mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12660.671385 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14972.881048 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14972.881048 # average WriteReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 21385.902394 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 21385.902394 # average SoftPFReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11374.309559 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11374.309559 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 19136.944388 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 19136.944388 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 13378.608852 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 13378.608852 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14428.336212 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 14428.336212 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.toL2Bus.trans_dist::ReadReq 12531191 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadResp 9460246 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteReq 22034 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteResp 22034 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::Writeback 3078590 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::HardPFReq 3649719 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1670210 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 704958 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeReq 365743 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 350744 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeResp 452026 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 55 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 102 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExReq 1320531 # Transaction distribution
-system.cpu1.toL2Bus.trans_dist::ReadExResp 1177447 # Transaction distribution
-system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 10037784 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15516501 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 332477 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 559655 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_count::total 26446417 # Packet count per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 321202488 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 568398888 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1205080 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1932672 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.pkt_size::total 892739128 # Cumulative packet size per connected master and slave (bytes)
-system.cpu1.toL2Bus.snoops 8517318 # Total snoops (count)
-system.cpu1.toL2Bus.snoop_fanout::samples 22943145 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::mean 5.359651 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::stdev 0.479898 # Request fanout histogram
+system.cpu1.toL2Bus.trans_dist::ReadReq 12427806 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadResp 9137324 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteReq 23353 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteResp 23353 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::Writeback 2978176 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::HardPFReq 3478890 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::WriteInvalidateResp 685307 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeReq 370922 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 353849 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeResp 446809 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 42 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExReq 1290596 # Transaction distribution
+system.cpu1.toL2Bus.trans_dist::ReadExResp 1141918 # Transaction distribution
+system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 9678826 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 15042396 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 312565 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 544877 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_count::total 25578664 # Packet count per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 309715832 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 550341480 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 1128872 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 1873928 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.pkt_size::total 863060112 # Cumulative packet size per connected master and slave (bytes)
+system.cpu1.toL2Bus.snoops 8621982 # Total snoops (count)
+system.cpu1.toL2Bus.snoop_fanout::samples 22555543 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::mean 5.370325 # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::stdev 0.482892 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::5 14691626 64.03% 64.03% # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::6 8251519 35.97% 100.00% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::5 14202655 62.97% 62.97% # Request fanout histogram
+system.cpu1.toL2Bus.snoop_fanout::6 8352888 37.03% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
-system.cpu1.toL2Bus.snoop_fanout::total 22943145 # Request fanout histogram
-system.cpu1.toL2Bus.reqLayer0.occupancy 11163844442 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoop_fanout::total 22555543 # Request fanout histogram
+system.cpu1.toL2Bus.reqLayer0.occupancy 10801104660 # Layer occupancy (ticks)
system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.snoopLayer0.occupancy 175587993 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.snoopLayer0.occupancy 179932994 # Layer occupancy (ticks)
system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer0.occupancy 7529809391 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer0.occupancy 7260511142 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer1.occupancy 8141370258 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer1.occupancy 7881710673 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer2.occupancy 182479297 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer2.occupancy 172097315 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
-system.cpu1.toL2Bus.respLayer3.occupancy 318532791 # Layer occupancy (ticks)
+system.cpu1.toL2Bus.respLayer3.occupancy 311084554 # Layer occupancy (ticks)
system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
-system.iocache.tags.replacements 115665 # number of replacements
-system.iocache.tags.tagsinuse 11.304646 # Cycle average of tags in use
+system.iobus.trans_dist::ReadReq 40536 # Transaction distribution
+system.iobus.trans_dist::ReadResp 40536 # Transaction distribution
+system.iobus.trans_dist::WriteReq 137093 # Transaction distribution
+system.iobus.trans_dist::WriteResp 137147 # Transaction distribution
+system.iobus.trans_dist::WriteInvalidateReq 54 # Transaction distribution
+system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 48328 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 14 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 24 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 29808 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 44750 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.bridge.master::total 123470 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 231816 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ide.dma::total 231816 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::system.iocache.cpu_side 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count_system.realview.ethernet.dma::total 80 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_count::total 355366 # Packet count per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 48348 # Cumulative packet size per connected master and slave (bytes)
+system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 28 # Cumulative packet size per connected master and slave (bytes)
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 68750.422753 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 86643.281052 # average ReadReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu0.data inf # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::cpu1.data inf # average WriteInvalidateReq mshr miss latency
+system.l2c.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10142.632657 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10141.107364 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10141.851172 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10200.351061 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10246.258345 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10223.680335 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 60526.959717 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 60673.140768 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 60597.130583 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 65791.319642 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 66008.041044 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 83682.306474 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67118.727173 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 67539.616975 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 76498.485419 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 65791.319642 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 92332.453986 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66746.287129 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 66891.837941 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76266.227305 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 66008.041044 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 93876.759003 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 83682.306474 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.membus.trans_dist::ReadReq 1264717 # Transaction distribution
+system.membus.trans_dist::ReadResp 1264717 # Transaction distribution
+system.membus.trans_dist::WriteReq 38516 # Transaction distribution
+system.membus.trans_dist::WriteResp 38516 # Transaction distribution
+system.membus.trans_dist::Writeback 686491 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateReq 1679861 # Transaction distribution
+system.membus.trans_dist::WriteInvalidateResp 1679861 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 316703 # Transaction distribution
+system.membus.trans_dist::SCUpgradeReq 302467 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 96183 # Transaction distribution
+system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution
+system.membus.trans_dist::ReadExReq 163141 # Transaction distribution
+system.membus.trans_dist::ReadExResp 147161 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 123470 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 92 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 25330 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 7297543 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.l2c.mem_side::total 7446435 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 230140 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count_system.iocache.mem_side::total 230140 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 7676575 # Packet count per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 156485 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 204 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 50660 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 229346740 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.l2c.mem_side::total 229554089 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 7308288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size_system.iocache.mem_side::total 7308288 # Cumulative packet size per connected master and slave (bytes)
+system.membus.pkt_size::total 236862377 # Cumulative packet size per connected master and slave (bytes)
+system.membus.snoops 540732 # Total snoops (count)
+system.membus.snoop_fanout::samples 4331622 # Request fanout histogram
+system.membus.snoop_fanout::mean 1 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::1 4331622 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 1 # Request fanout histogram
+system.membus.snoop_fanout::max_value 1 # Request fanout histogram
+system.membus.snoop_fanout::total 4331622 # Request fanout histogram
+system.membus.reqLayer0.occupancy 101146499 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer1.occupancy 55000 # Layer occupancy (ticks)
+system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer2.occupancy 22031996 # Layer occupancy (ticks)
+system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.reqLayer5.occupancy 23154905719 # Layer occupancy (ticks)
+system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer2.occupancy 14237686781 # Layer occupancy (ticks)
+system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
+system.membus.respLayer3.occupancy 187996205 # Layer occupancy (ticks)
+system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
+system.realview.ethernet.txBytes 966 # Bytes Transmitted
+system.realview.ethernet.txPackets 3 # Number of Packets Transmitted
+system.realview.ethernet.txIpChecksums 0 # Number of tx IP Checksums done by device
+system.realview.ethernet.txTcpChecksums 0 # Number of tx TCP Checksums done by device
+system.realview.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device
+system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
+system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
+system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
+system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
+system.realview.ethernet.totBandwidth 162 # Total Bandwidth (bits/s)
+system.realview.ethernet.totPackets 3 # Total Packets
+system.realview.ethernet.totBytes 966 # Total Bytes
+system.realview.ethernet.totPPS 0 # Total Tranmission Rate (packets/s)
+system.realview.ethernet.txBandwidth 162 # Transmit Bandwidth (bits/s)
+system.realview.ethernet.txPPS 0 # Packet Tranmission Rate (packets/s)
+system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
+system.realview.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post
+system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
+system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post
+system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
+system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
+system.realview.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post
+system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
+system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post
+system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
+system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
+system.realview.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post
+system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
+system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
+system.realview.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post
+system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
+system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
+system.realview.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post
+system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
+system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
+system.realview.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post
+system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
+system.realview.ethernet.coalescedTotal 0 # average number of interrupts coalesced into each post
+system.realview.ethernet.postedInterrupts 13 # number of posts to CPU
+system.realview.ethernet.droppedPackets 0 # number of packets dropped
+system.toL2Bus.trans_dist::ReadReq 6727338 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 6719778 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 38516 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 38516 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 1994497 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateReq 1679869 # Transaction distribution
+system.toL2Bus.trans_dist::WriteInvalidateResp 1572877 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 365008 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeReq 318091 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 683099 # Transaction distribution
+system.toL2Bus.trans_dist::SCUpgradeFailReq 80 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeFailResp 80 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 301724 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 301724 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 10020344 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 9267363 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 19287707 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 322818441 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 297911776 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.pkt_size::total 620730217 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.snoops 1454894 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 11304872 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.010257 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 0.100757 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 11188916 98.97% 98.97% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 115956 1.03% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 11304872 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 19960086799 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.snoopLayer0.occupancy 6306000 # Layer occupancy (ticks)
+system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 16653624789 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 15972471023 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
---------- End Simulation Statistics ----------
projects / gem5.git / commitdiff