Signed-off-by: Clifford Wolf <clifford@clifford.at>
smtbmc
[script]
-read_verilog -formal demo.v
+read -formal demo.sv
prep -top demo
[files]
-demo.v
+demo.sv
--- /dev/null
+module demo (
+ input clk,
+ output [5:0] counter
+);
+ reg [5:0] counter = 0;
+
+ always @(posedge clk) begin
+ if (counter == 50)
+ counter <= 0;
+ else
+ counter <= counter + 1;
+ end
+
+`ifdef FORMAL
+ always @(posedge clk) begin
+ assert (counter < 32);
+ end
+`endif
+endmodule
+++ /dev/null
-module demo (
- input clk,
- output [5:0] counter
-);
- reg [5:0] counter = 0;
-
- always @(posedge clk) begin
- if (counter == 15)
- counter <= 0;
- else
- counter <= counter + 1;
- end
-
- assert property (counter < 32);
-endmodule
Here is a simple example design with a safety property (assertion).
-.. literalinclude:: ../examples/quickstart/demo.v
+.. literalinclude:: ../examples/quickstart/demo.sv
:language: systemverilog
The property in this example is true. We'd like to verify this using a bounded
.. literalinclude:: ../examples/quickstart/demo.sby
:language: text
-Simply create a text file ``demo.v`` with the example design and another text
+Simply create a text file ``demo.sv`` with the example design and another text
file ``demo.sby`` with the SymbiYosys configuration. Then run::
sby demo.sby