Fix simulation to support diff pairs

diff --git a/gram/simulation/icarusecpix5platform.py b/gram/simulation/icarusecpix5platform.py
index cb0481f9d1cfd6c7d14dcccd78d5de34c8b14d21..d2155b2a72e1a7ac2516d4a6305cd9390d6b4776 100644 (file)
--- a/gram/simulation/icarusecpix5platform.py
+++ b/gram/simulation/icarusecpix5platform.py
@@ -28,15 +28,14 @@ class IcarusECPIX5Platform(LatticeECP5Platform):
 
         Resource("ddr3", 0,
                  Subsignal("clk", Pins("H3", dir="o")),
-                 #Subsignal("clk",    DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")),
+                 #Subsignal("clk", DiffPairs("H3", "J3", dir="o"), Attrs(IO_TYPE="SSTL135D_I")),
                  Subsignal("clk_en", Pins("P1", dir="o")),
                  Subsignal("we", PinsN("R3", dir="o")),
                  Subsignal("ras", PinsN("T3", dir="o")),
                  Subsignal("cas", PinsN("P2", dir="o")),
                  Subsignal("a", Pins("T5 M3 L3 V6 K2 W6 K3 L1 H2 L2 N1 J1 M1 K1", dir="o")),
                  Subsignal("ba", Pins("U6 N3 N4", dir="o")),
-                 #Subsignal("dqs",    DiffPairs("V4 V1", "U5 U2", dir="io"), Attrs(IO_TYPE="SSTL135D_I")),
-                 Subsignal("dqs", Pins("V4 V1", dir="io"), Attrs(IO_TYPE="SSTL135D_I", TERMINATION="OFF", DIFFRESISTOR="100")),
+                 Subsignal("dqs", DiffPairs("V4 V1", "U5 U2", dir="io"), Attrs(IO_TYPE="SSTL135D_I")),
                  Subsignal("dq", Pins("T4 W4 R4 W5 R6 P6 P5 P4 R1 W3 T2 V3 U3 W1 T1 W2", dir="io")),
                  Subsignal("dm", Pins("U4 U1", dir="o")),
                  Subsignal("odt", Pins("P3", dir="o")),

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index de800821ff287ae62cb270c69fb1e186b560eec8..a866cc0d3d41b086a8b32cbeec7a10344c591ec8 100644 (file)
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -79,7 +79,7 @@ module simsoctb;
   
   top simsoctop (
     .ddr3_0__dq__io(dram_dq),
-    .ddr3_0__dqs__io(dram_dqs),
+    .ddr3_0__dqs__p(dram_dqs),
     .ddr3_0__clk__io(dram_ck),
     .ddr3_0__clk_en__io(dram_cke),
     .ddr3_0__we__io(dram_we_n),