i965: Account for offsets when updating SURFACE_STATE.

If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 7f7b7ebe2b00c578ae609972cc29b185b3df02cb..e732b6d9b8e4f227db7d9169455c79fc040847a2 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -837,6 +837,7 @@ brw_update_texture_surface(struct gl_context *ctx,
    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
    uint32_t *surf;
    int width, height, depth;
+   uint32_t tile_x, tile_y;
 
    if (tObj->Target == GL_TEXTURE_BUFFER) {
       brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
@@ -870,7 +871,16 @@ brw_update_texture_surface(struct gl_context *ctx,
 
    surf[4] = 0;
 
-   surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0;
+   intel_miptree_get_tile_offsets(intelObj->mt, 0, 0, &tile_x, &tile_y);
+   assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
+   /* Note that the low bits of these fields are missing, so
+    * there's the possibility of getting in trouble.
+    */
+   assert(tile_x % 4 == 0);
+   assert(tile_y % 2 == 0);
+   surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
+             (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
+             (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0));
 
    /* Emit relocation to surface contents */
    drm_intel_bo_emit_reloc(brw->intel.batch.bo,

diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 236d50c8bc30c11255c4aef45f1464ca85ed53ef..9c8bc17d5cbf3c6627e6c5a1f91d9c6a9d5ba4a0 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -292,6 +292,7 @@ gen7_update_texture_surface(struct gl_context *ctx,
    struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel];
    struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
    int width, height, depth;
+   uint32_t tile_x, tile_y;
 
    if (tObj->Target == GL_TEXTURE_BUFFER) {
       gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index);
@@ -333,7 +334,15 @@ gen7_update_texture_surface(struct gl_context *ctx,
    surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) |
              ((intelObj->mt->region->pitch) - 1);
 
-   surf[5] = intelObj->_MaxLevel - tObj->BaseLevel; /* mip count */
+   intel_miptree_get_tile_offsets(intelObj->mt, 0, 0, &tile_x, &tile_y);
+   assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0));
+   /* Note that the low bits of these fields are missing, so
+    * there's the possibility of getting in trouble.
+    */
+   surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT |
+              (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT |
+              /* mip count */
+              (intelObj->_MaxLevel - tObj->BaseLevel));
 
    if (intel->is_haswell) {
       /* Handling GL_ALPHA as a surface format override breaks 1.30+ style