+CHIPSET(0x4c8a, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
+CHIPSET(0x4c8b, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
+CHIPSET(0x4c8c, rkl_gt05, "RKL GT0.5", "Intel(R) Graphics")
+CHIPSET(0x4c90, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
+CHIPSET(0x4c9a, rkl_gt1, "RKL GT1", "Intel(R) Graphics")
+
 CHIPSET(0x9A40, tgl_gt2, "TGL GT2", "Intel(R) Xe Graphics")
 CHIPSET(0x9A49, tgl_gt2, "TGL GT2", "Intel(R) Xe Graphics")
 CHIPSET(0x9A59, tgl_gt2, "TGL GT2", "Intel(R) Graphics")
 
    { "ehl", 0x4500 },
    { "jsl", 0x4E71 },
    { "tgl", 0x9a49 },
+   { "rkl", 0x4c8a },
 };
 
 /**
 
 #define dual_subslices(args...) { args, }
 
+#define GEN12_GT05_FEATURES                                     \
+   GEN12_FEATURES(1, 1, 4),                                     \
+   .num_subslices = dual_subslices(1)
+
 #define GEN12_GT_FEATURES(_gt)                                  \
    GEN12_FEATURES(1, 1, _gt == 1 ? 4 : 8),                      \
    .num_subslices = dual_subslices(_gt == 1 ? 2 : 6)
    GEN12_GT_FEATURES(2),
 };
 
+static const struct gen_device_info gen_device_info_rkl_gt05 = {
+   GEN12_GT05_FEATURES,
+};
+
+static const struct gen_device_info gen_device_info_rkl_gt1 = {
+   GEN12_GT_FEATURES(1),
+};
+
 static void
 gen_device_info_set_eu_mask(struct gen_device_info *devinfo,
                             unsigned slice,